What s New in HyperLynx 8.0

Size: px

Start display at page:

Download "What s New in HyperLynx 8.0"

Marjorie Johnson
5 years ago
Views:

2 What s New in HyperLynx 8.0 Copyright Mentor Graphics Corporation 2009 All Rights Reserved. Mentor Graphics, Board Station XE Flow, ViewDraw, Falcon Framework, IdeaStation, ICX and Tau are registered trademarks of Mentor Graphics Corporation. FPGA BoardLink, Design Capture, DesignView, TeamPCB, Expedition, Waveform Analyzer, BoardLink Pro, SymGen, CellGen, Library Manager, DxDesigner, Board Architect, and FPGA Xchange are trademarks of Mentor Graphics Corporation. All other products are the trademarks or registered trademarks of their respective owners.

3 Table of Contents What s New in HyperLynx HyperLynx HyperLynx PI...2 Setup Wizards...2 Pre- and Post-Layout Analysis...3 Pre-Layout Analysis...3 Post-Layout Analysis...4 Power Distribution Network Noise Analysis...5 DC Voltage Drop Analysis...6 Decoupling Analysis...7 Bypass Analysis...7 Improved Differential-Via Modeling...7 HyperLynx SI Enhancements...8 Improved Support of Advanced-Memory Interfaces (DDR2/3)...8 DDR Wizard...8 DDR2/DDR3 Wizard...9 Upgraded IBIS-Keyword Support...9 Upgraded IBIS-Keyword Support...10 Improvements Transmission Line Models...10 Coupling Transmission Lines...11 Touchstone Transformer Enhancements...11 Fast-Eye Simulation Improvements...12 Enhanced Multiboard Support...13 Oscilloscope Improvements...14 Simulation Sweeps...14 Simulation Sweeps...15 Per-Net / Per-Pin Stimulus...16 Re-Use of Stackups...17 Design and Technology Kits...17 Integration with Expedition Enterprise and Board Station XE...18 LineSim to CES Topology Templates...18 CES to LineSim...19 CES to BoardSim...19 DxDesigner to LineSim...20 Additional Operating System Support...20 What s New in HyperLynx 8.0 1

4 HyperLynx 8.0 This latest release of HyperLynx is the most comprehensive update in the history of the product. The most significant update is the addition of HyperLynx PI, the new Power Integrity analysis tool. Other additions include wizards to aid in rapid setup and execution of analysis parameters. Also, integration with Expedition Enterprise and Board Station XE has been enhanced, making transition from schematic environment to analysis environment much quicker and easier. Details of these, and all additions and enhancements, are in the following sections. HyperLynx PI HyperLynx PI is a significant new tool that provides the fastest time to accurate results. Present demands on PCB design often require several sometimes tens of different voltages on the same board. This means broken-up power planes that can create current density hot spots or increased voltage drop across the plane. Beyond that, the magnitude of the voltages (1.2 vdc or less) means that noise margins are very small. Thus, ensuring the integrity of board power is no longer possible using the old rules of thumb. Setup Wizards Because of the complexities of PI analysis, HyperLynx PI introduces an easy-to-use wizard environment from which to setup and run analysis suites. The image below illustrates the ease of stepping through the wizards to provide the necessary analysis output. This new wizard can cut test setup from hours or days, to just a few minutes. What s New in HyperLynx 8.0 2

Pre- and Post-Layout Analysis The further down the design path a project moves before discovering errors, the greater the cost to correct the error.

Pre-Layout Analysis Analysis with HyperLynx PI can begin prior to starting the actual layout. The Pre-layout editor allows physical PI scenarios to be entered and simulated.

5 Pre- and Post-Layout Analysis The further down the design path a project moves before discovering errors, the greater the cost to correct the error. Moving analysis as far towards the beginning of the project as possible results in significant cost savings. HyperLynx PI allows both pre-layout and post-layout analysis. Pre-Layout Analysis Analysis with HyperLynx PI can begin prior to starting the actual layout. The Pre-layout editor allows physical PI scenarios to be entered and simulated. For example, in the illustration a board outline with both a split and a void is proposed. The analysis can proceed, identifying problems and accurately determining the true number of decoupling capacitors required for the given power and speed requirements of the PCB. What s New in HyperLynx 8.0 3

For example, below, the vias proposed in the schematic are analyzed prior to layout to determine their effects on the board s power system.

6 All power integrity features are available for pre-layout use in addition to post-layout. This allows for detailed analysis very early in the design cycle and maximum what if? flexibility. For example, below, the vias proposed in the schematic are analyzed prior to layout to determine their effects on the board s power system. Post-Layout Analysis Once the layout has been finished, a completed power integrity analysis can be run prior to producing a prototype. Any issues can be corrected prior to spending any money on a first product. What s New in HyperLynx 8.0 4

Power Distribution Network Noise Analysis Locating and rectifying noise sources affecting the power distribution network (PDN) can be very difficult.

7 Power Distribution Network Noise Analysis Locating and rectifying noise sources affecting the power distribution network (PDN) can be very difficult. HyperLynx PI greatly simplifies the task and provides pin-point identification of trouble spots that need attention. Simulation uses current pulses to imitate the I/O, core, and block power-up/down current demand. The analysis includes effects of planes, decoupling capacitors, and stitching vias. The results are presented graphically as a detailed noise profile, shown below. What s New in HyperLynx 8.0 5

DC Voltage Drop Analysis With the continued use of very low DC voltages for some applications, the DC voltage drop along traces or voltage planes becomes critical.

8 DC Voltage Drop Analysis With the continued use of very low DC voltages for some applications, the DC voltage drop along traces or voltage planes becomes critical. No longer can even 100 mv of drop be tolerated on low voltage nets. Fragmented or discontinuous power planes can produce excessive DC currents in bottlenecks. In addition, the density of the metal, large pin fields, and vias can cause current density issues. Simple VRM and DC-load models are used to calculate the current density. The results are displayed graphically so that hot-spots can be easily located and corrected, as illustrated below. What s New in HyperLynx 8.0 6

Decoupling Analysis Decoupling capacitors are often placed using rules of thumb that may have been defined when there was just one voltage (or at most, just a few) and significantly slower switching

9 Decoupling Analysis Decoupling capacitors are often placed using rules of thumb that may have been defined when there was just one voltage (or at most, just a few) and significantly slower switching speeds. HyperLynx PI now allows for precise determination of the number, location, and capacitance of each bypass cap. The entire decoupling network is extracted and graphically presented as an impedance profile. Automatically included are the effects of capacitor mounting inductance, plane inductance, dielectric effects, and metal losses. Capacitors can be modeled several ways: with simple C-ESL-ESR, SPICE, or S-parameters. As illustrated below, the entire bypass analysis is wizard-driven, producing accurate results quickly and efficiently. Bypass Analysis Bypass analysis is very similar to decoupling analysis. However, instead of an impedance profile, bypass analysis shows the input impedance viewed from the location of signal vias. HyperLynx PI presents Z-parameter data, facilitating understanding the impedance effects. Or, the user can view S-parameters to understand loss effects, as shown below. Improved Differential-Via Modeling Differential-via modeling is enhanced in this release of HyperLynx. The new model includes common-mode effects, which are very important for differential signals with skew, or other problems that cause common-mode conversion. What s New in HyperLynx 8.0 7

10 HyperLynx SI Enhancements HyperLynx 8.0 introduces new signal integrity enhancements. These include transmission line model improvements, S-Parameter enhancements, improvements to Fast Eye Simulation including a new wizard environment for Fast Eye Diagrams, improved differential-via modeling, and a SERDES Design Kit Configurator. Improved Support of Advanced-Memory Interfaces (DDR2/3) Signal Integrity capabilities for support of advanced DDR, DDR2, and DDR3 devices are enhanced and made easier to use than even prior versions. The features are described in this section. Wizards now make using these devices quick and reasonably simple. This new support feature analyzes timing for both address and data buses. HyperLynx can produce measurements for clock-to-strobe skew, timing and signal integrity on all signal edges, and offers advanced crosstalk simulation. DDR Wizard The new wizard allows exceptionally quick setup of simulations, saving time and allowing many more simulations (and thus better accuracy) than other simulators. Parameters are easily set with sliders and menus. Associations are set up for clocks and address/control signals. Stimulus can be set by per-pin or per-net to support timing offsets. Read and write operations are configurable to eliminate wasted non-meaningful results. And, configurations can be saved to allow almost instant re-simulation using the same parameters. What s New in HyperLynx 8.0 8

DDR2/DDR3 Wizard The wizard also supports DDR3 timing alignment for clock and strobe signals, which is required for the new fly-by architecture.

11 DDR2/DDR3 Wizard The wizard also supports DDR3 timing alignment for clock and strobe signals, which is required for the new fly-by architecture. This provides comprehensive reports of timing results, including full timing and SI analysis with pass/fail for setup and hold times. Also included is DT de-rating for setup and hold times. The new function provides analysis for both data (source synchronous) and address/control signals (common clock). What s New in HyperLynx 8.0 9

Upgraded IBIS-Keyword Support Enhanced support for IBIS keywords is critical to advanced-memory simulation for receiver thresholds and model specifications.

12 Upgraded IBIS-Keyword Support Enhanced support for IBIS keywords is critical to advanced-memory simulation for receiver thresholds and model specifications. This data is automaticically used for batchmode simulation, and the measurements are made available in an interactive oscilloscope. Improvements Transmission Line Models Important improvements have been made to lossy transmission line simulation based on the best-available research regarding PCB dielectric modeling. These utilize the more accurate multi-pole Debye models, which now give ultra-wideband frequency (DC to > 50 GHz) support with completely correct low-frequency asymptotics, which is missing in many other simulators. In addition, support for modeling copper surface roughness has been added, which is critical for analysis of 6 Gbps and higher bit-rate signals. What s New in HyperLynx

Touchstone Transformer Enhancements Enhancements in S-parameter modeling include addition of a standalone, complex-pole fitter. This makes fitting S-parameter models more explicit and visible.

13 Coupling Transmission Lines Quickly and easily create coupled transmission line segments with this new feature. The user can select multiple transmission lines in a schematic, and then couple them together with a simple right-click of the mouse. Touchstone Transformer Enhancements Enhancements in S-parameter modeling include addition of a standalone, complex-pole fitter. This makes fitting S-parameter models more explicit and visible. Also a new wizard-driven transform application has been added. This allows easy setup of passivity and symetry enforcemenet, conversion between S/Y/Z parameters, conversion between standard and mixed parematers, S-parameter renormalization (for viewing), and safe port reduction with auto termination of eliminated ports. What s New in HyperLynx

Fast-Eye Simulation Improvements This release of HyperLynx features a number of new fast-eye features, including: sinusoidal deterministic jitter (can be used to model crosstalk, power-integrity

14 Fast-Eye Simulation Improvements This release of HyperLynx features a number of new fast-eye features, including: sinusoidal deterministic jitter (can be used to model crosstalk, power-integrity effects, etc.), receiver decision feedback equalization (DFE) and driver pre-emphasis, synthesis of optimal DFE and pre-emphasis, advanced jitter controls, and nested statistical eye contours to allow correlation of eye closing to probability of occurrence. Standalone Wizard/Flow for Fast Eye Diagrams Consistent with the thinking across all HyperLynx tools, Fast-Eye Simulation has been re-implemented in a standalone wizard. This new wizard gives more control of the simulation to the user. Mentor s FastEye solution is orders of magnitude faster than traditional simulation approaches, producing very fast and accurate results. The flow can be integrated with HyperLynx, or advanced users can run the flow from external files. The addition of the wizard makes the flow easier to understand and control. What s New in HyperLynx

Enhanced Multiboard Support Advanced connector models are supported in the Multiboard Wizard. This graphical editor performs model swathing.

15 Enhanced Multiboard Support Advanced connector models are supported in the Multiboard Wizard. This graphical editor performs model swathing. Its easy-to-use drag and drop feature makes connections between connectors fast and easy. Then, the model can be extracted and exported to LineSim. What s New in HyperLynx

Measurements have been improved to operate on multiple edges, and includes display of overshoot,

16 Oscilloscope Improvements There are a number of improvements to the oscilloscope function that makes it easier to use and presents more accurate data. Measurements have been improved to operate on multiple edges, and includes display of overshoot, flight time, and edge rates. The new functions include: Enable/Disable All Probes Import multiple saved waveforms What s New in HyperLynx

variety of LineSim or BoardSim interactive

lines or segments, passive component values, IC

The central sweep manager allows easy global

In pre-layout, simulation sweeps can be cross

17 Simulation Sweeps HyperLynx now has the capability to parametrically sweep a wide variety of LineSim or BoardSim interactive simulations, including stackups, transmission lines or segments, passive component values, IC corners, and IBIS model selectors. The central sweep manager allows easy global views and control of the sweep parameters. In pre-layout, simulation sweeps can be cross probed between the sweeps manager selection and schematic in LineSim. What s New in HyperLynx

18 Per-Net / Per-Pin Stimulus This new feature allows each IC pin to receive a unique stimulus. This is required for source synchronous buses, and is excellent for locating crosstalk. The stimulus is easy to create and name, and then is applied by name to nets in BoardSim or pins in LineSim. What s New in HyperLynx

Re-Use of Stackups Now, users can save stackups as

This saves the time and possibility of errors associated

The saved stackup can be loaded into any LineSim or

Design and Technology Kits Kits are now availabe for

19 Re-Use of Stackups Now, users can save stackups as re-usable IP. This saves the time and possibility of errors associated with re-entering all the physical parameters. The saved stackup can be loaded into any LineSim or BoardSim design. Design and Technology Kits Kits are now availabe for specific design and simulation of a number of devices and interfaces. These include: DDR DDR2 Fibre Channel PCI-X PCI Express USB Serial ATA SAS What s New in HyperLynx

LineSim to CES Topology Templates With the enhanced integration, LineSim can now be used to graphically define topology templates and enter their

20 Integration with Expedition Enterprise and Board Station XE HyperLynx 8.0 improves integration, and therefore the efficiency of both tools. Each of the enhancements is described in detail in this section. LineSim to CES Topology Templates With the enhanced integration, LineSim can now be used to graphically define topology templates and enter their constraints. Among definable constraints are length/delay, differential pairs, detailed route ordering, as well as advanced formula usage. The illustration shows how easily constraints can be entered. What s New in HyperLynx

CES to LineSim Conversely, enhanced integration lets users

This provides an easy starting point for topology-template

The following screen shot illustrates the ease of net

CES to BoardSim New capabilities also allow CES to transfer

21 CES to LineSim Conversely, enhanced integration lets users extract nets from CES to LineSim. This provides an easy starting point for topology-template definition or refinement. The following screen shot illustrates the ease of net extraction. CES to BoardSim New capabilities also allow CES to transfer constraints to BoardSim for batch simulation and checking. BoardSim can perform batch simulation on both electrical constraints and model assignments, as shown below. What s New in HyperLynx

Additional Operating System Support Finally, increased integration brings support for additional operating system.

22 DxDesigner to LineSim Now, users can extract nets from DxDesigner for use in LineSim. This also includes back annotation. Extraction of nets for use in LineSim is the starting point for topologytemplate definition refinement. The screenshot illustrates how easily extraction is. Additional Operating System Support Finally, increased integration brings support for additional operating system. In addition to the existing OS support (Microsoft Windows 2000, Microsoft Windows XP, Sun Solaris 2.8/9/10), now additional operating systems that are supported included Red Hat Linux and Microsoft Windows Vista. What s New in HyperLynx

23 MF :090123

Electrical optimization and simulation of your PCB design

Electrical optimization and simulation of your PCB design Steve Gascoigne Senior Consultant at Mentor Graphics Zagreb, 10. lipnja 2015. Copyright CADCAM Group 2015 The Challenge of Validating a Design..