When is the use of a Most Effective and Why MPSoC, June 2007 K. Charles Janac, Chairman, President and CEO SoC Communication Complexity Problem Arbitration problem in an SoC with 30 initiators: Hierarchical due to floorplan Pipelined due to performance Arbiter becomes far too complex Then designer makes a like bus blindly (no QoS, power mgmt. etc.) Or builds a intentionally Or acquires a tool kit Or acquires a turnkey IP ITRS Roadmap 2005 Avg. # of Initiators In 2007 = 32. Central Bus Arbiter Arteris Proprietary 2 9-6-1 1
Architecture Application Complexity Wireless handset Initiators ports Telecom infrastructure Initiators ports Multimedia Design Initiators ports Topology Topology Target Models Target ports Target Models Target ports Target Models Target ports Mips / mw / $ Power Efficient QoS important Security User Channel / $ Performance High speed designs Maximum integration Mips or MB/s / $ Complex QOS DRAM Centric Inter-Chip link > 60 sockets s Improve SoC Architecture Performance Arteris Proprietary 3 Network on Chip Project Complexity Number of Design Starts By 2008 60% SoCs 90 or 65nm Source: Gartner 10M units 25M units 90 &65 nm s Help Manage SoC Complexity Arteris Proprietary 4 9-6-2 2
When is a Most Effective and Why? Handling modern SOC complexity lies in the capability to manage multiple constraints above certain thresholds: Number of Initiators, total IPs Latency Area, Frequency, Power QoS Bandwidth, Latency, QOS Power Clocks / Power & Voltage domains Floorplan Reuse & Interoperability IP reuse Reconfigurability Bandwidth Gate area Wire efficiency/ Global wires Arteris Proprietary 5 Customer Design: Telecom Infrastructure initiators "Arteris has the most industrialized on-chip interconnect, which delivers significant value by helping us achieve new classes of performance while reducing our design cycle Daniel Abecassis,, General Manager, ST Wireless Infrastructure Division 500 MHz targets Courtesy STMicroelectronics Arteris Proprietary 6 9-6-3 3
Courtesy IMEC Arteris Proprietary 7 Software Defined Radio baseband platform evolving to cognitive radio Courtesy IMEC Up to 200Mbps SDR 8 nodes 90nm, 24mm2, 3mW standby, 2nJ/bit 11n-40 2x2, 400MHz Complicated segmented busses Up to 3Gbps Cognitive Radio >13 nodes 45nm, 50mm2, 3mW standby with sensing, 2nJ/bit, 1GHz imec/restricted Arteris Proprietary 2006 8 8 9-6-4 4
Examples Architectural Complexity & Variety Separated traffic Classes Low Low cost cost Control Control Clustered design Memory Scheduler Initiator Initiator Initiator Initiator Initiator Local Local Local Local High High throughput throughput Latency Latency critical critical Top level Target Target Target Target Target Target Memory scheduler Memory scheduler Local Local Local Local Low Low cost cost Control Control Peripheral SubSystem 2D mesh design Arteris Proprietary 9 Partitioning timing & power Power/voltage isolation Power domain GALS link Clock domain Isolator AI bus OCP DRAM Modular provides ideal boundaries to power and/or clock domains independently Arteris Proprietary 10 9-6-5 5
Accommodating Design Change - Quickly extract V1 Derivative change New clock Different PLL extract V2 Arteris Proprietary 11 The Effectiveness Space <90nm process >20 IPs >200 Mhz ------------------------- QoS Low Power Multi IP protocol Power Multi QoS data flows Many initiators/many targets IP reuse ------------------------- Fast time to Mkt Lower Unit Costs Lower Project Costs Higher Unit Revenue (telecom) Lower Risk for Complex SoC Projects Latency Reconfigurability Bandwidth Gate area Wire efficiency/ Global wires Arteris Proprietary 12 9-6-6 6