inst.eecs.berkeley.edu/~cs6c CS6C : Machine Structures Lecture 9 CPU Design: The Single-Cycle II & Control 2-7-22!!!Instructor Paul Pearce! Dell may have shipped infected motherboards! Dell is warning customers that its PowerEdge R4 rack-mount server may have shipped with spyware onboard in the embedded system management software (firmware). Good luck getting Norton McAfee to clean that.! http://www.theregister.co.uk/2/7/2/dell_server_warning/ CS6C L9 CPU Design: The Single-Cycle II & Control ()!
How to Design a Processor: step-by-step!. Analyze instruction set architecture (ISA) => datapath requirements! meaning of each instruction is given by the register transfers! datapath must include storage element for ISA registers! datapath must support each register transfer! 2. Select set of datapath components and establish clocking methodology! 3. Assemble datapath meeting requirements! 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.!. Assemble the control logic! CS6C L9 CPU Design: The Single-Cycle II & Control (2)!
Clk Clocking Methodology!............ Storage elements clocked by same edge! Being physical devices, flip-flops (FF) and combinational logic have some delays! Gates: delay from input change to output change! Signals at FF D input must be stable before active clock edge to allow signal to travel within the FF (set-up time), and we have the usual clock-to-q delay! Critical path (longest path through logic)!determines length of clock period! CS6C L9 CPU Design: The Single-Cycle II & Control (3)!
Register-Register Timing: One complete cycle! Clk PC Old Value,,, etc ctr New Value Instruction Access Time Old Value New Value Delay through Control Logic Old Value New Value RegWr Old Value New Value Register File Access Time, B Old Value New Value Delay Old Value New Value RegWr ctr Register Write Occurs Here CS6C L9 CPU Design: The Single-Cycle II & Control (4)!
3c: Logical Operations with Immediate! R[rt] = R[rs] op ZeroExt[imm]! RegWr 26 2 op rs rt immediate 6 bits bits bits bits bits ctr immediate bits But weʼre writing to register??! CS6C L9 CPU Design: The Single-Cycle II & Control ()!
3c: Logical Operations with Immediate! R[rt] = R[rs] op ZeroExt[imm] ]! RegDst RegWr imm 26 CS6C L9 CPU Design: The Single-Cycle II & Control (6)! 2 op rs rt immediate 6 bits bits bits bits ZeroExt bits immediate bits What about register read??! ctr Src Already defined -bit MUX; Zero Ext?!
3d: Load Operations! R[rt] = Mem[R[rs] + SignExt[imm]]!Example: lw rt,rs,imm! 26 2 op rs rt immediate 6 bits bits bits bits RegDst RegWr imm ZeroExt ctr Src CS6C L9 CPU Design: The Single-Cycle II & Control (7)!
3d: Load Operations! R[rt] = Mem[R[rs] + SignExt[imm]]!Example: lw rt,rs,imm! 26 2 op rs rt immediate 6 bits bits bits bits RegDst RegWr imm ExtOp Extender Src ctr MemtoReg MemWr?" In WrEn Adr CS6C L9 CPU Design: The Single-Cycle II & Control (8)!
3e: Store Operations! Mem[ R[rs] + SignExt[imm] ] = R[rt]! Ex.: sw rt, rs, imm! 26 2 op rs rt immediate 6 bits bits bits bits RegDst ctr MemtoReg MemWr RegWr imm ExtOp Extender Src In WrEn Adr CS6C L9 CPU Design: The Single-Cycle II & Control (9)!
3e: Store Operations! Mem[ R[rs] + SignExt[imm] ] = R[rt]! Ex.: sw rt, rs, imm! 26 2 op rs rt immediate 6 bits bits bits bits RegDst ctr MemtoReg MemWr RegWr imm ExtOp Extender Src In WrEn Adr CS6C L9 CPU Design: The Single-Cycle II & Control ()!
3f: The Branch Instruction! beq rs, rt, imm mem[pc] Fetch the instruction from memory! Zero = R[rs] - R[rt] Calculate branch condition! if (Zero) Calculate the next instructionʼs address! PC = PC + 4 + ( SignExt(imm) x 4 )!!else! PC = PC + 4! 26 op 2 rs rt immediate 6 bits bits bits bits CS6C L9 CPU Design: The Single-Cycle II & Control ()!
path for Branch Operations! beq rs, rt, imm!! path generates condition (zero)! 4 PC Ext imm Adder Adder 26 2 op rs rt immediate 6 bits bits bits bits Inst Address" npc_sel Mux PC RegWr Already have mux, adder, need special sign extender for PC, need equal compare (sub?)! CS6C L7 Combinational Logic Blocks and Intro to CPU Design (2)! Zero z" ctr
Putting it All Together:A Single Cycle path! 4 PC Ext imm Adder Adder npc_sel Mux Inst PC Adr RegDst RegWr imm Extender CS6C L7 Combinational Logic Blocks and Intro to CPU Design (3)! <2:2> <:2> <:> ExtOp <:> Imm Zero Instruction<:> Src ctr MemtoReg MemWr z In WrEn Adr
An Abstract View of the Implementation! Instruction Address Next Address Ideal Instruction PC Instruction Register File A B Control Control Signals Conditions Addr In Ideal Out path CS6C L9 CPU Design: The Single-Cycle II & Control (4)!
An Abstract View of the Critical Path! Critical Path (Load Instruction) = Delay clock through PC (FFs) + Instruction s Access Time + Register File s Access Time, + to Perform a -bit Add + Instruction Address Next Address Ideal Instruction PC Access Time + Stable Time for Register File Write Instruction Register File A B (Assumes a fast controller)" Addr In Ideal CS6C L9 CPU Design: The Single-Cycle II & Control ()!
Administrivia! HW 7 due Saturday! Specification update now online. Be sure to check it out. The changes are designed to make integration with project 2 easier. They are very minor.! Project 2 online now!! Reminder: Midterm regrades due Monday.! Paul will be gone on Monday. Noah will be giving the lecture.! Paul will have OH on Monday (barring flight delays)! Be prepared for a kinetic learning activity! CS6C L9 CPU Design: The Single-Cycle II & Control ()!
Review: A Single Cycle path! We have everything but the values of control signals! RegDst RegWr imm npc_sel Extender instr fetch unit zero Instruction<:> <2:2> ctr Z In <:2> MemWr <:> WrEn Adr <:> Imm MemtoReg CS6C L9 CPU Design: The Single-Cycle II & Control (7)! ExtOp Src
Recap: Meaning of the Control Signals! npc_sel:! +4 PC < PC + 4!!! br PC < PC + 4 + n =next!!!!!! {SignExt(Im), }! Later in lecture: higher-level connection between mux and branch condition! 4 PC Ext Adder Adder npc_sel " Mux " PC Inst Address" imm CS6C L9 CPU Design: The Single-Cycle II & Control (8)!
Recap: Meaning of the Control Signals! ExtOp:!zero, sign! src:! reg;! imm! ctr:!add, SUB, OR! RegDst RegWr imm ExtOp Extender MemWr: write memory MemtoReg: alu; mem RegDst: rt; rd RegWr: write register Src ctr MemtoReg MemWr In WrEn Adr CS6C L9 CPU Design: The Single-Cycle II & Control (9)!
RTL: The Add Instruction! 26 2 6 op rs rt rd shamt funct 6 bits bits bits bits bits 6 bits add rd, rs, rt! MEM[PC]!!Fetch the instruction!!!!!from memory! R[rd] = R[rs] + R[rt]!The actual operation! PC = PC + 4!Calculate the next!!!!instructionʼs address! CS6C L9 CPU Design: The Single-Cycle II & Control (2)!
Instruction Fetch Unit at the Beginning of Add Fetch the instruction from Instruction memory: Instruction = MEM[PC]! same for all instructions! Inst Instruction<:> 4 PC Ext Adder Adder npc_sel PC Mux Inst Address" imm CS6C L9 CPU Design: The Single-Cycle II & Control (2)!
The Single Cycle path during Add 26 2 op rs rt rd shamt funct R[rd] = R[rs] + R[rt]! RegDst=rd RegWr= npc_sel=+4 imm ExtOp=x Extender instr fetch unit zero 6 Src=reg Instruction<:> <2:2> Imm ctr=add MemtoReg= MemWr= Z In <:2> <:> WrEn Adr <:> CS6C L9 CPU Design: The Single-Cycle II & Control (22)!
Instruction Fetch Unit at the End of Add! PC = PC + 4! This is the same for all instructions except: Branch and Jump! Inst 4 PC Ext npc_sel=+4 Adder Adder PC Mux Inst Address" imm CS6C L9 CPU Design: The Single-Cycle II & Control (23)!
Single Cycle path during Or Immediate?! 26 2 op rs rt immediate R[rt] = R[rs] OR ZeroExt[Imm]! RegDst= RegWr= npc_sel= imm ExtOp= Extender instr fetch unit zero Src= Instruction<:> <2:2> Imm ctr= MemtoReg= Z In <:2> MemWr= <:> WrEn Adr <:> CS6C L9 CPU Design: The Single-Cycle II & Control (24)!
Single Cycle path during Or Immediate?! 26 2 op rs rt immediate R[rt] = R[rs] OR ZeroExt[Imm]! RegDst=rt RegWr= npc_sel=+4 imm ExtOp=zero Extender instr fetch unit zero Src=imm Instruction<:> <2:2> Imm ctr=or MemtoReg=alu Z In <:2> MemWr= <:> WrEn Adr <:> CS6C L9 CPU Design: The Single-Cycle II & Control (2)!
The Single Cycle path during Load?! 26 2 op rs rt immediate R[rt] = {R[rs] + SignExt[imm]}! RegDst= RegWr= npc_sel= imm ExtOp= Extender instr fetch unit zero Src= Instruction<:> <2:2> Imm ctr= MemtoReg= Z In <:2> MemWr= <:> WrEn Adr <:> CS6C L9 CPU Design: The Single-Cycle II & Control (26)!
The Single Cycle path during Load! 26 2 op rs rt immediate R[rt] = {R[rs] + SignExt[imm]}! RegDst=rt RegWr= npc_sel=+4 imm ExtOp=sign Extender instr fetch unit zero Src=imm Instruction<:> <2:2> Imm ctr=add MemtoReg=mem Z In <:2> MemWr= <:> WrEn Adr <:> CS6C L9 CPU Design: The Single-Cycle II & Control (27)!
The Single Cycle path during Store?! 26 2 op rs rt immediate {R[rs] + SignExt[imm]} = R[rt]! RegDst= RegWr= npc_sel= imm ExtOp= Extender instr fetch unit zero Src= Instruction<:> <2:2> Imm ctr= MemtoReg= Z In <:2> MemWr= <:> WrEn Adr <:> CS6C L9 CPU Design: The Single-Cycle II & Control (28)!
The Single Cycle path during Store! 26 2 op rs rt immediate {R[rs] + SignExt[imm]} = R[rt]! RegDst=x RegWr= npc_sel=+4 imm ExtOp=sign Extender instr fetch unit zero Src=imm Instruction<:> <2:2> Imm ctr=add MemtoReg=x Z In <:2> MemWr= <:> WrEn Adr <:> CS6C L9 CPU Design: The Single-Cycle II & Control (29)!
The Single Cycle path during Branch?! 26 2 op rs rt immediate if (R[rs] - R[rt] == ) then Zero = ; else Zero =! RegDst= RegWr= npc_sel= imm ExtOp= Extender instr fetch unit zero Src= Instruction<:> <2:2> Imm ctr= MemtoReg= Z In <:2> MemWr= <:> WrEn Adr <:> CS6C L9 CPU Design: The Single-Cycle II & Control (3)!
The Single Cycle path during Branch! 26 2 op rs rt immediate if (R[rs] - R[rt] == ) then Zero = ; else Zero =! RegDst=x RegWr= npc_sel=br imm ExtOp=x Extender instr fetch unit zero Src=reg Instruction<:> <2:2> Imm ctr=sub MemtoReg=x Z In <:2> MemWr= <:> WrEn Adr <:> CS6C L9 CPU Design: The Single-Cycle II & Control ()!
Instruction Fetch Unit at the End of Branch! if (Zero == ) then PC = PC + 4 + SignExt[imm]*4 ; else PC = PC + 4! npc_sel Zero imm 4 PC Ext 26 2 op rs rt immediate Adder Adder MUX npc_sel ctrl" " Mux " Inst PC Adr Instruction<:> What is encoding of npc_sel?! Direct MUX select?! Branch inst. / not branch! Letʼs pick 2nd option! npc_sel = +4! npc_sel = br! npc_sel zero? MUX x Q: What logic gate?! CS6C L9 CPU Design: The Single-Cycle II & Control ()!
Peer Instruction! ) In the worst case, the biggest delay is the memory access time! 2) With only changes to control, our datapath could write (something) to memory and registers in one cycle.! 2 a) FF b) FT c) TF d) TT CS6C L9 CPU Design: The Single-Cycle II & Control (33)!
Summary: A Single Cycle path! We have everything! Now we just need to know how to BUILD! CONTROL! RegDst RegWr imm npc_sel Extender instr fetch unit zero Instruction<:> <2:2> ctr Z In <:2> MemWr <:> WrEn Adr <:> Imm MemtoReg CS6C L9 CPU Design: The Single-Cycle II & Control (3)! ExtOp Src
Summary: Single-cycle Processor steps to design a processor. Analyze instruction set datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.. Assemble the control logic Formulate Logic Equations Design Circuits Processor Control Input path Output CS6C L9 CPU Design: The Single-Cycle II & Control (36)!