TEST, QUALIFICATION AND ELECTRONICS INTEGRATION OF THE ALICE SILICON PIXEL DETECTOR MODULES I.A.CALI 1,2, G.ANELLI 2, F.ANTINORI 3, A.BADALA 4, A.BOCCARDI 2, G.E.BRUNO 1, M.BURNS 2, M.CAMPBELL 2, M.CASELLE 1, S.CERESA 2, P.CHOCHULA 2,5, M.CINAUSERO 6, J.CONRAD 2, R.DIMA 3, D.ELIA 1, D.FABRIS 3, R.A.FINI 1, E.FIORETTO 6, F.FORMENTI 2, B.GHIDINI 1, S.KAPUSTA 5, A.KLUGE 2, M.KRIVDA 7, V.LENTI 1, F.LIBRIZZI 4, M.LUNARDON 3, V.MANZARI 1, M.MOREL 2, S.MORETTO 3, F.NAVACH 1, P.NILSSON 2, F.OSMIC 2, G.S.PAPPALARDO 4, V.PATICCHIO 1, A.PEPATO 3, G.PRETE 6, A.PULVIRENTI 4, P.RIEDLER 2, F.RIGGI 4, L.SANDOR 7, R.SANTORO 1, F.SCARLASSARA 3, G.SEGATO 3, F.SORAMEL 8, G.STEFANINI 2, C.TORCATO DE MATOS 2, R.TURRISI 3, L.VANNUCCI 6, G.VIESTI 3, T.VIRGILI 9 1 Dipartimento di Fisica e Sez. INFN di Bari, I-70126, Bari, Italy 2 CERN - European Organization for Nuclear Research, CH-1211 Geneva 23, Switzerland 3 Dipartimento di Fisica e Sezione INFN, I-35131 Padova, Italy 4 Dipartimento di Fisica e Sezione INFN, I-95129 Catania, Italy 5 Comenius University, SK-84215 Bratislava, Slovakia 6 Laboratori Nazionali di Legnaro, I-35020 Legnaro, Italy 7 Slovak Academy of Sciences, SK-04353, Kosice, Slovakia 8 Dipartimento di Fisica dell Universita e Gruppo collegato INFN di Udine, I-33100 Udine, Italy 9 Universita di Salerno e Sezione INFN, I-84081 Baronissi, Italy The ALICE Silicon Pixel Detector (SPD) consists of two cylindrical barrel layers with 10 7 active hybrid pixel cells in total. The requirements in radiation hardness and the challenging material budget and dimensional constraints have led to specific technology developments and novel solutions. An overview of the SPD and its electronics readout system is presented. The procedures for detector module testing, qualification and integration are reported. 1
2 1. Introduction The ALICE Silicon Pixel Detector (SPD) consists of two cylindrical barrel layers with 10 7 active hybrid pixel cells in total. The SPD comprises 1200 front-end ASICs, 150 µm thick, bump bonded in groups of 5 to 200 µm thick silicon sensors to form ladders. Each ladder contains nearly 41K active cells. The basic detector module is the half-stave (HS) which consists of two ladders and one PILOT Multi Chip Module (MCM) interconnected by an aluminium/polyimide multilayer bus. The full SPD contains 120 half-staves (HS) on two half-barrel layers. Comprehensive tests and qualification procedures for the ladders and the HS have been developed. Laboratory and beam tests have been carried out on prototype elements. The following sections give an overview of the on-detector and off-detector electronics. The status of production modules test, qualification and integration is presented. 2. Overview of the ALICE SPD The SPD (see Fig. 1(a)) constitutes the two innermost layers of the ALICE Inner Tracking System (ITS) [ 1 ] at radii of 3.9 cm and 7.6 cm respectively, with a total of nearly 10M active hybrid pixel cells with dimensions of 50 µm (rφ) x 425 µm (z). The SPD half-staves (see Fig.1(b)) are mounted on 10 carbon fibre support (a) (b) Figure 1. jig (b) A CAD drawing of the full SPD (a) and an image of an HS on the mounting sectors. A HS is an assembly of two ladders glued to a multi-layer bus that carries and distributes power and signals. Each HS is equipped with a Multi Chip Module (MCM) connected to a Link Receiver card (LRx) in the Router back-end electronics. The MCM receives and distributes the 10MHz clock and control signals, generates analog reference levels, performs
3 data multiplexing and serialization, and drives the outgoing data stream at 800Mb/s. The LRx cards provide the clock and control signals and perform zero suppression on the data streams. The I/O communication is via fibreoptic links. Each half-sector (6 HS) is read out by a Router, a VME module that is interfaced to the ALICE DAQ system. A specific feature of the the SPD is that it will provide a multiplicity signal (FastOR) contributing to the L0 (lowest latency) trigger. 3. Test of system components Comprehensive test procedures have been developed for the acceptance and qualification of components and half-staves throughout the prototyping, production and assembly sequence. The pixel ASIC [ 2 ] includes 42 internal DACs that allow adjusting all the key operating parameters, such as the global threshold as well as the individual threshold in each pixel cell. The most elementary functional test is based on electrical pulses, internally generated with programmable amplitude and timing. The detector efficiency has been studied by varying the pulse amplitude at various threshold settings (S-curves). Detector efficiency and calibration have also been studied using a 109 Cd radioactive source. Measurements have been taken at various settings of the global threshold DAC. The correspondence between the charge deposited in the detector and the DAC value has been determined. Combining the results of the electrical test pulse and the source measurements, a mean threshold of 1500e with a RMS noise of 200e has been found. The test pulse has also been calibrated and a conversion factor of 66e /mv has been determined. The results obtained are in agreement with those found in previous ladder tests [ 3 ]. Each Multi Chip Module (MCM) contains several ASICs [ 4 ]: the Digital Pilot (DP), the Analog Pilot (AP) and the Gigabit optical link serializer/driver (GOL). It also contains an optical transducer package connected via fibres to the the back-end electronics (LRx cards in the Router). Following electrical/optical conversion in the transducer, the incoming clock and control signals are distributed by the DP to the 10 pixel chips in the corresponding half-stave. The 10 MHz pixel chip clock is generated by the DP using the incoming 40 MHz TTC clock. The raw data of the 10 pixel chips are multiplexed and serialized in the DP, then transmitted to the GOL that drives a laser diode in the optical package at 800Mb/s using a G-link compatible protocol. The jitter recovery performed by the DP has been studied applying clocks with different jitter levels (29 ps incoming clock 9 ps produced clock). The optical link has
4 been studied measuring the signal integrity of both the reconstructed clock and the control data stream. The incoming optical power has been reduced until the DP was no longer able to decode the data correctly. The optical power margin is 12dB approximately. This is adequate to compensate for losses due to connector break points and radiation effects. Long time stability tests have been carried out and eye diagrams examined on the 800 MHz G-Link communication varying the configurations parameters. The GOL configuration has been optimized in order to minimize both jitter (12 ps) and bit error rate (10 17 ). The SPD can provide a trigger input signal to the ALICE central trigger processor using the built-in Fast-OR functionality: in each chip, an electric pulse is fired whenever a hit is detected in a cell. The Fast-OR efficiency has been studied using a 90 Sr radioactive source with a scintillator telescope. The Fast-OR efficiency, defined as the ratio of the number of events recorded to the number of scintillator triggers, has been found to be 99%. The Fast-OR response uniformity across the pixel matrix has been determined by pulsing single pixels and counting the corresponding number of Fast-OR signals generated. The response uniformity is well within the requirements. 4. Half Stave test system The half-stave functionality has been studied using specially developed electronics cards and software tools. The test system is based on a VME module with extensive FPGA programmable functionality that, together with an LRx card and dedicated software, is capable of emulating the data acquisition, trigger and detector control systems. The communication between the HS and the test system is via the same optical link as used in the final DAQ. The system makes use of boundary scan to identify missing connections or short circuits both on the multi-layer bus and on the wire bonding connections of the HS. With a sequence of successive configuration and status accesses all possible defects are identified. In a fully automated way the system scans the pixels matrices using test pulses and modifies both the internal DACs settings of the readout chip and the pulses amplitude. An online analysis tool provides, studying the data acquired, response matrices, S-curves and determines the best DACs settings. Noisy and dead pixels are also automatically identified during source tests. A full test and calibration run requires 30 minutes approximately. The system generates a configuration file that contains all the information required to operate
5 the detector and keep track of its status. Some of these data are the test parameters, the hardware status (integrity of connections, dead or noisy pixels) and the calibration parameters found during the test procedure. The files produced are automatically stored in the construction database. The test procedure is repeated several times during the various steps of the SPD assembly in order to detect any possible malfunction and track the stability of the system. 5. Beam test 2004 and ALICE Trigger, DAQ and DCS integration A combined beam test of prototypes of the ALICE Inner Tracking System (ITS) was performed in November 2004 in the H4 line at CERN SPS with 158 GeV/c protons. The setup included two detector modules in each of the three silicon ITS technologies: pixels, drift (SDD) and strips (SSD). This was the first test of the detectors integrated with the ALICE DAQ and trigger systems. The full SPD electronic chain was operated successfully. Fig.2(a) shows an example of the correlation plots - SPD and SDD in this case - that were obtained. The full data analysis is in progress. 6. SPD calibration in the ALICE DCS framework The SPD calibration system is being developed within the ALICE Detector Control System framework. A block diagram is shown in fig.2(b). The communication between the different component is based on TCP/IP using a DIM protocol. Software tools in C++, PVSS and ROOT allow to simulate the ALICE DAQ and trigger system during the calibration phases. The data are retrieved via VME. A dedicated tool will analyze the detector response and identify the configuration required for the operating conditions. The prototype of this system is nearing completion and will be used in December 2005 to test the first SPD sector during final integration and commissioning. The control and readout electronics will be the final one based on the Router and the LinkRx cards. 7. Summary The SPD components prototypes have been fully validated in laboratory as well as beam tests. The production is under way; the first sector has been fully assembled. Test procedures have been developed and implemented in all the production steps. The ALICE on-detector and off-detector electronics performs to specifications. A prototype of the final system for detector
6 (a) (b) Figure 2. Correlation plot between the second plane of the the SPD and the first plane of the SDD (a); A block diagram of the ALICE SPD detector control system (b) calibration and control system is being developed and will be operated in the integration test of the first sector. Bibliography 1. ITS Technical Design Report, CERN-LHCC 99-12 (1999). 2. K. Wyllie et al., Front-end pixel chips for tracking in ALICE and particle identification in LHCb, Proceeding of the Pixel 2002 Conference, SLAC Electronic Conference Proceedings, Carmel, USA, September 2002. 3. P. Riedler et al., Recent test results of the ALICE silicon pixel detector, Nuclear Instruments and Methods in Physics Research A, (2005), 549, p. 65-69. 4. A. Kluge et al., The ALICE Silicon Pixel Detector Front-end and Read-out Electronics, Proceedings of the Vertex 2004 Conference, to be published in Computer Physics Communications.