NSF Workshop 2/02/2012 3D Integration & Packaging Challenges with through-silicon-vias (TSV) Dr John U. Knickerbocker IBM - T.J. Watson Research, New York, USA Substrate IBM Research
Acknowledgements IBM Research & S&TG - P. Andry -E. Colgan -B. Dang - T. Dickson - M. Farooq - C. Jahnes -J. Maria - R. Polastre - C. Tsang -C. Tyberg -B. Webb - S. Wright 2 IBM Research
System Trends & 3D Technology Integration Benefits Consumer / Network Appliances / Sensors Applications Low Cost Pocket Size / Small Form Factor Increasing Function @ Same or Smaller Size Lower Power Local transactions Wireless High Bandwidth / High Data Rate Security High Volume / Time to Market 3D Technology Power Efficiency Scalability / Modularity Heterogeneous Integration Increasing BW / Function Lower Cost Computers / Servers / Cloud / HPC Applications Power Efficiency Performance -Multi-core - Multi-thread - High Bandwidth - Heterogeneous Integration Cost Security Reliability 3 IBM Research
Packaging Integration Density Integration Density (I/O per square cm) 3D IC Integration I/O: 6 μm pitch 2,500,000 I/O / sq. cm Wiring pitch: 90 nm Si on Si Package I/O: 50 μm pitch & Chip Stacking w / TSV 40,000 I/O / sq. cm Wiring pitch: 2 μm Organic & Ceramic Pkg (SCM & MCM) I/O: 200 μm pitch 2,500 I/O / sq. cm Wiring pitch: 50 to 200 μm I/O: 150 um pitch 4,400 I/O / sq. cm Wiring pitch: 40 to 150 μm Time 4 IBM Research
Advantages: Short vertical interconnects Miniaturization Higher Bandwidth / lower latency New Function in small form factor Lower power / energy savings Improved performance / streaming Lower Cost 3D Integration Challenges: Architecture / Design to leverage 3D technology Power Delivery / Thermal Mgt Application Dependent Industry Compatibility & Standards MFG Equipment, Process, Assembly & Fine pitch Wafer Test 5 IBM Research
3D-Technology Challenges & Readiness 3D Challenges 3D Readiness 1. 3D Architecture. Circuits, Timing, EDA Tools, Modeling Data Library / Fabrication Rules 2. 3D Technology & Integration Elements Material, Structure, Processes - Thinned Si - Through Silicon - Via (TSV) - Silicon - Silicon Interconnection (SSI) - Low power link - Module Integration - Assembly - Test (WLT for KGD) - Power delivery - Cooling Chip Stack Substrate 3. Introduction of New Function or New Competitive Product Value Add - Industry Infrastructure, 3D Standards - Miniaturization - 3D Products Volume Lower Costs - Function Design / Architecture for lower costs (Perf., Power, Het. Integ.) Power Efficiency, Performance - Standards New Applications / Size / Function 6 IBM Research
VLSI Design for Stacked Die with TSV s Design considerations for 3D stacked die with TSV s - Design tools, know-how, micro-architecture - EDA tools - Physical floor planning & partitioning - Electrical design and models - Checking and verification - Power & thermal models - Chip Infrastructure - Power & ground delivery and distribution - Clock distribution - IP Blocks - Custom and random logic - SRAM, edram and other memory -FPGA - Analog, special functions - In die-stack link - Off die-stack I/O Substrate Substrate Processor Memory Processor Memory Memory 7 IBM Research
3D Silicon Integration 3D Silicon Pkg Integration SSI Silicon Package Cooling Cu Wiring Circuits, Trench Capacitors TSV Substrate 3D Die Stack & Si Pkg Integration TSV SSI Die Stack Si Package Base Substrate 8 IBM Research
Architecture - Design - Build - Characterization Few Examples of 3D Test Vehicles - TV s silicon through via development - TV s high density wiring, signal integrity & cross talk (Si Carrier & Die Stack (TSV, Link & uc-4) - TV s high I/O interconnection & chip stacking - TV s active circuit die stacks (Funct., EDA, etc) - TV s optical, thermal, module assessments - TV s for reliability TSV Cooling Chip Chip Si Si Silicon Thru-via CMOS IC OE Substrate Decoupling Capacitors Cooler Chip 1 Chip 2 18-bump chain. Organic Chip Package waveguide *ECTC 2008 Doany et al. 9 IBM Research
High Bandwidth Wiring & Link characterization Wiring - Signal & Ground Test Vehicle TSV Characterization (Example) Micro-joint solder ( 25 um dia & 50 um pitch) - Inductance - DC resistance - DC resistance - DTC -EM BEOL Characterization Decoupling Capacitors - Signal integrity vs Distance & Data rate - 10-14 uf/cm2 demonstrated / with TSV - Far end X-talk: Design dependent Chip To Chip & Chip Stack Link Characterization Modeling and Data Library - Signal integrity, Data rate, X-Talk,. - Frequency & Time Domain 10 IBM Research
High Bandwidth, Link Characterization & Energy Efficiency Dickson et al. VLSI 11 IBM Research
Thin die & Multi-high uc-4 Die Stack Assembly TSV = Cu or W TSV pitch = 50 um uc-4 = Solder uc-4 pitch = 50 um Top Chip Si Die Ceramic or Organic Substrate Si Si Si Si carrier 12 IBM Research
Farooq et al. IEDM 2011 / IEEE copyright 13 IBM Research
3D-Technology Research & Manufacturing Summary 3D Integration Research 3D Chip 3D Stack & Si Pkg Si Pkg Dev / Mfg / Products -- Architecture - Design / Structure / Size -- Application Sizing - Wafers 200 mm / 300mm - - Cost Sizing - Design Kits - - Technology Qualifications - Technology Platforms - - Product Qualifications - Architecture / Design - Assembly (C2C, C2W, W2W) - Design Tools / Circuits - IP Library & Models & Low power links - TSV Dia, Pitch / Si Thickness - Electrical, Mechanical, Thermal - CMOS Wafer Integration & Finishing - Test & Reliability - Stack Interconnection size, pitch: - Modeling Performance, Power, Cost Time 14 IBM Research
Summary Opportunity to Improve our Quality of Life Sensors Data Management Energy efficiency / Green Personal Handheld Servers & High Performance Computers IBM 3D Technology Advancements / Mfg 3D Technology Elements TSV Higher density Die Stack Integration platforms Silicon Package Integration platforms Low power electrical interconnects 3D Stack & 2.5D Pkg System / Hardware Demonstrations Application Dependent on 3D Architecture & Design Efficient Integration & Optimization over time Cost Benefits, Power Efficiency, Performance, Size, 3D Silicon Integration Demonstrations Si Pkg 15 IBM Research