The CPU Bus : Structure 0 - PDF Free Download

The CPU Bus : Structure 0 The following can be applied to both the internal CPU buses and the external system buses. This distinction becomes blurred when we discuss Systems on a single Chip (SoC).

The CPU Bus : Structure 0 The following can be applied to both the internal CPU buses and the external system buses. This distinction becomes blurred when we discuss Systems on a single Chip (SoC). Device 1 Enq Device 2 Ack Buses require a protocol in order to function correctly. Most bus protocols use a four-cycle protocol

The CPU Bus : Behaviour 1

The CPU Bus : Behaviour 1 Device 1 Action Device 2 1 2 3 4 time from Computers as Components W. Wolf

The CPU Bus : Signals 2 Most bus operations are reading and writing. A typical bus will require the following to support this :

The CPU Bus : Signals 2 Most bus operations are reading and writing. A typical bus will require the following to support this : Clock synchronizes the bus components.

The CPU Bus : Signals 2 Most bus operations are reading and writing. A typical bus will require the following to support this : Clock synchronizes the bus components. R/W controls whether a read or write should take place. Address an m-bit set of signals used to identify the location for an access. Data an n-bit set of signals used to carry the data to or from the CPU. Under most circumstances the bus will be controlled by the CPU. The main exceptions are

The CPU Bus : Notation 3 high rising falling A low 10 ns B changing stable C timing constraint time from Computers as Components W. Wolf Timing diagram notation

The CPU Bus : Read - Write cycles 4 Clock R/W Address enable Address Data ready Data time from Computers as Components W. Wolf A typical timing diagram for read and write cycles

The CPU Bus : VHDL descriptions 0 Buses will be described as either

The CPU Bus : VHDL descriptions 0 Buses will be described as either or an interface ( port description ).

The CPU Bus : VHDL descriptions 0 Buses will be described as either an interface ( port description ). or a set of signals.

The CPU Bus : VHDL descriptions 0 Buses will be described as either an interface ( port description ). or a set of signals. The control signals or ports will normally be unidirectional.

The CPU Bus : VHDL descriptions 0 Buses will be described as either an interface ( port description ). or a set of signals. The control signals or ports will normally be unidirectional. The bus(es) will be bi-directional and will need to be described with a resolution function to resolve the bus access. When a signal can be driven by more than one source, there must be a way of resolving what happens if multiple drivers are active at the same time.

The CPU Bus : Magic Smoke entity magic is port (a, b, c : in std_logic; bus: out std_logic); end magic;

The CPU Bus : Magic Smoke entity magic is port (a, b, c : in std_logic; bus: out std_logic); end magic; architecture smoke of magic is signal sig : std_logic; begin sig <= a; sig <= b; sig <= c; z <= sig; end architecture;

The CPU Bus : VHDL descriptions 0a U X 0 1 Z W L H U U U 0 U U U 0 U U X U X 0 X X X 0 X X 0 0 0 0 0 0 0 0 0 0 1 U X 0 1 X X 0 1 X Z U X 0 X X X 0 X X W U X 0 X X X 0 X X L 0 0 0 0 0 0 0 0 0 H U X 0 1 X X 0 1 X U X 0 X X X 0 X X U Uninitialised X Forcing unknown 0 Forcing 0 1 Forcing 1 Z High impedance W Weak unknown L Weak 0 H Weak 1 Don t care std_u_logic The resolution table for the AND function when the inputs are defined as std_u_logic. Note that the high impedance value, Z, is not treated as a special case.

The CPU Bus : VHDL descriptions 0b U X 0 1 Z W L H U U U U U U U U U U X U X X X X X X X X 0 U X 0 X 0 0 0 0 X 1 U X X 1 1 1 1 1 X Z U X 0 1 Z W L H X W U X 0 1 W W W W X L U X 0 1 L W L W X H U X 0 1 H W W H X U X X X X X X X X Possible values for 3.3 v LVTTL X 1.5v 0 < 0.4v 1 > 2.4v W > 0.8v & < 1.5v < 2.0v & > 1.5v L < 0.8v & > 0.4v H > 2.0v & < 2.4v std_logic The resolution function for std_logic. This shows what the result will be if 2 values are driving the same signal. For example driving a signal with a strong 1 and a strong 0 results in a strong unknown X. Strictly speaking the terms weak and strong signals relate to whether the 0 or the 1 outputs are driven by the gate transistors or are passive. See ASIC design, M.J. Smith, (ref. to be completed)

The CPU Bus : VHDL descriptions 1 -- property of Altera Corporation LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY bidir IS PORT( bidir : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); oe, clk : IN STD_LOGIC; inp : IN STD_LOGIC_VECTOR (7 DOWNTO 0); outp : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END bidir; ARCHITECTURE maxpld OF bidir IS SIGNAL a : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores -- value from input. SIGNAL b : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores -- feedback value.

The Bus Interface : VHDL descriptions 2 BEGIN PROCESS(clk) BEGIN IF clk = 1 AND clk EVENT THEN -- Creates the flipflops a <= inp; outp <= b; END IF; END PROCESS; PROCESS (oe, bidir) -- Behavioral representation BEGIN -- of tri-states. IF( oe = 0 ) THEN bidir <= "ZZZZZZZZ"; b <= bidir; ELSE bidir <= a; b <= bidir; END IF; END PROCESS; END maxpld;

Bus Interface : Quartus RTL View

Register to Bus : An alternative 4 library ieee; use ieee.std_logic_1164.all; entity ld_reg is generic ( n : natural := 16); port ( clk : in std_logic; reset : in std_logic; load : in std_logic; bus_enable : in std_logic; q : inout std_logic_vector(n-1 downto 0)); end ld_reg;

Register to Bus : 2 5 architecture rtl of ld_inc_reg is signal q_val : std_logic_vector(n-1 downto 0); begin -- rtl p0 : process (clk) begin -- process if (rising_edge(clk)) then -- rising clock edge if reset = 0 then -- synchronous reset. q_val <= (others =>( 0 )); else if load = 1 then q_val <= q; end if; end if; end if; end process p0;

Register to Bus : Last Bit -- purpose: tristated output from register -- type : combinational -- inputs : bus_enable, q_val -- outputs: q, 16 bit output drive_bus : process( bus_enable, load, q_val ) begin if (bus_enable = 1 and load = 0 ) then q <= std_logic_vector(q_val); else q <= (others=>( Z )); end if; end process drive_bus; end rtl;

CPU Buses : RTL view 7

CPU Buses : RTL view 7 Do you understand this?

clk reset2 reset1 address_bus 15 address_bus 14 address_bus 13 address_bus 12 address_bus 11 address_bus 10 address_bus 9 address_bus 8 address_bus 7 address_bus 6 address_bus 5 address_bus 4 address_bus 3 address_bus 2 address_bus 1 address_bus 0 data_bus 7 data_bus 6 data_bus 5 data_bus 4 data_bus 3 data_bus 2 data_bus 1 data_bus 0 read_m write_m CPU Buses : hardware (vst) view 7 data reg. program counter d_h en. Structure of the r-s cpu address register showing internal buses d_bus control Address bus and the external connection to the address and data buses Data bus d_l en. t_reg r_reg acc. acc d_en IR Control Unit flag ALU

CPU Buses : hardware (vst) view 8 clk reset1 reset2 cpu a_bus 15 Cpu integrated into an SoC, along with a_bus 14 a_bus 13 a_bus 12 a_bus 11 the a_bus ram 10 & rom, as indicated by the a_bus 9 shaded area. The external address and data buses are now both internal. cpu a_bus 8 a_bus 7 a_bus 6 a_bus 5 a_bus 4 a_bus 3 a_bus 2 a_bus 1 a_bus 0 d_bus 7 data_seg cpu_ram rom_select code_seg board_rom d_bus 6 d_bus 5 d_bus 4 d_bus 3 d_bus 2 d_bus 1 d_bus 0

CPU Buses : hardware timing 9 source register D Q circuit propagation delay bus gate R out n bit bus logic block R in dest. reg. gate prop. bus prop. ALU etc. latch t g t bp t comb t l The set of factors to be considered when calculating D Q clock speed. This example uses latches rather than edge triggered devices. R out latch hold time, t h latch setup time,t su R in t R2valid minimum pulse width,t w Minimum clock period, t min after V. Heuring & H. Jordan Computer Systems Design & Arch. 2nd Ed.