!"#$%&&"'(')"*+"%,%-".#"'/"'.001$$"!!"#$%&'#()#*+"+#,-."/0110#230#4."50",+"+#)6# 6+-+#(.6+-0#)4475.8)60#0/#.65-0#230#9+**+"+# 2.48).-0#(.6+-0#! 2+"*5."5*:#,."/0110#;)**0! *),".6*:#-.99-0*0"5."+#2+660,.40"5)#;)*)2)#<*+"+#,-."/0110#2+"2+--0"5)=! (.-).860*:#-.99-0*0"5."+#(.-).8)6)#.66>)"50-"+#/)#7"# 9-+20**+#<*+"+#,-."/0110#*0?70"1).6)=!!"+65-0#*)#9+**+"+#/0;)")-0#/0)#97"5.5+-)#.#;)60*# <+(().40"50#90-#86+223)#97-.40"50# 2+49+-5.40"5.6)=! @,")#,-."/011.#)49)0,.5.#/0(0#0**0-0#/0;)")5.#.#9-)+-) variable x: integer; signal abc: bit; constant Vdd: real := 12.3;
!"#$%&&"'(')%#*+!!"#$%&'#(")*&+,-.#%),#/-,)0.11,#,#-"2,).-.#,++'")3.-)�"#%)#*.-3&#*,2$�"#(,-",4+"3,'# 56-,)/.78! 9+#-,)/.#(,#:$.*";"*,3&#")#;,:.#0"# 0"*<",-,1"&).## entity COMPARE_digit is port (a, b : in integer range 1 to 10; c : out boolean); end COMPARE_digit; variable ABC: real range 1.0 to 10.0;
!"#$%&&"'(')*&$%#$&!!"#$%&'()*+),)-.*/$'(-)*"(*0"$1*0'2&"*-.%* %"#&'&)*#"*3'*2"3.2",.(&)*'%%'*#&.##'*42'(-.55'* +)#&'(&.! 6.*+)#&'(&"*0)##)()*.##.2.*-"+7"'2'&.* '%%1"(&.2()*-"*$(*0'8'4.9*.(&"&:*)*'2+7"&.+&$2. constant Vdd: Real := 4.5; constant CYCLE : Time := 100 ns; constant PI : Real := 3.14; constant FIVE : std_logic_vector (0 to 3) := "0101";
!"#$%&&"'('!")#%*&!!"#"$%&'()*'+,"#-$.-,$/0"%%-1'2-#),$3,(,0,4! 5'##"$0"26#,0'*-$)*'$%"*"$7'*,-$-#),)8! 9#$(-1#'%-$:6"&$-((-*-$,#,+,'%,++')"$ ;<==>?@AB?>$,#$3'(-$.,$!A?=>!A$ %&,#,+,'%,++'+,"#-$:")*-CC-$-((-*-$.,('))-('DE! A#$6#&$-#),)8$6#$(-1#'%-$7,-#-$.,0F,'*')"$ )*'2,)-$%'$port signal count: integer range 1 to 10; signal GROUND: bit :=0 ; signal SYS_BUS : std_logic_vector (7 downto 0); port (A, B : in std_logic);
!"#$%&&"'(')%*"%+,-&!!"#$%#&'#(')*$%'*"*$'+,'*-#.#$"*'$process! )/#00*-"#+*".1$2*)$%#)1&*$#2$3"#$%#&'#(')*$ #%%'*"*$'0.#".#"*#+*".*$'"$0'+3)#4'1"*$ 5#))/1,,10.1$2'$3"$0*-"#)*$,*&$63'$ )#00*-"#+*".1$#%%'*"*$'"$(#0*$#)$$7.*+,1$2'$ 0'+3)#4'1"*89! 2*%*$*00*&*$2'6:'#&#.#$,&'+#$2'$*00*&*$30#.# variable INDEX : integer range 1 to 50; variable CYCLE : time range 10 ns to 50 ns := 10ns; varaible MEMORY : bit_vector (0 to 7); variable x,y,z : integer;
!"#$%&&"'(')*+,)&&"-#&!!"#"$%"&'()*$+',+*-./*$,*&$0.)0").&*$(#$ &+1()/./"! 23",*&.#4"$4+,*#4*$4.))*$-&.#4*55*$(1./*$ 0"'*$",*&./"&+! 6)0(#+$",*&.#4+$&+1+*4"#"$+#$.,,"1+/+$,.7.-*1! 8*#*&.)'*#/*$-)+$",*&.#4+$4*9"#"$*11*&*$ 4*))"$1/*11"$/+,"! 6)/&+'*#/+$1+$4*9*$*1,)+0+/.&*$).$0"#9*&1+"#* " :;;<;: =$>$=?@ " A<;;:BB<=$>$CDB:8:;$E=?@F
!"#$%&&"'(')*+,%#-"!!"#$%$& and, or, nand, nor, xor! '()*+$",*)$ =, /=, <, <=, >, >=! -",%*.(,*+$",(/(/*0$.,(.$%$ &, +, -, *, /, mod, rem, **, abs!!"#$%$& not! 1234&/$)/50(%(6(,.(/()(,%"/(7/"06$,*."/$,/ 8*9(/*))*/50$".$.*7/
Logical (lowest precedence) Operators AND, OR, NAND, NOR, XOR, XNOR Relational Shift =, /=, <, <=, >, >= SLL, SRL, SLA, SRA, ROL, ROR Adding (including concatenation) +, -, & Multiplying *, /, MOD (modulus), REM (remainder) Misc (highest precedence) ABS (absolute), ** (exponentiation), NOT Jim Duckworth, WPI 17 VHDL Basics - Module 2
Logical Operators (cont d) may be used with predefined (single element and one-dimensional array) bit, std_logic, and Boolean types d <= a AND c; -- assume a, b, c, d, e, are type std_logic Relational d <= b NOR c; d <= a NAND b NAND c; -- illegal NAND/NOR sequence -- not associative d <= (a NAND b) NAND c; -- use parentheses NOTE: not three-input NAND gate d <= a OR (b AND c); e <= (b AND d) XOR (a NAND c); used for comparison operations. two operands must be same type - result is a Boolean value c <= a = b; -- assume a and b are type integer Jim Duckworth, WPI 18 VHDL Basics - Module 2
Operators (cont d) Adding Operators +,- for integer operands (NOT for bits or bit_vectors) also supported for SIGNED and UNSIGNED data types in signed and unsigned packages & (concatenation) for single elements or one-dimensional array LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; -- for arithmetic operations ENTITY test4 IS PORT(i, j : IN integer RANGE 0 TO 99; a, b : IN std_logic_vector(7 DOWNTO 0); k : OUT integer RANGE 0 TO 99; c, d : OUT std_logic_vector (7 DOWNTO 0)); END test4; Jim Duckworth, WPI 19 VHDL Basics - Module 2
Operators (cont d) ARCHITECTURE arch OF test4 IS k <= i + j; -- ok for integers c <= a + b; -- ok for std_logic if unsigned included d <= a(5 DOWNTO 0) & b(7 DOWNTO 6); END arch; Jim Duckworth, WPI 20 VHDL Basics - Module 2
Synthesis Results Jim Duckworth, WPI 21 VHDL Basics - Module 2
Synthesis Results Jim Duckworth, WPI 22 VHDL Basics - Module 2
Concurrent Signal Assignments Module 3 Jim Duckworth, WPI 1 Concurrent Signal Assignments - Module 3
Concurrent Signal Assignment Signals that appear outside of a process Event-triggered, when an event (change in value) occurs on one of the signals in the expression Three types concurrent signal assignment conditional signal assignment selected signal assignment Jim Duckworth, WPI 2 Concurrent Signal Assignments - Module 3
Concurrent Signal Assignment (cont d) ARCHITECTURE example OF full_adder sum <= a XOR b XOR c; temp <= a AND b; cout <= temp AND c; END example; Any time an event occurs on signals a, b, or c the concurrent signal assignments are re-executed. Signals in expression act like sensitivity list for process Equivalent process statement: PROCESS (a, b, c) sum <= a XOR b XOR c; END PROCESS; Jim Duckworth, WPI 3 Concurrent Signal Assignments - Module 3
Conditional Signal Assignment Selects different values for the target signal priority associated with series of WHEN.. ELSE Similar to an IF statement example multiplexer: i0 i1 i2 i3 q ARCHITECTURE example OF mux IS q <= i0 WHEN a = 0 AND b = 0 ELSE i1 WHEN a = 1 AND b = 0 ELSE i2 WHEN a = 0 AND b = 1 ELSE i3 WHEN a = 1 AND b = 1 ELSE X ; -- driven unknown END example; a b Jim Duckworth, WPI 4 Concurrent Signal Assignments - Module 3
Complete VHDL Jim Duckworth, WPI 5 Concurrent Signal Assignments - Module 3
Synthesis Results RTL Schematic Jim Duckworth, WPI 7 Concurrent Signal Assignments - Module 3
Synthesis Results Technology Schematic Jim Duckworth, WPI 8 Concurrent Signal Assignments - Module 3
Selected Signal Assignment Selects different values for a target signal no priority associated with input conditions Similar to a CASE statement ARCHITECTURE example OF mux IS WITH sel SELECT q <= i0 WHEN 00, i1 WHEN 01, i2 WHEN 10, i3 WHEN 11, X WHEN OTHERS; END example; Jim Duckworth, WPI 10 Concurrent Signal Assignments - Module 3
Selected Signal Assignment (cont d) Another example using enumerated type ARCHITECTURE example OF alu IS TYPE op_code IS (and_op, or_op, add_op, sub_op); SIGNAL inst : op_code; inst <= -- inst gets some value; WITH inst SELECT result <= a AND b WHEN and_op, a OR b WHEN or_op, a + b WHEN add_op, a - b WHEN sub_op; END example; Jim Duckworth, WPI 11 Concurrent Signal Assignments - Module 3
Selected Signal Assignment (cont d) Another example ARCHITECTURE example OF sel IS WITH x SELECT z <= a WHEN 1 2, b WHEN 3 TO 6, c WHEN OTHERS; END example; Jim Duckworth, WPI 12 Concurrent Signal Assignments - Module 3
Aggregates A set of comma separated elements enclosed in parenthesis Denotes the value of a composite type (array or record) Value specified by listing the value of each element bus_a <= 10110111 ; bus_b <= (OTHERS => 0 ); bus_c <= (2 => 0, 6 => 0, OTHERS => 1 ); Jim Duckworth, WPI 14 Concurrent Signal Assignments - Module 3
Drivers I drivers vengono creati attraverso assegnazione di segnale. Driver Multipli: molto utili per gestire data-bus, bus bi-direzionali, vengono risolti in un unico valore dalle cosiddette resolution functions Errori nella gestione dei drivers ENTITY mio_mux IS PORT( i0,i1,i2,i3,a,b:in std_logic; q : OUT std_logic); END mio_mux; ARCHITECTURE sbagliata OF mio_mux IS q <= i0 when a='0' AND b='0' else '0'; q <= i1 when a='1' AND b='0' else '0'; q <= i2 when a='0' AND b='1' else '0'; q <= i3 when a='1' AND b='1' else '0'; END sbagliata; Sono stati creati 4 drivers, ma ci sono ambiguità:una eventuale resolution function, come potrebbe gestire questa situazione? ARCHITECTURE giusta OF mio_mux IS q <= i0 when a='0' AND b='0'else i1 when a='1' AND b='0' else i2 when a='0' AND b='1' else i3 when a='1' AND b='1' else 'X'; END giusta; In questo modo abbiamo un unico driver!
The Process Statement Module 4 Jim Duckworth, WPI 1 The Process Statement - Module 4
Process Sequential Statements IF statements CASE statements LOOP statement Variable Assignment Signal Assignment Overview Jim Duckworth, WPI 2 The Process Statement - Module 4
Architecture - Review An Architecture describes the functionality of an Entity Consists of concurrent statements, e.g. Process Statement Concurrent Signal Assignments Conditional Signal Assignments Concurrent statements - order does not matter -- example of concurrent signal assignments ARCHITECTURE arch OF full_adder IS sum <= a XOR b XOR c; temp <= a AND b; cout <= temp AND c; END arch; Jim Duckworth, WPI 3 The Process Statement - Module 4
Process Statement A process is the fundamental building block of architecture bodies. A Process statement is an example of a concurrent statement. It is composed of a set of sequential statements - executes in sequence [process_label:] PROCESS [(sensitivity_list)] [process declarations] sequential statements END PROCESS [process_label]; Sensitivity List shows which signals the process is sensitive to any change on these signals causes process to be executed suspends after executing last sequential statement - waits for another event to occur on signal in sensitivity list Jim Duckworth, WPI 4 The Process Statement - Module 4
IF statement Example of a sequential statement - only used in process or subprogram Selects a sequence of statements for execution based on the value of a condition Each condition is checked sequentially until the first condition is true - priority is implied IF opcode = add_op THEN result := abus + b_bus; ELSIF opcode = inc_op THEN IF flag = false THEN result := 0; ELSE result := result + 1; END IF; END IF; -- nested IF statement Jim Duckworth, WPI 5 The Process Statement - Module 4
CASE statement Selects one of a number of branches based on the value of an expression Expression must be integer, enumerated type or one-dimensional character array (like bit_vector or std_logic_vector) All possible values must be covered exactly once CASE state IS -- state is an enumerated type in this example WHEN s0 => -- branch 1 counter := 0; state <= s2; WHEN s1 => -- branch 2 state <= s4; WHEN s2 s3 => -- can use set of choices (not logical OR) counter := counter + 1; state <= s0; WHEN OTHERS => -- can use OTHERS to cover remaining values state <= s3; END CASE; Jim Duckworth, WPI 6 The Process Statement - Module 4
LOOP STATEMENTS Used to iterate through a set of sequential statements Three types FOR identifier IN range LOOP END LOOP; WHILE boolean_expression LOOP END LOOP; LOOP EXIT WHEN condition_test END LOOP; Jim Duckworth, WPI 7 The Process Statement - Module 4
Process example - BCD_COUNT LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; -- required for addition ENTITY bcd_count IS -- bcd counter PORT (clk, reset: IN std_logic; q : OUT std_logic_vector (3 DOWNTO 0)); END bcd_count; Jim Duckworth, WPI 8 The Process Statement - Module 4
BCD_COUNT (cont d) ARCHITECTURE behav OF bcd_count IS SIGNAL temp : std_logic_vector (3 DOWNTO 0); -- two concurrent statements (Process and signal assignment) PROCESS (clk, reset) -- sensitivity list for process IF reset = 1 THEN temp <= 0000 ; ELSIF clk EVENT AND clk = 1 THEN IF temp = 1001 THEN -- check if 9 temp <= 0000 ; -- back to 0 ELSE temp <= temp + 1; -- increment by one END IF; END IF; END PROCESS; q <= temp; END behav; Jim Duckworth, WPI 9 The Process Statement - Module 4
Variable Assignment Assigns a new value (immediately) to a variable a := b + 45; -- a and b are integers Variables only used in process or subprograms Declared inside process Not accessible outside of process Need to assign to signal for access outside process Used for temporary storage Jim Duckworth, WPI 12 The Process Statement - Module 4
Example ENTITY example2 IS -- PORT(a_bus : IN integer RANGE 0 TO 127; flag : OUT std_logic); END example2; ARCHITECTURE arch OF example2 IS PROCESS(a_bus) VARIABLE j : integer RANGE 0 to 127; --only visible in process j := a_bus / 2; j := j + 4; -- update immediately IF j > 50 THEN flag <= '1'; ELSE flag <= '0'; END IF; END PROCESS; END arch; Jim Duckworth, WPI 13 The Process Statement - Module 4
Signal Assignments inside a Process Changes the value of a signal (wire or net) (If outside a process then it is a concurrent statement) If inside a process then executed sequentially with other statements. A signal assignment will supersede a previous assignment to the same signal A signal update occurs after a delta delay (very small delay) - allows for ordering of events. Very important difference: variables updated immediately signals get new values at a later time (usually end of process or when simulation time advances) Jim Duckworth, WPI 14 The Process Statement - Module 4
Example ARCHITECTURE behav OF incorrect_example IS SIGNAL a : integer; -- declare internal signal PROCESS(f) VARIABLE j, k : integer; j := f + k; -- j updated immediately a <= j + 1; -- a updated at end of process k := a; -- k gets old value of a END PROCESS END behav; Jim Duckworth, WPI 15 The Process Statement - Module 4
Concurrent Signals - Reminder ENTITY test3 IS PORT (a, clk d END test3; : IN std_logic; : OUT std_logic); ARCHITECTURE arch OF test3 IS SIGNAL b, c : std_logic; b <= a; -- order does not matter d <= c; c <= b; END arch; Jim Duckworth, WPI 16 The Process Statement - Module 4
RTL Schematic Jim Duckworth, WPI 18 The Process Statement - Module 4
Signals in Clocked Process (flip-flops) ENTITY test3a IS PORT (a, clk : IN std_logic; d : OUT std_logic); END test3a; ARCHITECTURE arch OF test3a IS SIGNAL b, c : std_logic; PROCESS (clk) IF clk'event AND clk = '1' THEN b <= a; c <= b; d <= c; END IF; END PROCESS; -- b, c, d updated with previous values of a, b, c END arch; Jim Duckworth, WPI 19 The Process Statement - Module 4
RTL Schematic Jim Duckworth, WPI 21 The Process Statement - Module 4
Process Overview A process may be used to describe combinational or sequential (clocked) logic. Combinational Logic in combinational logic the outputs are only dependent on the inputs no latches or flip-flops should be generated Sequential Logic contains memory elements (storage) - outputs dependent on both current inputs and past events see next module for examples Jim Duckworth, WPI 22 The Process Statement - Module 4
Process Style for Combinational Logic General Rules sensitivity list is required and MUST include all signals used in process Synthesis tools will only provide warning, simulation will fail variables must NOT be used before being set last successive assignment to a signal is last one implemented all outputs should have default values if not, a latch will be generated to hold the current value No WAIT statements allowed in process Jim Duckworth, WPI 23 The Process Statement - Module 4
Incorrect Combinational Process Jim Duckworth, WPI 24 The Process Statement - Module 4
Latch and constant value generated Jim Duckworth, WPI 25 The Process Statement - Module 4
Incorrect Process for Combinational Logic ENTITY comparator IS -- 4-bit magnitude comparator PORT(a,b : IN std_logic_vector(3 DOWNTO 0); equal, less, great : OUT std_logic); END comparator; ARCHITECTURE incorrect OF comparator IS PROCESS(a, b) IF a = b THEN equal <= '1'; ELSIF a <= b THEN less <= '1'; ELSIF a >= b THEN great <= '1'; END IF; END PROCESS; END incorrect; Jim Duckworth, WPI 26 The Process Statement - Module 4
Correct Process for Combinational Logic ENTITY comparator IS -- 4-bit magnitude comparator PORT(a,b : IN std_logic_vector(3 DOWNTO 0); equal, less, great : OUT std_logic); END comparator; ARCHITECTURE correct OF comparator IS PROCESS(a, b) equal <= '0'; less <= '0'; great <= '0'; IF a = b THEN equal <= '1'; ELSIF a <= b THEN less <= '1'; ELSIF a >= b THEN great <= '1'; END IF; END PROCESS; END correct; Jim Duckworth, WPI 27 The Process Statement - Module 4
Alternative Combinational Process ARCHITECTURE correct2 OF comparator IS -- same as previous? PROCESS(a, b) IF a = b THEN equal <= '1'; ELSE equal <= '0'; END IF; IF a <= b THEN less <= '1'; ELSE less <= '0'; END IF; IF a >= b THEN great <= '1'; ELSE great <= '0'; END IF; END PROCESS; END correct2; Jim Duckworth, WPI 28 The Process Statement - Module 4
Concurrent Statements (preferred) ARCHITECTURE preferred OF comparator IS equal <= 1 WHEN a = b ELSE 0 ; less <= 1 WHEN a <= b ELSE 0 ; great <= 1 WHEN a >= b ELSE 0 ; END preferred; Jim Duckworth, WPI 29 The Process Statement - Module 4