ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic George Mason University
Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 3, RT-level combinational circuit Sections 3., 3.2, 3.3, 3.6, 3.7., 3.7.3. Recommended S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design Chapter 6, Combinational-Circuit Building Blocks Chapter 5.5, Design of Arithmetic Circuits Using CAD Tools 2
Types of VHDL Description (Modeling Styles) 3
Types of VHDL Description VHDL Descriptions dataflow structural Testbenches behavioral Concurrent statements Components and interconnects Sequential statements Registers State machines Instruction decoders Subset most suitable for synthesis 4
Synthesizable VHDL Dataflow VHDL VHDL code synthesizable Dataflow VHDL VHDL code synthesizable 5
Data-Flow VHDL Concurrent Statements concurrent signal assignment ( ) conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) 6
Concurrent signal assignment <= target_signal <= expression; 7
Conditional concurrent signal assignment When - Else target_signal <= value when condition else value2 when condition2 else... valuen- when conditionn- else valuen; 8
Selected concurrent signal assignment With Select-When with choice_expression select target_signal <= expression when choices_, expression2 when choices_2,... expressionn when choices_n; 9
Modeling Wires and Buses
Signals SIGNAL a : STD_LOGIC; a wire SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO ); b 8 bus
Merging wires and buses a b c 5 4 d = a b c SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO ); SIGNAL c: STD_LOGIC; SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO ); d <= a & b & c; 2
Splitting buses d 4 5 a = d 9..6 b = d 5.. c = d SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO ); SIGNAL c: STD_LOGIC; SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO ); a <= d(9 downto 6); b <= d(5 downto ); c <= d(); 3
Combinational-Circuit Building Blocks 4
Fixed Shifters & Rotators 5
Fixed Logical Shift Right in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO ); 4 A >> C 4 L A(3) A(2) A() A() A(3) A(2) A() A C C = '' & A(3 downto ); 6
Fixed Arithmetic Shift Right in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO ); 4 A >> C 4 A A(3) A(2) A() A() A C A(3) A(3) A(2) A() C = A(3) & A(3 downto ); 7
Fixed Logical Shift Left in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO ); 4 A << C 4 L A(3) A(2) A() A() A(2) A() A() C = A(2 downto ) & ''; A C 8
Fixed Rotation Left in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO ); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO ); 4 A <<< C 4 A(3) A(2) A() A() A(2) A() A() A(3) C = A(2 downto ) & A(3); A C 9
Variable Rotators 2
8-bit Variable Rotator Left A 8 3 B A <<< B C 8 To be covered during one of the future classes 2
Gates 22
Basic Gates AND, OR, NOT x x x x 2 2 x x 2 x n x x 2 x n (a) AND gates x x x + x 2 2 x x 2 x n x + x 2 + + x n (b) OR gates x x (c) NOT gate 23
Basic Gates NAND, NOR x x 2 x x x x 2 2 x x 2 x n x n (a) NAND gates x x x x + x 2 2 x 2 x + x 2 + + x n x n (b) NOR gates 24
DeMorgan s Theorem and other symbols for NAND, NOR x x 2 x x 2 x x 2 (a) x x 2 = x + x 2 x x 2 x x 2 x x 2 (b) x + x 2 = x x 2 25
Basic Gates XOR x x 2 f = x x 2 x x 2 f = x x 2 (a) Truth table (b) Graphical symbol x x 2 f = x x 2 (c) Sum-of-products implementation 26
Basic Gates XNOR x x 2 f = x x 2 x x 2 f = x x 2 = x. x 2 (a) Truth table (b) Graphical symbol x x 2 f = x x 2 (c) Sum-of-products implementation 27
Data-flow VHDL: Example x y cin s cout 28
Data-flow VHDL: Example () LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY fulladd IS PORT ( x : IN STD_LOGIC ; y : IN STD_LOGIC ; cin : IN STD_LOGIC ; s : OUT STD_LOGIC ; cout : OUT STD_LOGIC ) ; END fulladd ; 29
Data-flow VHDL: Example (2) ARCHITECTURE dataflow OF fulladd IS BEGIN s <= x XOR y XOR cin ; cout <= (x AND y) OR (cin AND x) OR (cin AND y) ; END dataflow ; 3
Logic Operators Logic operators and or nand nor xor not xnor Logic operators precedence only in VHDL-93 Highest Lowest not and or nand nor xor xnor 3
No Implied Precedence Wanted: y = ab + cd Incorrect y <= a and b or c and d ; equivalent to y <= ((a and b) or c) and d ; equivalent to y = (ab + c)d Correct y <= (a and b) or (c and d) ; 32
Multiplexers 33
2-to- Multiplexer s s f w f w w w (a) Graphical symbol (b) Truth table VHDL: f <= w WHEN s = '' ELSE w ; or f <= w WHEN s = ' ELSE w ; 34
VHDL code for a 2-to- Multiplexer Entity LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY mux2to IS PORT ( w, w, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to ; ARCHITECTURE dataflow OF mux2to IS BEGIN f <= w WHEN s = '' ELSE w ; END dataflow ; 35
Cascade of two multiplexers w 3 w 2 y w VHDL: s2 s f <= w WHEN s = ' ELSE w2 WHEN s2 = ELSE w3 ; 36
VHDL design entity implementing a cascade of two multiplexers LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY mux_cascade IS PORT ( w, w2, w3: IN STD_LOGIC ; s, s2 : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux_cascade ; ARCHITECTURE dataflow OF mux2to IS BEGIN f <= w WHEN s = ' ELSE w2 WHEN s2 = ELSE w3 ; END dataflow ; 37
Operators Relational operators = /= < <= > >= Logic and relational operators precedence Highest Lowest not = /= < <= > >= and or nand nor xor xnor 38
Priority of logic and relational operators compare a = bc Incorrect when a = b and c else equivalent to when (a = b) and c else Correct when a = (b and c) else 39
4-to- Multiplexer (a) Graphic symbol (b) Truth table s s s s s f w w w 2 w 3 f w w w 2 w 3 WITH s SELECT f <= w WHEN "", w WHEN "", w2 WHEN "", w3 WHEN OTHERS ; 4
VHDL code for a 4-to- Multiplexer entity LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY mux4to IS PORT ( w, w, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR( DOWNTO ) ; f : OUT STD_LOGIC ) ; END mux4to ; ARCHITECTURE dataflow OF mux4to IS BEGIN WITH s SELECT f <= w WHEN "", w WHEN "", w2 WHEN "", w3 WHEN OTHERS ; END dataflow ; 4
Decoders 42
2-to-4 Decoder (b) Graphical symbol (a) Truth table w w y 3 En w w y 3 y 2 y y w y 2 y En y y x x Enw <= En & w ; WITH Enw SELECT y <= "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN OTHERS ; 43
VHDL code for a 2-to-4 Decoder entity LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR( DOWNTO ) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(3 DOWNTO ) ) ; END dec2to4 ; ARCHITECTURE dataflow OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO ) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN OTHERS ; END dataflow ; 44
Encoders 45
Priority Encoder w w w w 2 w 3 y y z y y <= "" WHEN w(3) = '' ELSE "" WHEN w(2) = '' ELSE "" WHEN w() = '' ELSE "" ; w 3 w 2 w w y y z z <= '' WHEN w = "" ELSE '' ; - - - - - - d d 46
VHDL code for a Priority Encoder entity LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY priority IS PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; y : OUT STD_LOGIC_VECTOR( DOWNTO ) ; z : OUT STD_LOGIC ) ; END priority ; ARCHITECTURE dataflow OF priority IS BEGIN y <= "" WHEN w(3) = '' ELSE "" WHEN w(2) = '' ELSE "" WHEN w() = '' ELSE "" ; z <= '' WHEN w = "" ELSE '' ; END dataflow ; 47
Adders 48
6-bit Unsigned Adder 6 6 Cout X + S Y Cin 6 49
Operations on Unsigned Numbers For operations on unsigned numbers USE ieee.std_logic_unsigned.all and signals of the type STD_LOGIC_VECTOR OR USE ieee.numeric_std.all and signals of the type UNSIGNED and conversion functions: std_logic_vector(), unsigned() 5
VHDL code for a 6-bit Unsigned Adder LIBRARY ieee ; USE ieee.std_logic_64.all ; USE ieee.std_logic_unsigned.all ; ENTITY adder6 IS PORT ( Cin : IN STD_LOGIC ; X : IN STD_LOGIC_VECTOR(5 DOWNTO ) ; Y : IN STD_LOGIC_VECTOR(5 DOWNTO ) ; S : OUT STD_LOGIC_VECTOR(5 DOWNTO ) ; Cout : OUT STD_LOGIC ) ; END adder6 ; ARCHITECTURE dataflow OF adder6 IS SIGNAL Sum : STD_LOGIC_VECTOR(6 DOWNTO ) ; BEGIN Sum <= ('' & X) + Y + Cin ; S <= Sum(5 DOWNTO ) ; Cout <= Sum(6) ; END dataflow ; 5
Addition of Unsigned Numbers () LIBRARY ieee ; USE ieee.std_logic_64.all ; USE ieee.numeric_std.all ; ENTITY adder6 IS PORT ( Cin : IN STD_LOGIC ; X : IN STD_LOGIC_VECTOR(5 DOWNTO ) ; Y : IN STD_LOGIC_VECTOR(5 DOWNTO ) ; S : OUT STD_LOGIC_VECTOR(5 DOWNTO ) ; Cout : OUT STD_LOGIC ) ; END adder6 ; 52
Addition of Unsigned Numbers (2) ARCHITECTURE dataflow OF adder6 IS SIGNAL Xu : UNSIGNED(5 DOWNTO ); SIGNAL Yu: UNSIGNED(5 DOWNTO ); SIGNAL Su : UNSIGNED(6 DOWNTO ) ; BEGIN Xu <= unsigned(x); Yu <= unsigned(y); Su <= ('' & Xu) + Yu + unsigned('' & Cin) ; S <= std_logic_vector(su(5 DOWNTO )) ; Cout <= Su(6) ; END dataflow ; 53
Addition of Unsigned Numbers (3) ARCHITECTURE dataflow OF adder6 IS signal Sum: STD_LOGIC_VECTOR(6 DOWNTO ) ; BEGIN Sum <= std_logic_vector( unsigned('' & X) + unsigned(y) + unsigned('' & Cin) ) ; S <= Sum(5 downto ); Cout <= Sum(6) ; END dataflow ; 54
Operations on Signed Numbers For operations on signed numbers USE ieee.numeric_std.all, signals of the type SIGNED, and conversion functions: std_logic_vector(), signed() OR USE ieee.std_logic_signed.all and signals of the type STD_LOGIC_VECTOR 55
Signed and Unsigned Types Behave exactly like STD_LOGIC_VECTOR plus, they determine whether a given vector should be treated as a signed or unsigned number. Require USE ieee.numeric_std.all; 56
Multipliers 57
Unsigned vs. Signed Multiplication Unsigned Signed 5 - x x 5 x x - 225 58
8x8-bit Unsigned Multiplier 8 8 a b * c U 6 59
Multiplication of unsigned numbers LIBRARY ieee; USE ieee.std_logic_64.all; USE ieee.std_logic_unsigned.all ; entity multiply is port( a : in STD_LOGIC_VECTOR(7 downto ); b : in STD_LOGIC_VECTOR(7 downto ); c : out STD_LOGIC_VECTOR(5 downto ) ); end multiply; architecture dataflow of multiply is begin c <= a * b; end dataflow; 6
8x8-bit Signed Multiplier 8 8 a b * c S 6 6
Multiplication of signed numbers LIBRARY ieee; USE ieee.std_logic_64.all; USE ieee.std_logic_signed.all ; entity multiply is port( a : in STD_LOGIC_VECTOR(7 downto ); b : in STD_LOGIC_VECTOR(7 downto ); c : out STD_LOGIC_VECTOR(5 downto ) ); end multiply; architecture dataflow of multiply is begin c <= a * b; end dataflow; 62
8x8-bit Unsigned and Signed Multiplier 8 8 a cu * b cs 6 6 63
Multiplication of signed and unsigned LIBRARY ieee; USE ieee.std_logic_64.all; USE ieee.numeric_std.all ; numbers entity multiply is port( a : in STD_LOGIC_VECTOR(7 downto ); b : in STD_LOGIC_VECTOR(7 downto ); cu : out STD_LOGIC_VECTOR(5 downto ); cs : out STD_LOGIC_VECTOR(5 downto ) ); end multiply; architecture dataflow of multiply is begin -- signed multiplication cs <= STD_LOGIC_VECTOR(SIGNED(a)*SIGNED(b)); -- unsigned multiplication cu <= STD_LOGIC_VECTOR(UNSIGNED(a)*UNSIGNED(b)); end dataflow; 64
Comparators 65
4-bit Number Comparator 4 4 A B A > B AgtB AgtB <= '' WHEN A > B ELSE '' ; 66
VHDL code for a 4-bit Unsigned Number Comparator entity LIBRARY ieee ; USE ieee.std_logic_64.all ; USE ieee.std_logic_unsigned.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; AgtB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE dataflow OF compare IS BEGIN AgtB <= '' WHEN A > B ELSE '' ; END dataflow ; 67
VHDL code for a 4-bit Signed Number Comparator entity LIBRARY ieee ; USE ieee.std_logic_64.all ; USE ieee.std_logic_signed.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; AgtB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE dataflow OF compare IS BEGIN AgtB <= '' WHEN A > B ELSE '' ; END dataflow ; 68
Buffers 69
Tri-state Buffer e x f e = (a) A tri-state buffer x f e x f Z Z x e = (b) Equivalent circuit f (c) Truth table 7
Four types of Tri-state Buffers e e x f x f f <= x WHEN (e(a) = '') ELSE 'Z'; f <= not x WHEN (b) (e = '') ELSE 'Z'; e e x f x f f <= x WHEN (e(c) = '') ELSE 'Z'; f <= not x WHEN (d) (e = '') ELSE 'Z'; 7
Tri-state Buffer entity () LIBRARY ieee; USE ieee.std_logic_64.all; ENTITY tri_state IS PORT ( e: IN STD_LOGIC; x: IN STD_LOGIC; f: OUT STD_LOGIC ); END tri_state; 72
Tri-state Buffer entity (2) ARCHITECTURE dataflow OF tri_state IS BEGIN f <= x WHEN (e = ) ELSE Z ; END dataflow; 73
ROM 74
ROM 8x6 example () Addr 3 8x6 ROM Dout 6 C 75
ROM 8x6 example (2) LIBRARY ieee; USE ieee.std_logic_64.all; USE ieee.numeric_std.all; ENTITY rom IS PORT ( ); Addr : IN STD_LOGIC_VECTOR(2 DOWNTO ); Dout : OUT STD_LOGIC_VECTOR(5 DOWNTO ) END rom; 76
ROM 8x6 example (3) ARCHITECTURE dataflow OF rom IS SIGNAL temp: INTEGER RANGE TO 7; TYPE vector_array IS ARRAY ( to 7) OF STD_LOGIC_VECTOR(5 DOWNTO ); CONSTANT memory : vector_array := ( X 8A", X"D459", X"A87", X"7853", X"65D", X"642F", X"F742", X"F548"); BEGIN temp <= to_integer(unsigned(addr)); Dout <= memory(temp); END dataflow; 77
Describing Combinational Logic Using Dataflow Design Style 78
MLU Example 79
MLU Block Diagram A A MUX_ MUX_4_ NEG_A MUX_ MUX_2 IN IN IN2 OUTPUT IN3 SEL SEL Y Y NEG_Y B B L L NEG_B MUX_3
MLU: Entity Declaration LIBRARY ieee; USE ieee.std_logic_64.all; ENTITY mlu IS PORT( NEG_A : IN STD_LOGIC; NEG_B : IN STD_LOGIC; NEG_Y : IN STD_LOGIC; A : IN STD_LOGIC; B : IN STD_LOGIC; L : IN STD_LOGIC; L : IN STD_LOGIC; ); END mlu; Y : OUT STD_LOGIC 8
MLU: Architecture Declarative Section ARCHITECTURE mlu_dataflow OF mlu IS SIGNAL A : STD_LOGIC; SIGNAL B : STD_LOGIC; SIGNAL Y : STD_LOGIC; SIGNAL MUX_ : STD_LOGIC; SIGNAL MUX_ : STD_LOGIC; SIGNAL MUX_2 : STD_LOGIC; SIGNAL MUX_3 : STD_LOGIC; SIGNAL L: STD_LOGIC_VECTOR( DOWNTO ); 82
MLU - Architecture Body BEGIN A<= NOT A WHEN (NEG_A='') ELSE A; B<= NOT B WHEN (NEG_B='') ELSE B; Y <= NOT Y WHEN (NEG_Y='') ELSE Y; MUX_ <= A AND B; MUX_ <= A OR B; MUX_2 <= A XOR B; MUX_3 <= A XNOR B; L <= L & L; with (L) select Y <= MUX_ WHEN "", MUX_ WHEN "", MUX_2 WHEN "", MUX_3 WHEN OTHERS; END mlu_dataflow; 83
Logic Implied Most Often by Conditional and Selected Concurrent Signal Assignments 84
Data-flow VHDL Major instructions Concurrent statements concurrent signal assignment ( ) conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) 85
Conditional concurrent signal assignment When - Else target_signal <= value when condition else value2 when condition2 else... valuen- when conditionn- else valuen; 86
Most often implied structure When - Else target_signal <= value when condition else value2 when condition2 else... valuen- when conditionn- else valuen; Value N Value N- Condition N-. Value 2 Value Target Signal Condition 2 Condition 87
Data-flow VHDL Major instructions Concurrent statements concurrent signal assignment ( ) conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) 88
Selected concurrent signal assignment With Select-When with choice_expression select target_signal <= expression when choices_, expression2 when choices_2,... expressionn when choices_n; 89
Most Often Implied Structure With Select-When with choice_expression select target_signal <= expression when choices_, expression2 when choices_2,... expressionn when choices_n; expression expression2 choices_ choices_2 target_signal expressionn choices_n choice expression 9
Allowed formats of choices_k WHEN value WHEN value_ value_2... value N WHEN OTHERS 9
Allowed formats of choice_k - example WITH sel SELECT y <= a WHEN "", c WHEN "" "", d WHEN OTHERS; 92
when-else vs. with-select-when () "when-else" should be used when: ) there is only one condition (and thus, only one else), as in the 2-to- MUX 2) conditions are independent of each other (e.g., they test values of different signals) 3) conditions reflect priority (as in priority encoder); one with the highest priority need to be tested first. 93
when-else vs. with-select-when (2) "with-select-when" should be used when there is ) more than one condition 2) conditions are closely related to each other (e.g., represent different ranges of values of the same signal) 3) all conditions have the same priority (as in the 4-to- MUX). 94