Lecture 9
Topics Midterm Finish Chapter 7
Xilinx FPGAs
Chapter 7 Spartan 3E Architecture Source: Spartan-3E FPGA Family Datasheet CLB Configurable Logic Blocks Each CLB contains four slices Each slice contains two Look Up Tables (LUTs) Implements logic functions Can be configured as 16x1 memory (RAM16) Can be configured as a 16-bit shift register (SRL16) Each slice contains two storage elements Implements flip flops or latches
Spartan 3E Architecture LUTs in SLICEM can be programmed as distributed 16x1 RAM Can be configured to store larger amounts 16x4, 32x2, 64x1 in one CLB Can also be configured as dual port using two LUTs Same data written to both 16x1 memories Independent read addresses and outputs
Spartan 3E Architecture
Spartan 3E Architecture LUTs The F and G LUTs in a slice have four logic inputs (A1-A4) and a single output (D). Any four variable Boolean logic operation can be implemented using one LUT.
Spartan 3E Architecture
Spartan 3E Architecture Wide Multiplexer Each slice has two mutliplexers F5MUX multiplexes the two LUTs in a slice. FiMUX multiplexes the two CLB inputs See figure 20 of Spartan 3E datasheet for feedback routing
Spartan 3E Architecture Carry and Arithmetic Logic Full Adder Cin A B Sum Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 0 1 1 1 1 0
Spartan 3E Architecture Multiplication Useful for small multipliers Use dedicated 18x18 multiplier blocks for larger
Spartan 3E Architecture Storage Elements Programmable as either a D-type FF or latch
Sequential Logic (i.e. Registers, FF s) Reset always @(posedge CLK or posedge RST) if (RST) Q <= 1'b0; else Q <= (F G H) & (A (B & C & D & E)); More difficult timing analysis Less than optimal optimization by the synthesis tool
Sequential Logic (i.e. Registers, FF s) Reset (cont.) always @(posedge CLK) if (RST) Q <= 1'b0; else Q <= (F G H) & (A (B & C & D & E));
Spartan 3E Architecture Shift Registers Each SLICEM LUT can be programmed as a 16-bit shift register Delay data from 1 to 16 clock cycles w/o using FFs. Can cascade to form larger shift registers The four SLICEM LUTs of a CLB can be combined to produce a 64 bit shift register The CLB FF can be used for one more shift delay
Instantiation of Design Elements Inferred always @(I0 or I1 or S) begin if (S==0) O = I0; else O = I1; Explicit MUXF5 MUXF5_inst (.O(O), // Output of MUX to general routing.i0(i0), // Input (tie directly to the output of LUT4).I1(I1), // Input (tie directly to the output of LUT4).S(S) // Input select to MUX Library guide for MUXF5 recommends inferred but some design elements can only be explicitly instantiated (e.g. KEEPER)
Initialization Set, Resets, and Synthesis Optimization Xilinx FPGA devices have abundant flip-flops. All architectures support an asynchronous reset for those registers and latches. Even though this capability exists, Xilinx does not recommend that you code for it. Using asynchronous resets may result in: More difficult timing analysis Less optimal optimization by the synthesis tool The timing hazard which an asynchronous reset poses on a synchronous system is well known. Less well known is the optimization trade-off which the asynchronous reset poses on a design. Global Set/Reset (GSR) All Xilinx FPGA devices have a dedicated asynchronous reset called Global Set/Reset (GSR). GSR is automatically asserted at the end of FPGA configuration, regardless of the design. For gate-level simulation, this GSR signal is also inserted to mimic this operation to allow accurate simulation of the initialized design as it happens in the silicon. Adding another asynchronous reset to the actual code only duplicates this dedicated feature. It is not necessary for device initialization or simulation initialization. Source: Xilinx Synthesis and Simulation Deign Guide (UG626)
Initialization Initial State of the Registers and Latches FPGA flip-flops are configured as either preset (asynchronous set) or clear (asynchronous reset) during startup. This is known as the initialization state, or INIT. The initial state of the register can be specified as follows: If the register is instantiated, it can be specified by setting the INIT generic/parameter value to either a 1or 0, depending on the desired state. For more information, see the Libraries Guides. If the register is inferred, the initial state can be specified by initializing the VHDL signal declaration or the Verilog reg declaration as shown in the following coding examples. Initial State of the Registers and Latches Verilog Coding Example One reg register1 = 1 b0; // specifying regsiter1 to start as a zero reg register2 = 1 b1; // specifying register2 to start as a one reg [3:0] register3 = 4 b1011; //specifying INIT value for 4-bit register Initial State of the Registers and Latches Verilog Coding Example Two Another possibility in Verilog is to use an initial statement: reg [3:0] register3; initial begin register3= 4 b1011; end Note: Not all synthesis tools support this initialization Note: Your simulation will match your implementation if you use this coding style. Otherwise your simulation will initialize registers to X whereas the registers will initialize to 0 on the FPGA. Source: Xilinx Synthesis and Simulation Deign Guide (UG626)
Homework 7.9 7.11 7.12 7.13