FPGA briefing Part II FPGA development FPGA development 1
FPGA development FPGA development : Domain level analysis (Level 3). System level design (Level 2). Module level design (Level 1). Academical focus is on level 3. Commercial tool development focus is on level 2 Free tools are at level 1. Module design level Module level design (level 1): Programming languages. FPGA development proces Design tools. Specification : Describes : requirements, use cases. Form : Text, UML, Matlab model. System level design : Describes : Architecture, Interfaces, modules and components. Form : UML diagrams, SystemC, others. Module design : Form : Dedicated languages, VHDL, C. FPGA tools 2
Programming languages High level languages : Hardware description Language, Europe => VHDL (, US=>Verilog.) HandelC (C based system level design language). SystemC (C++ based system level design language). HandelC and SystemC code is typically translated to VHDL by the tools, reusing VHDL to FPGA toolchains. VHDL Originally an initiative of the U.S. government in 1980 to advance the state-of-the-art in silicon technology. IEEE standardized in 87, 93 and 2000 versions. Abstractions levels covers from algorithmic models to gate level. Allows technology independent description. 3
VHDL examples - structural Object oriented language: entity (external view) and architecture (internal view). library IEEE; use IEEE.std_logic_1164.all; use work.math_pack.all; entity counter is port (count_o : out std_logic_vector(7 downto 0); clk_i : in std_logic; reset_i : in std_logic); end; architecture arch_one of counter is signal count_s : std_logic_vector (7 downto 0); begin counter: process(clk_i, reset_i) begin if (reset_i = '1') then if reset_i'event then count_s <= (others => '0'); end if; elsif clk_i'event and (clk_i = '1') then count_s <= increment(count_s); end if; end process; count_o <= count_s; end arch_one; VHDL example - behavioral Black box description like. If i give this input, then this output will be present after a given time. clk_s <= not clk_s after 20 ns; reset_n_s <= 1 after 10 ns; user_input_s <= open door after 100 ns; 4
FPGA development process Verification is a huge Part of working with FPGAs approximately 70 %. VHDL models are verified with a simulator. VHDL models System design specification Simulation and verification Testbenches for models Verification with a simulator requires a testbench which models the environment of the FPGA. VHDL syntese Place and route Programmable file VHDL models and testbenches A system model needs to be built, which contains the modules dscribed in the system design specification. A testbench is made for the over-all system, modelling the system environment, and by doing this can verify the system behavior and interfaces. 5
VHDL models creating infra structure Integration of Modules IP cores, and other modules onto a bus structure. VHDL models design rules Design rules must be used when writing VHDL models. Design rule examples for FPGA s Do not use tri-state logic for standard modules. Avoid instantiating FPGA specific components in VHDL code, this makes it hard to re-use the model with another FPGA. Use compile switches to switch between simulation components and FPGA target components like memory. Use synchronously logic. Be avare of clock domain shifts. 6
Testbenches Testbenches often use file I/O for reading test data and writing results to files. Advanced techniques as transaction based modelling modelling for instance verification of an IP block with a write access (writing a value to the module) and a read access (reading a return value). Functional simulation Testbench and system models are loaded into the simulator. The simulator makes syntax checks and compiles the VHDL code. The simulator (Modelsim a.o.) operates with time. 7
Functional simulation - continued Simulator output can be checked manually by viewing waveforms or automatically by the testbench. Simulators can also perform functions as code coverage and code profiling when executing the testbench tests. Simulators Modelsim from Mentor Graphics is more or less a defacto standard for simulation of VHDL, Verilog or SystemC models. Is available from free of charge versions from FPGA vendors (VHDL or Verilog only) to expensive ASIC tape out versions. 8
Modelsim XE-III FPGA Synthesis FPGA synthesis is the process of converting the VHDL design to a netlist of specific FPGA logic components, like LUTs, Flip-Flops etc. 9
Synthesis Synthesis tools comes with libraries of the FPGA components they support. When new components are available so will the libraries be. Used to an area covered only by third party tool vendors (non-fpga vendors), but now for instance Xilinx have their synthesis tool XST in a free version, covering not all but most FPGAs in their product line. Place and route Place and route tools are performing the task of placing the synthesized logic on the target FPGA and routing the connections through columns and row interconnects in a way that meets the constraints of the design. 10
Place and route constraints Pin constraints to the PCB. Clock constraint, how fast must the system be 10Mhz or 400 MHz? Logic block constraints, placement of IP cores. Place and route tools Are typically delivered by the FPGA vendor, and can be free of charge. Example Xilinx ISE webpack (includes also XST synthesis). 11
Bitfile generation The bitfile contains the programable code for the FPGA. Encryption of bit file? How should the device be programmed? FPGA configurations - examples Master Slave CPU /8 FPGA Slave Master Serial flash or EEPROM /1 FPGA 12
System level design (level 2) Advantages : HW/SW co-design. Architecture exploration. Make important design decision early. Specification : Describes : requirements, use cases. Form : Text, UML, Matlab model. System level design : Describes : Architecture, Interfaces, modules and components. Form : UML diagrams, SystemC, others. Module design : Form : Dedicated languages, VHDL, C. FPGA tools System level design (level 2) SystemC is a IEEE standard and a til C++ library (can be downloaded free from www.systemc.org). Is a merge of C++(SW) og VHDL(HW), ideal for HW/SW co-design. Operates with tid, which gives opportunities for simulation of the system against real time requirements. System level design language, which separates functionality from communication. 13
System level design (level 2) SystemC verification : SystemC is C++ + time. Re-use of system models. Quick generation of VHDL models (prototyping/proof-ofconcept). Digital designer - responsiblities Digital designer : Defines system architecture. Creates system level models. Creates system views static, dynamic, logical and physical. Designs the system interfaces. Verifies system architecture, system interfaces in a simulator. 14
Digital designer - challenges Organisatorial placement. Process power. Personal characteristica. SW background, learn bit of HW and vice versa. Domain analysis level (level 3) Advantages : Very high level and simple functional models can be verified. Verification of requirements through the whole process. Higher probability of implementing the system that the customer wants. 15
Welcome to a world of opportunities You are all hereby invited to discuss challenges and opportunities poul.lumholtz@teknologisk.dk 16