Reading Object Code. A Visible/Z Lesson

Similar documents
Reading Object Code. A Visible/Z Lesson

Background/Review on Numbers and Computers (lecture)

Chapter 2: Introduction to Maple V

Chapter 6 What's this Stuff on the Left?

CS:APP2e Web Aside ASM:X87: X87-Based Support for Floating Point

ZDT -A Debugging Program for the Z80

Analysis of input and output configurations for use in four-valued CCD programmable logic arrays

Total 100

Compilation Lecture 11a. Register Allocation Noam Rinetzky. Text book: Modern compiler implementation in C Andrew A.

'* ~rr' _ ~~ f' lee : eel. Series/1 []J 0 [[] "'l... !l]j1. IBM Series/1 FORTRAN IV. I ntrod uction ...

Graph-Based vs Depth-Based Data Representation for Multiview Images

COMP 181. Prelude. Intermediate representations. Today. Types of IRs. High-level IR. Intermediate representations and code generation

On - Line Path Delay Fault Testing of Omega MINs M. Bellos 1, E. Kalligeros 1, D. Nikolos 1,2 & H. T. Vergos 1,2

Pipelined Multipliers for Reconfigurable Hardware

Exploring the Commonality in Feature Modeling Notations

System-Level Parallelism and Throughput Optimization in Designing Reconfigurable Computing Applications

Outline: Software Design

represent = as a finite deimal" either in base 0 or in base. We an imagine that the omputer first omputes the mathematial = then rounds the result to

Introduction to Seismology Spring 2008

Learning Convention Propagation in BeerAdvocate Reviews from a etwork Perspective. Abstract

Extracting Partition Statistics from Semistructured Data

HEXA: Compact Data Structures for Faster Packet Processing

Allocating Rotating Registers by Scheduling

Graphs in L A TEX. Robert A. Beeler. January 8, 2017

Partial Character Decoding for Improved Regular Expression Matching in FPGAs

Assembler Programming

Direct-Mapped Caches

OFF-LINE ROBOT VISION SYSTEM PROGRAMMING USING A COMPUTER AIDED DESIGN SYSTEM S. SRIDARAN. Thesis submitted to the Faculty of the

Defect Detection and Classification in Ceramic Plates Using Machine Vision and Naïve Bayes Classifier for Computer Aided Manufacturing

Page INTRODUCTION PART I - THE PLATO SYSTEM

13.1 Numerical Evaluation of Integrals Over One Dimension

UCSB Math TI-85 Tutorials: Basics

Gray Codes for Reflectable Languages

Algorithms, Mechanisms and Procedures for the Computer-aided Project Generation System

MATH STUDENT BOOK. 12th Grade Unit 6

Contents Contents...I List of Tables...VIII List of Figures...IX 1. Introduction Information Retrieval... 8

EXODUS II: A Finite Element Data Model

Performance Benchmarks for an Interactive Video-on-Demand System

1. The collection of the vowels in the word probability. 2. The collection of real numbers that satisfy the equation x 9 = 0.

Assembler Language "Boot Camp" Part 3 - Assembly and Execution; Branching SHARE 115 in Boston August 3, 2009

Path Sharing and Predicate Evaluation for High-Performance XML Filtering*

Algorithms for External Memory Lecture 6 Graph Algorithms - Weighted List Ranking

the data. Structured Principal Component Analysis (SPCA)

Video Data and Sonar Data: Real World Data Fusion Example

Connection Guide. Installing the printer locally (Windows) What is local printing? Installing the printer using the Software and Documentation CD

And, the (low-pass) Butterworth filter of order m is given in the frequency domain by

What are Cycle-Stealing Systems Good For? A Detailed Performance Model Case Study

with respect to the normal in each medium, respectively. The question is: How are θ

timestamp, if silhouette(x, y) 0 0 if silhouette(x, y) = 0, mhi(x, y) = and mhi(x, y) < timestamp - duration mhi(x, y), else

Assembler Language "Boot Camp" Part 2 - Instructions and Addressing. SHARE 118 in Atlanta Session March 12, 2012

SAND Unlimited Release Printed November 1995 Updated November 29, :26 PM EXODUS II: A Finite Element Data Model

Assembler Language "Boot Camp" Part 2 - Instructions and Addressing SHARE 116 in Anaheim February 28, 2011

COST PERFORMANCE ASPECTS OF CCD FAST AUXILIARY MEMORY

The recursive decoupling method for solving tridiagonal linear systems

1 The Knuth-Morris-Pratt Algorithm

Department of Electrical Engineering and Computer Science MASSACHUSETTS INSTITUTE OF TECHNOLOGY Fall Test I Solutions

An Evaluation of Automatic and Interactive Parallel Programming Tools

SYS-ED/COMPUTER EDUCATION TECHNIQUES, INC.

Cluster Centric Fuzzy Modeling

特集 Road Border Recognition Using FIR Images and LIDAR Signal Processing

PASCAL 64. "The" Pascal Compiler for the Commodore 64. A Data Becker Product. >AbacusiII Software P.O. BOX 7211 GRAND RAPIDS, MICK 49510

Self-Adaptive Parent to Mean-Centric Recombination for Real-Parameter Optimization

Design Implications for Enterprise Storage Systems via Multi-Dimensional Trace Analysis

CA Release Automation 5.x Implementation Proven Professional Exam (CAT-600) Study Guide Version 1.1

Scheduling Multiple Independent Hard-Real-Time Jobs on a Heterogeneous Multiprocessor

Connection Guide. Installing the printer locally (Windows) What is local printing? Installing the printer using the Software and Documentation CD

Adobe Certified Associate

Reverse Engineering of Assembler Programs: A Model-Based Approach and its Logical Basis

Coupling of MASH-MORSE Adjoint Leakages with Spaceand Time-Dependent Plume Radiation Sources

An Event Display for ATLAS H8 Pixel Test Beam Data

AN INTRODUCTION TO FORTRAN AND NUMERICAL MODELING

Design Patterns. Patterns.mkr Page 223 Wednesday, August 25, :17 AM

Multiple Assignments

PROJECT PERIODIC REPORT

Re-programming a many-to-many merge with Hash Objects

NONLINEAR BACK PROJECTION FOR TOMOGRAPHIC IMAGE RECONSTRUCTION. Ken Sauer and Charles A. Bouman

Drawing lines. Naïve line drawing algorithm. drawpixel(x, round(y)); double dy = y1 - y0; double dx = x1 - x0; double m = dy / dx; double y = y0;

The Mathematics of Simple Ultrasonic 2-Dimensional Sensing

Improved Vehicle Classification in Long Traffic Video by Cooperating Tracker and Classifier Modules

Rapid, accurate particle tracking by calculation of radial symmetry centers

Data I/O and Post- Processing Utilities

Assembler Language "Boot Camp" Part 5 - Decimal and Logical Instructions. SHARE 117 in Orlando Session 9214 August 11, 2011

Evolutionary Feature Synthesis for Image Databases

Staircase Join: Teach a Relational DBMS to Watch its (Axis) Steps

Accommodations of QoS DiffServ Over IP and MPLS Networks

Calculation of typical running time of a branch-and-bound algorithm for the vertex-cover problem

Sparse Certificates for 2-Connectivity in Directed Graphs

Exploiting Enriched Contextual Information for Mobile App Classification

Define - starting approximation for the parameters (p) - observational data (o) - solution criterion (e.g. number of iterations)

Automated Test Generation from Vulnerability Signatures

CA Test Data Manager 4.x Implementation Proven Professional Exam (CAT-681) Study Guide Version 1.0

Type RS Instruction Format This is a four byte instruction of the form OP R1,R3,D2(B2). Type Bytes Operands RS 4 R1,R3,D2(B2) OP R 1 R 3 B 2

CleanUp: Improving Quadrilateral Finite Element Meshes

PHYS 3437: Computational Methods in Physics, Assignment 2

Rotation Invariant Spherical Harmonic Representation of 3D Shape Descriptors

Tavultesoft Keyboard Manager. User s Guide and Reference. Tavultesoft

PACKED DECIMAL ARITHMETIC

Tree Awareness for Relational DBMS Kernels: Staircase Join

A DYNAMIC ACCESS CONTROL WITH BINARY KEY-PAIR

Supplementary Material: Geometric Calibration of Micro-Lens-Based Light-Field Cameras using Line Features

Transcription:

Reading Objet Code A Visible/Z Lesson The Idea: When programming in a high-level language, we rarely have to think about the speifi ode that is generated for eah instrution by a ompiler. But as an assembly programmer, it is ritial that we be able to read the mahine ode that is produed for eah instrution. Otherwise, there will be programs that are extremely diffiult to understand and debug. VisibleZ was built to help you visualize eah instrution as it appears in objet ode and wath it exeute. When the assembler proesses an instrution, it onverts the instrution from its mnemoni form to a standard mahine-language (binary) format alled an instrution format. In the proess of onversion, the assembler must determine the type of instrution, onvert symboli labels and expliit notation to a base/displaement format, determine lengths of ertain operands, and parse any literals and onstants. Consider the following Move Charater instrution, MVC COSTOUT,COSTIN The assembler must determine the operation ode (x D2 ) for MVC, determine the length of COSTOUT, and ompute base/displaement addresses for both operands. After assembly, the result whih is alled objet ode, might look something like the following in hexadeimal, D207C008C020 The assembler generated 6 bytes (12 hex digits) of objet ode in a Storage to Storage (SS) type one format. In order to understand the objet ode whih an assembler will

generate, we need some familiarity with 5 basi instrution formats (there are many other instrution types overing privileged, non-privileged, and semi-privileged instrutions whih are beyond the sope of this disussion). First we onsider the Storage to Storage type one (SS1) format listed below. This is the instrution format for the MVC instrution above. Byte 1 - mahine operation ode Byte 2 - length -1 in bytes assoiated with operand 1 Byte 3 and 4 - the base/displaement address assoiated with operand 1 Byte 5 and 6 - the base/displaement address assoiated with operand 2 Eah box represents one byte or 8 bits and eah letter represents a single hexadeimal digit or 4 bits. The subsripts indiate the number of the operand used in determining the ontents of the byte. For example, the instrution format indiates that operand 1 is used to ompute L1L1, the length assoiated with the instrution. If we reonsider the assembled form of the MVC instrution above we see that the op-ode is x D2, and the length, derived from COSTOUT, is listed as x 07. Sine the assembler always derements the length by 1 when onverting to mahine ode, we determine that COSTOUT is 8 bytes long - 8 bytes will be moved by this instrution. Additionally we see that the base register for COSTOUT is x C (register 12) and the displaement is x 008. The base/displaement address for COSTIN is x C020. Why was register 12 hosen as the base register? How were the displaements omputed? These parts of the objet ode ould not be determined by the information given in the example above. In order to determine base/displaement addresses we must examine the USING and DROP diretives that are oded in the program. These diretives are disussed in the topi alled BASE DISPLACEMENT ADDRESSING on the website.

Being able to read objet ode is a neessary skill for an assembler programmer as knowledge of an instrution s format gives several important lues about semantis of the instrution. For example, knowing that MVC is a storage to storage type one instrution, informs us that both operands are fields in memory and that the first operand will determine the number of bytes that will be moved. Sine the length (L1L1) oupies one byte or 8 bits, the maximum length we an reate is 2 8-1 = 255. Reall that the assembler derements the length when assembling, so the instrution is apable of moving a maximum of 256 bytes. The 256 byte limitation is shared by all storage to storage type one instrutions. Storage to Storage type two (SS2) is a variation on SS1. Byte 1 - mahine operation ode Byte 2 - L1 - the length assoiated with operand 1 (4 bits) L2 - the length assoiated with operand 2 (4 bits) Byte 3 and 4 - the base/displaement address assoiated with operand 1 Byte 5 and 6 - the base/displaement address assoiated with operand 2 The only differene between SS1 and SS2 is the length byte. Notie that both operands ontribute a length in the seond byte. Sine eah length is 4 bits, the maximum value that ould be represented is 2 4-1 = 15. Again, sine the assembler derements the length by 1, the instrution an proess operands that are large as 16 bytes. There are many arithmeti instrutions that require the mahine to use the length of both operands. Consider the example below,

Objet Code Soure Code AFIELD DS PL4 BFIELD DS PL2... FA31C300C304 AP AFIELD,BFIELD AP (Add Paked) is an instrution whose format is SS2. Looking at the objet ode that was generated, we see that x FA is the op-ode and that the length of the first operand is x 3 whih was omputed by subtrating 1 from the length of AFIELD. Similarly, the length of BFIELD was used to generate the seond length of x 1. In exeuting this instrution, the mahine makes use of the size of both fields. In this ase, a 2-byte field is added to a 4-byte field. A third type of instrution format is Register to Register (RR). Byte 1 - mahine operation ode Byte 2 - R1 - the register whih is operand 1 R2 - the register whih is operand 2 Instrutions of this type have two operands, both of whih are registers. An example of an instrution of this type is LR (Load Register). The effet of the instrution is to opy the ontents of the register speified by operand 2 into the register speified by operand 1. The following LR (Load Register) instrution,

LR R3,R12 would ause register 12 to be opied into register 3. The assembler would produe the objet ode listed below as a result of the LR instrution. 183C Examining the objet ode we see that the op-ode is x 18, operand 1 is register 3, and operand 2 is register 12. You should note that 4 bits are enough to represent any of the registers whih are numbered 0 through 15. A fourth type of instrution format is Register to Indexed Storage (RX). Byte 1 - mahine operation ode Byte 2 - R1 - the register whih is operand 1 X2 - the index register assoiated with operand 2 Byte 3 and 4 - the base/displaement address assoiated with operand 2 For instrutions of this type, the first operand is a register and the seond operand is a storage loation. The storage loation is designated by a base/displaement address as well as an index register. The subjet of index registers is disussed in the topi BASE DISPLACEMENT ADDRESSING. L (Load) is an example of an instrution of type RX. Consider the example below.

L R5,TABLE(R7) The Load instrution opies a fullword from memory into a register. The above instrution might assemble as follows, 5857C008 The op-ode is x 58, operand 1 is speified as x 5, the index register is denoted x 7 and Operand 2 generates the base/displaement address x C008. Again, from the information given in the example above, there is no way to determine how the base/displaement address was omputed without looking at the USING statements in the program. Related to the RX type is a similar instrution format alled Register to Storage (RS). In this type the index register is replaed by a register referene or a 4-bit mask (pattern) R3 below. One instrution whih has a Register to Storage format is STM (Store Multiple). An example of how STM an be oded is as follows, STM R14,R12,12(R13) The previous instrution would generate the following objet ode, 90ECD00C

where x 90 is the op-ode, x E = 14 is operand 1, x C = 12, is treated as R3, and x D00C is generated from an expliit base/displaement address (12(R13)). The fifth and final instrution format that we will onsider is alled Storage Immediate (SI). In this format, the seond operand, alled the immediate onstant, resides in the seond byte of the instrution. This onstant is usually speified as a self-defining term. The format for SI instrutions is listed below. Byte 1 - mahine operation ode Byte 2 - I2I2 - the immediate onstant denoted in operand 2 Byte 3 and 4 - the base/displaement address assoiated with operand 1 An example of a storage immediate instrution is Compare Logial Immediate (CLI). This instrution will ompare one byte in storage to the immediate byte whih resides in the instrution itself. We see from the instrution format that operand 2 is the immediate onstant. For example, onsider the instrution below. CLI CUSTTYPE,C A When assembled, the objet ode might look like the following,

95C1C100 The op-ode is x 95, the self-defining term C A is onverted to the EBCDIC representation x C1, and the variable CUSTTYPE would generate the base/displaement address x C100. Again, there is not enough information provided to determine the exat base/displaement address for CUSTTYPE. The x C100 address is merely an example of what might be generated. Trying It Out in VisibleZ: 1) Load the program readingobjetcode.obj from the \Codes diretory and single step through eah instrution. Identify the type and parts of eah instrution below. The ode doesn t do anything but is representative of the different instrution formats you will enounter. Answers are provided at the end. 90 e d0 0 Instrution Type 90 e d 00 0d 0 Instrution Type 0d 0

41 20 0 0e Instrution Type 41 2 0 00e d2 03 0 16 0 1a Instrution Type d2 03 016 01a 92 1 0 26 Instrution Type 92 1 026

fa 42 0 1e 0 23 Instrution Type fa 4 2 01e 023 07 f Instrution Type 07 f Answers: 90 e d0 0 Instrution Type = RS 90 = op ode (STM) e d = operand 1 register = operand 3 register = operand 2 base register 00 = operand 2 displaement

0d 0 Instrution Type = RR 0d = op ode (BASR) = operand 1 register 0 = operand 2 register 41 20 0 0e Instrution Type = RX 41 = op ode (LA) 2 = operand 1 register 0 = operand 2 index register (none) = operand 2 base register 00e = operand 2 displaement d2 03 0 16 0 1a Instrution Type = SS1 d2 = op ode (MVC) 03 = length of operand 1 (minus 1) = operand 1 base register 016 = operand 1 displaement = operand 2 base register 01a = operand 2 displaement

92 1 0 26 Instrution Type = SI 92 = op ode (MVI) 1 = immediate onstant (operand 2) = operand 1 base register 026 = operand 1 displaement fa 42 0 1e 0 23 Instrution Type = SS2 fa = op ode (AP) 4 = length of op 1 (minus 1) 2 = length of op 2 (minus 1) = operand 1 base register 01e = operand 1 displaement = operand 2 base register 023 = operand 2 displaement 07 f Instrution Type = RR 07 = op ode (BCR) f = operand 1 register = operand 2 register