Modeling and Verifying Mixed-Signal Designs with MATLAB and Simulink

Modeling and Verifying Mixed-Signal Designs with MATLAB and Simulink Arun Mulpur, Ph.D., MBA Industry Group Manager Communications, Electronics, Semiconductors, Software, Internet Energy Production, Medical Devices, Robotics 2014 MathWorks, Inc. 1

Mixed-Signal Design and Verification Challenges Difficult design trade-offs SPECIFICATION Limited analog design abstractions DIGITAL DESIGN ANALOG DESIGN Limited analog/digital links Slow design iterations IMPLEMENTATION IMPLEMENTATION VHDL, Verilog Spice-like PROTOTYPE / INTEGRATION TEST & VERIFICATION Specification isolated from verification Disconnected teams 2

Focus on Algorithm Design Rapid design construction SPECIFICATION Easier analog modeling ANALOG & DIGITAL DESIGN Limited analog/digital links Slow design iterations IMPLEMENTATION IMPLEMENTATION VHDL, Verilog Spice-like PROTOTYPE / INTEGRATION TEST & VERIFICATION Specification isolated from verification Disconnected teams 3

Anticipate Impairments at System-Level Rapid design construction SPECIFICATION Easier analog modeling ANALOG & DIGITAL DESIGN Multi-domain simulation Rapid design iterations Fixed-Point Physical IMPLEMENTATION IMPLEMENTATION VHDL, Verilog Spice-like PROTOTYPE / INTEGRATION TEST & VERIFICATION Specification isolated from verification Disconnected teams 4

Perform Continuous Verification Rapid design construction SPECIFICATION Easier analog modeling ANALOG & DIGITAL DESIGN Multi-domain simulation IMPLEMENTATION IMPLEMENTATION TEST & VERIFICATION Integrated specification VHDL, Verilog Spice-like Rapid design iterations PROTOTYPE / INTEGRATION Improved team communication 5

Modeling and Verifying Mixed-Signal Designs with MATLAB and Simulink Rapid design construction SPECIFICATION Easier analog modeling ANALOG & DIGITAL DESIGN Multi-domain simulation IMPLEMENTATION IMPLEMENTATION TEST & VERIFICATION Integrated specification VHDL, Verilog Spice-like Rapid design iterations PROTOTYPE / INTEGRATION Improved team communication 6

Save >30% of Overall Development Time (and Improve Quality, Reduce Re-spins, etc.) With MathWorks Tools Time spent in project phases Without MathWorks Tools 0 50 100 150 200 250 Requirements System Design Implementation Integration Testing Days 7

Recent Successes Customer Use case Atmel IDT-Newave Realtek RFMD Fujitsu RF Front End for DVB Analog-digital co-design and verification Audio chipset Rapid simulation of PLLs Voice-band codec Analog-Digital design Video transceiver System-level/SPICE cosimulation 40 Gbit/s SERDES Rapid system simulation 8

An Integrated Environment for Model-Based Design of Mixed-Signal Systems Saves Time and Costly Errors Algorithmic design with many trusted functions You don t have to become a modeling guru Anticipating implementation impairments / constraints Find errors early and optimize your design Building and reusing system-verification test-benches The verification effort will be limited 9

Design and Verification of a Sigma-Delta ADC 10

Goal: Preliminary Design of a Simple ADC Sigma-delta ADC Which order? Will it be stable? Analog input signal around 8kHz Design of input anti-aliasing analog filter Design of output decimation filter Tradeoff cost and performances 11

Mixed-Signal Modeling with Simulink Analog and digital in same model Time handling Multiple solvers / schedulers SPECIFICATION DESIGN Algorithms Digital Analog Fixed-Point Physical IMPLEMENTATION VHDL, Verilog Spice-like TEST & VERIFICATION FPGA ASIC ASIC SMPS INTEGRATION 12

Sigma-Delta ADC with Circuit Elements Mixed-behavioral and circuit design Include circuit elements Complex filter design SPECIFICATION DESIGN Algorithms Digital Analog Fixed-Point Physical IMPLEMENTATION VHDL, Verilog Spice-like TEST & VERIFICATION FPGA ASIC ASIC SMPS INTEGRATION 13

Hardware Rapid Prototyping On-target automatic HDL code generation Verification via co-simulation with third party HDL simulators SPECIFICATION DESIGN Algorithms Digital Analog Fixed-Point Physical IMPLEMENTATION VHDL, Verilog Spice-like TEST & VERIFICATION FPGA ASIC ASIC SMPS INTEGRATION 14

Re-Use Testbench for Verification Model refinement, implementation and verification in a single environment 15

Design and Verification of a PLL 17

Phase-Locked Loop Feedback control system Generates a signal with a fixed relation to the phase of a reference signal Used for frequency synthesis, synchronization Measurements of interest Time: rise time, overshoot, lock time, jitter Frequency: phase noise, spurs Reference Phase Detector Loop Filter VCO 1/N 18

PLL Key Components Digital Flip-Flop Based Phase\Frequency Detector Analog Circuit Model Charge Pump Flip-flops Delay Memory Basic Logic Resistors Capacitors Current sources 19

Design a 2.4 GHz ISM Band PLL Specifications: 8 channels of 10 MHz BW Integer N divider, type 2, 3 rd order PLL architecture Phase noise < -103dBc @ 3.5 MHz offset Reference spurs < -60 dbc Lock time < 10 us Phase Margin > 60 degrees Loop filter (III order) design: Meet all specifications Minimize in-band phase noise 20

From Behavioral Model to Implementation Start your design in MATLAB Refine design details using behavioral circuit models Verify the specs with the refined model Link to circuit simulators to verify the behavioral models Verify the performances with the refined model Link to circuit simulators to verify the implementation 21

Design Exploration in MATLAB Stability analysis Step response Noise performance SPECIFICATION DESIGN Algorithms Digital Analog Fixed-Point Physical IMPLEMENTATION VHDL, Verilog Spice-like TEST & VERIFICATION FPGA ASIC ASIC SMPS INTEGRATION 22

Sequence of Model Elaborations Start with a basic Phase Domain linear PLL SPECIFICATION DESIGN Algorithms Digital Analog Fixed-Point Physical IMPLEMENTATION VHDL, Verilog Spice-like TEST & VERIFICATION FPGA ASIC ASIC SMPS INTEGRATION 23

Laplace Representation vs. Circuit Elements Progressively refine the model and validate it using the same testbench SPECIFICATION DESIGN Algorithms Digital Analog Fixed-Point Physical IMPLEMENTATION VHDL, Verilog Spice-like TEST & VERIFICATION FPGA ASIC ASIC SMPS INTEGRATION 24

Converting from Phase to Time Domain Build an accurate model for spurs and phase-noise simulation SPECIFICATION DESIGN Algorithms Digital Analog Fixed-Point Physical IMPLEMENTATION VHDL, Verilog Spice-like TEST & VERIFICATION FPGA ASIC ASIC SMPS INTEGRATION 25

Time Domain Model Starting point for detailed circuit design SPECIFICATION DESIGN Algorithms Digital Analog Fixed-Point Physical IMPLEMENTATION VHDL, Verilog Spice-like TEST & VERIFICATION FPGA ASIC ASIC SMPS INTEGRATION 26

Top-Down Design With MATLAB and Simulink Focus on Simulation and Model Refinement at the System Level SPECIFICATIONS Rapid design construction Easier analog modeling Fixed-point and bit-accurate simulation IMPLEMENTATION Multi-domain simulation Hardware / Software codesign Mixed-Signal IC Design Tools VHDL, Verilog Spice-like Fast simulation VERIFICATION / INTEGRATION / PROTOTYPE 27

Top-Down Design for ASICs Integration with Standard EDA flows SPECIFICATIONS Synthesizable HDL code generation Analog design gap IMPLEMENTATION Rapid design iterations Mixed-Signal IC Design Tools Slow simulation VHDL, Verilog Spice-like Early verification VERIFICATION / INTEGRATION / PROTOTYPE Late verification Fixed-Point Designer, HDL Coder, HDL Verifier What about Analog/Mixed-Signal? 28

Two Options for Integration with EDA tools Cosimulation Code generation Debugging Testbench generation Validation of behavioral models Regression testing 29

Option 1: Cosimulation 30

Verification of Circuit Design: Cosimulation Verify implementation against executable specifications SPECIFICATION DESIGN Algorithms Digital Analog Fixed-Point Physical IMPLEMENTATION VHDL, Verilog Spice-like TEST & VERIFICATION FPGA ASIC ASIC SMPS INTEGRATION 31

Verification of Circuit Design: Cosimulation Current Source Level Shifters Inverters Charge Loop Filter Discharge +/- 5 V supply + ground 24 nmos & pmos transistors 8 current sources for bias Input: 1V step functions from PFD Output: VCO control voltage 32

Cosimulation with Simulink Verify transistor level design: within the context of a full system simulation using visualization and analysis capabilities of Simulink and MATLAB testing each module independently of other modules 33

Cosimulation Verification Workflow Ideal behavioral model Cosimulation Refined model 34

Option 2: Code Generation 35

Mixed-Signal Design Gap How to Bridge Simulink and Mixed-Signal EDA Flows?? No standard API for analog simulators Different analog simulators provide different results Cosimulation can be slow Analog synthesis is still a research topic 36

Using C Code Generation and DPI-C Interface 1. Make your Simulink model C code generation compliant 2. Generate C code from your Simulink model 3. Automatically wrap the C code using SystemVerilog DPI-C interface 4. Import, build and simulate the equivalent behavioral SystemVerilog model in your IC design tool 2. SystemVerilog wrapper 1. C Code 3. IC Design Tool 37

Benefits of C Code Generation and DPI-C Export Fast simulation using the native SystemVerilog API IC design tool independent Customizable approach supported by MathWorks Leverages mature C code generation technology Most suitable for testbench generation and IC verification Support discrete and continuous time signals Simulink IC Design Tool 38

Some Details 39

Mixed-Signal PLL Model Charge Pump + Loop filter (analog) Binary Signal Source Phase / Frequency Detector (digital) Divider (triggered block) VCO (analog) 40

Export of Mixed-Signal Models Continuous time signals Discrete time solver 41

From Variable to Fixed Time Step Solver Chose a fixed sample time that it is small enough to give correct results Tradeoff accuracy and simulation time Large time step Small time step 42

Schedule the Execution of SystemVerilog Modules Simulink handles multi-rate systems automatically You need to define a scheduler to control the SystemVerilog execution Slow Clock 43

SystemVerilog Discretizes Time Discrete sample times in Simulink are integer multiple of an arbitrary fundamental sample time In SystemVerilog all sample times are integer multiple of 1fs (or a reference discrete sample time) 44

Certified by STARC http://www.mathworks.com/company/newsletters/articles/a-next-generation-workflow-for-system-level-design-of-mixed-signal-integrated-circuits.html 45

STARC: Semiconductor Technology Academic Research Center Members: Fujitsu Semiconductor, Renesas, ROHM, Sony, Toshiba Key Takeaways Reference Motif Circuit (Sigma-Delta Converter) Circuit Level Two Months Verilog-AMS Six Days STARCAD-AMS (MathWorks) Three Days Several semiconductor companies adopting STARC recommendation Japan member companies Non-member AMER/EMEA semiconductor majors http://www.mathworks.com/company/newsletters/articles/a-next-generation-workflow-for-system-level-design-of-mixed-signal-integrated-circuits.html 46

Two Options for Integration with EDA tools Cosimulation Code generation Debugging Testbench generation Validation of behavioral models Regression testing 47

Mixed-Signal Verification: Reuse System Level Testbenches in IC Design Tools Two complementary verification approaches using Simulink system-level testbenches You don t have to become a modeling guru Cosimulation Find errors early and optimize your design Code generation The verification effort will be limited 48

Next Steps 49

Explore Mixed-Signal Design with MATLAB and Simulink http://www.mathworks.com/mixed-signal-systems/ 50

Browse Videos, Webinars, Articles 51

Download and Try Mixed-Signal Library Direct Link: https://www.mathworks.com/programs/mixed-signal/index.html 52

Request Onsite Meeting and Discussion Discuss your project and workflow with MathWorks Applications Engineering Team Digital: HDL code generation, verification Connectivity to Mentor, Cadence, and Synopsys flows Analog: Verilog-A or SystemVerilog code generation C code with DPI-C wrappers Connectivity to Cadence and Synopsys flows IBIS-AMI component creation from MATLAB and Simulink 53