Introduction to Digital Logic Missouri S&T University CPE 2210 Multipliers/Dividers Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science and Technology cetinkayae@mst.edu http://web.mst.edu/~cetinkayae/teaching/cpe2210fall2016 11 November 2016 rev. 16.0 2014 2016 Egemen K. Çetinkaya
Introduction Multipliers Dividers ALUs Summary Multipliers/Dividers Outline 2
Digital Logic Systems Overview Combinatorial logic circuits for no memory systems Boolean algebra to mathematically design/analyze logic gates are building blocks Sequential logic circuits for memory systems Finite State Machines to mathematically design/analyze flip-flops and latches store memory flip-flops and latches are building blocks of sequential logic Sequential logic circuits (aka controllers) combine combinatorial circuits storage elements (e.g. registers) 3
Digital Systems Components analog phenomena electric signal A2D digital data digital data sensors and other inputs Digital System D2A electric signal actuators and other outputs digital data digital data Transducer: sensor + actuator Not all sensors/actuators require A2D/D2A conversion Digital system can be implemented: microprocessor readily available, cheap, easy to program, easy to reprogram custom circuit smaller, faster, consume less power 4
Digital Systems Paths Digital systems have two paths: datapath circuit control circuit Datapath circuit store data manipulate data transfer data from one part to another Control circuit controls the operation of datapath circuit 5
Datapath Components Building Block examples Registers Shifters Counters/timers Multiplexer/demultiplexers Decoders/encoders Adders Comparators Subtractors Multipliers/dividers ALUs: Arithmetic Logic Units 6
Adders Half-Adder Adds two bits, generates sum bit and carry-out bit Lets try to design the circuit: Next steps? Implement as a circuit co = ab, s = a b a b A: 1 1 1 1 + B: 0 1 1 b a ci c o s 0 1 1 b a ci c o s 1 0 1 b a ci c o s 0 0 b a c o s 1 SUM a b Half-adder (HA) co s co s 7
Adders Full-Adder Adds three bits, generates sum bit and carry-out bit Lets try to design the circuit: Next steps? Implement as a circuit co = ab + ac + bc s = a b c a b Full-adder (FA) co s ci a b Full adder (FA) c o ci s 8
Adders Carry-Ripple Adder Carry-ripple adder: Uses half- and full-adders E.g.: 4-bit carry-ripple adder can build any size adder based on full- and half-adders a3 b3 a2 b2 a1 b1 a0 b0 a b ci a b ci a b ci a b F A F A F A HA a3 a2 a1 a0 b3 b2 b1 b0 c o s c o s c o s c o s 4-bit adder c o s3 s2 s1 s0 c o s3 s2 s1 s0 9
Adders Carry-Ripple Adder Carry-ripple adder: Can also use only full-adders E.g.: 4-bit carry-ripple adder a3 b3 a2 b2 a1 b1 a0 b0 ci a b ci a b ci a b ci a b ci a3 a2 a1 a0 b3 b2 b1 b0 F A F A F A F A 4-bit adder ci c o s c o s c o s c o s c o s3 s2 s1 s0 c o s3 s2 s1 s0 10
Comparison Half-Adder vs. Half-Subtractor HA operation: a+b s = a b co = ab HS operation: b a D = a b B = b a a b a b a b a b Half-adder (HA) co s Halfsubtractor B D co s B D 11
Comparison Full-Adder vs. Full-Subtractor FA operation: a+b+c s = a b c co = ab + ac + bc FS operation: b a Bi D = b a Bi Bo = b (a Bi) + abi a b ci a b Bi Full adder (FA) (FS) c o s B o D 12
Subtractors Subtraction via 2 s Complements Subtraction via adding 2 s complement A B = A + ( B) A B = A + (2 s complement of B) A B = A + (inverted B + 1) A B N-bit A Adder B cin 1 S 13
Lets shift left one Shift Register Shift Left Operation Example Egemen K. Çetinkaya 0 1 1 0 1 1 0 1 14
Lets shift left one Shift Register Shift Left Operation Example Egemen K. Çetinkaya 0 1 1 0 1 1 0 1 After moving one bit to left? 15
Lets shift left one Shift Register Shift Left Operation Example Egemen K. Çetinkaya 0 1 1 0 1 1 0 1 After moving one bit to left 1 1 0 1 1 0 1 0 dropped the MSB added 0 for LSB 16
Lets shift left 2-bits Shift Register Shift Left Operation Example 0 1 1 0 1 1 0 1 Egemen K. Çetinkaya After first shift left After second shift left 17
Lets shift left 2-bits Shift Register Shift Left Operation Example 0 1 1 0 1 1 0 1 Egemen K. Çetinkaya After first shift left 1 1 0 1 1 0 1 0 After second shift left 18
Lets shift left 2-bits Shift Register Shift Left Operation Example 0 1 1 0 1 1 0 1 Egemen K. Çetinkaya After first shift left 1 1 0 1 1 0 1 0 After second shift left 1 0 1 1 0 1 0 0 19
Shift Register Shift Left Operation Example What was the arithmetic operation we just did? Egemen K. Çetinkaya 20
Shift Register Shift Left Operation Example Shift left n-bits will multiply by 2 n Egemen K. Çetinkaya 21
Shift Register Shift Right Operation Example Lets shift right one Egemen K. Çetinkaya 0 1 1 0 1 1 0 1 22
Shift Register Shift Right Operation Example Lets shift right one Egemen K. Çetinkaya 0 1 1 0 1 1 0 1 After moving one bit to right? 23
Shift Register Shift Right Operation Example Lets shift right one Egemen K. Çetinkaya 0 1 1 0 1 1 0 1 After moving one bit to right 0 0 1 1 0 1 1 0 Added 0 for MSB dropped the LSB 24
Shift Register Shift Right Operation Example Lets shift right 2-bits 0 1 1 0 1 1 0 1 Egemen K. Çetinkaya After first shift right After second shift right 25
Shift Register Shift Right Operation Example Lets shift right 2-bits 0 1 1 0 1 1 0 1 Egemen K. Çetinkaya After first shift right 0 0 1 1 0 1 1 0 After second shift right 26
Shift Register Shift Right Operation Example Lets shift right 2-bits 0 1 1 0 1 1 0 1 Egemen K. Çetinkaya After first shift right 0 0 1 1 0 1 1 0 After second shift right 0 0 0 1 1 0 1 1 27
Shift Register Shift Right Operation Example What was the arithmetic operation we just did? Egemen K. Çetinkaya 28
Shift Register Shift Right Operation Example Shift right n-bits will divide by 2 n Egemen K. Çetinkaya 29
Division via Shift Signed Number Example Previous examples were unsigned numbers Need to preserve the sign for signed numbers Consider A = 24 = 011000 A/2 = 24/2 = 12 = 001100 A/4 = 24/4 = 6 = 000110 Consider A = 24 = 101000 A/2 = 24/2 = 12 = 110100 A/4 = 24/4 = 6 = 111010 30
Multipliers Multiplication Operation Multiplication product via multiplicand and multiplier Multiplicand M Multiplier Q (14) (11) 1 1 1 0 1 0 1 1 Product P (154) 1 1 1 0 1 1 1 0 0 0 0 0 1 1 1 0 1 0 0 1 1 0 1 0 31
Multipliers Multiplication Operation Multiplication results in partial products Multiplicand M Multiplier Q (14) (11) 1 1 1 0 1 0 1 1 Partial product 1 + 1 1 1 0 1 1 1 0 Partial product 2 + 1 0 1 0 1 0 0 0 0 Partial product 3 + 0 1 0 1 0 1 1 1 0 Product P (154) 1 0 0 1 1 0 1 0 32
Multiplier Circuit Array Style Multiplier Multiplication by hand can be mimicked 33
Multiplier Circuit Array Style Multiplier Generalized representation of multiplication by hand 34
pp4 pp3 pp2 pp1 Egemen K. Çetinkaya Multiplier Circuit Array Style Multiplier a3 a2 a1 a0 b0 b1 0 0 b2 + (5-bit) 0 0 b3 0 0 0 + (6-bit) A P B + (7-bit) p7..p0 Block symbol 35
Dividers Division Operation Dividend divided by divisor resulting in Q and R 00001111 15 Divisor 1001 10001100 9 140 1001 9 10001 50 1001 45 10000 5 1001 1110 1001 101 Quotient Dividend Remainder 36
A/B produces Q and R Divider Circuit Array Style Divider The most significant bit of the dividend A then becomes the least significant bit of R. The divisor B is repeatedly subtracted from this partial remainder to determine whether it fits. More info [HH2013] [EL2004] 37
ALUs Arithmetic Logic Units Arithmetic Logic Unit (ALU) ALUs performs Boolean and arithmetic functions Performs operations on n-bit operands e.g. 4-bit addition, subtraction e.g. 8-bit addition, subtraction Functions include on TI 74S381 ALU chip: Clear, A B, A+B, XOR, OR, AND, Preset 38
Multipliers/Dividers Summary Many multipliers design exists Division is a slow and expensive operation Need to preserve the sign for signed numbers when doing multiplication/division via shifting ALUs performs Boolean and arithmetic functions 39
References and Further Reading [V2011] Frank Vahid, Digital Design with RTL Design, VHDL, and Verilog, 2nd edition, Wiley, 2011. [BV2009] Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 3rd edition, McGraw-Hill, 2009. [G2003] Donald D. Givone, Digital Principles and Design, McGraw-Hill, 2003. [HH2013] David Harris and Sarah Harris, Digital Design and Computer Architecture, 2nd edition, Morgan Kaufmann, 2013. [EL2004] Miloš D. Ercegovac and Tomás Lang, Digital Arithmetic, 1st edition, Morgan Kaufmann, 2004. 40
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