ENGIN 241 Digital Systems with Lab (4) Dr. Honggang Zhang Engineering Department University of Massachusetts Boston 1
Introduction Hardware description language (HDL): Specifies logic function only Computer-aided design (CAD) tool produces or synthesizes optimized gates Most commercial designs built using HDLs, and two leading HDLs: VHDL 2008 Very High Speed Integrated circuit Hardware Description Language. Widely used to translate designs into bit patterns that program actual devices. Developed in 1981 by the Department of Defense IEEE standard (1076) in 1987 Updated in 2008 (IEEE STD 1076-2008) SystemVerilog Developed in 1984 by Gateway Design Automation IEEE standard (1364) in 1995 Extended in 2005 (IEEE STD 1800-2009) 2
HDL to Gates Simulation Inputs applied to circuit Outputs checked for correctness Millions of dollars saved by debugging in simulation instead of hardware Synthesis Transforms HDL code into a netlist describing the hardware (i.e., a list of gates and the wires connecting them) IMPORTANT: When using an HDL, think of the hardware that the HDL should produce 3
Example: timing simulation of a circuit described in HDL. 4
VHDL Modules Two types of Modules: Behavioral: describe what a module does. Structural: describe how it is built from simpler modules. 5
It is important to distinguish between hardware description languages & programming languages With both, a language is used to program a device. Computers operate by following a list of tasks, each of which must be done in sequential order. Speed of operation is determined by how fast the computer can execute each instruction. A digital logic circuit is limited in speed only by how quickly the circuitry can change its outputs in response to changes in the inputs. It is monitoring all inputs concurrently & responding to any changes. 6
Comparing operation of a computer and a logic circuit in performing the logical operation of y = AB. A y B The logic circuit is an AND gate. The output y will be HIGH within about 10 nanoseconds of the point when A and B are HIGH simultaneously. Within approximately 10 nanoseconds after either input goes LOW, the output y will be LOW. 7
Comparing operation of a computer and a logic circuit in performing the logical operation of y = AB. The computer must run a program of instructions that makes decisions. Each shape in the flowchart represents one instruction. If each takes 20 ns, it will take a minimum of two or three instructions (40 60 ns) to respond to changes in the inputs. 8
Implementing Logic Circuits With PLDs Programmable Logic Devices (PLDs) are devices that can be configured in many ways to perform logic functions. Internal connections are made electronically to program devices. 9
Implementing Logic Circuits With PLDs PLDs are configured electronically & their internal circuits are wired together electronically to form a logic circuit. This programmable wiring can be thought of as thousands of connections, either connected (1), or not connected (0). Each intersection of a row (horizontal wire) & column (vertical wire) is a programmable connection. 10
PLDs use a switch matrix that is often referred to as a programmable array. By deciding which intersections are connected & which are not, we can program the way the inputs are connected to the outputs of the array. 11
A program written in a hardware description language (e.g., VHDL) defines the connections to be made. The program is loaded into the device after translation by a compiler. 12
Programmable Logic Devices The reason for using programmable logic devices Lots of logic gates in a single IC. Control of the interconnection of these gates electronically. PLDs allow the design process to be automated. Designers identify inputs, outputs, and logical relationships. PLDs are electronically configured to form the defined logic circuits. 13
For out-of-system programming the PLD is placed in a programmer, connected to a PC. PC software translates and loads the information. In-system programming is done by connecting directly to portal pins while the IC remains in the system. An interface cable connects the PLD to a PC running the software that loads the device. 14
Logic circuits can be described using schematic diagrams, logic equations, truth tables, and HDL. PLD development software can convert any of these descriptions into 1s and 0s and loaded into the PLD. We will use Active-HDL software 15
A system is built from logic blocks. Each block is described by a design file. After testing it is compiled using development software. The compiled block is tested using a simulator for verify correct operation. A PLD is programmed to verify correct operation. 16
VHDL Format and Syntax 17
Format refers to a definition of inputs, outputs & how the output responds to the input (operation). Languages that are interpreted by computers must follows strict rules of syntax, which refers to the order of elements. Format of HDL files. 18
On the left side of the diagram is the set of inputs, and on the right is the set of outputs. The symbols in the middle define its operation. 19
A circuit described in HDL must be given a name. Start with input/output (I/O) definition, then, the definition of an operation is contained in a set of statements. Inputs & outputs (ports) must be assigned names and defined according to the nature of the port. The mode defines whether it is input or output. The type refers to the number of bits and how those bits are grouped and interpreted. A single bit input, can have only two values: 0 and 1. A four-bit binary number can have any one of 16 different values (0000 2-1111 2 ). 20
The keyword ENTITY gives a name to the circuit block, which in this case is and_gate. The keyword PORT tells the compiler that we are defining inputs and outputs to this circuit block. The BIT description tells the compiler that each variable in the list is a single bit. The ARCHITECTURE declaration is used to describe the operation of everything inside the block, which is between BEGIN and VHDL is not case-sensitive. Here we use lowercase for variable names. END. 21
In many designs, there is a need to define signal points inside the circuit block called buried nodes or local signals. Points in the circuit that may be useful as a reference point, that are not inputs or outputs. 22
VHDL local signals: Keyword SIGNAL defines intermediate signal. Keyword BIT designates the type of signal 23
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Representing Data in VHDL 25
Representing Data in HDL Every programming language & HDL has its own unique way of identifying number systems. Generally done with a prefix to indicate the system. When we read one of these number designations, we must think of it as a symbol that represents a binary bit pattern. These numeric values are referred to as scalars or literals. Binary Hexadecimal Decimal 26
In order to describe a port with more than one data bit we assign a name and the number of bits. This is called a bit array or bit vector. Each element (bit) has a unique index number (0 7) to describe position in the overall structure. HDLs & computer programming languages use this notation. 27
VHDL syntax a name for the bit vector is followed by the mode, the type, and the range. Enclosed in parenthesis, in the ENTITY section. To declare an eight-bit input port called p1 PORT (p1 :IN BIT_VECTOR (7 DOWNTO 0); 28
Intermediate variables can be declared as an array of bits in the ARCHITECTURE section Eight-bit temperature port p1 assigned to a signal named temp SIGNAL temp :BIT_VECTOR {7 DOWNTO 0}; BEGIN temp <= p1; END; 29
Representing numbers Numbers can be specified in binary, octal, decimal, or hexadecimal. The size, i.e., the number of bits, may optionally be given. Underscores in a number are ignored and can be helpful in breaking long numbers into more readable chunks. 30
STD_LOGIC numbers are written in binary and enclosed in single quotes: '0' and '1' indicate logic 0 and 1. The format for STD_LOGIC_VECTOR constants is NB"value", where N is the size in bits, B is a letter indicating the base. B for binary, O for octal, D for decimal, and X for hexadecimal. For example, 9X"25" indicates a 9-bit number with a value of 25 16 =37 10 =000100101 2. If the base is omitted, it defaults to binary. If the size is not given, the number is assumed to have a size matching the number of bits specified in the value. 31
Examples Underscores in a number are ignored and can be helpful in breaking long numbers into more readable chunks. 32
Bit swizzling Operate on a subset of a bus or to concatenate (join together) signals to form a bus. () aggregate operator Example, y is given the 9-bit value c(2)c(1)d(0)d(0)d(0)c(0)101 using bit swizzling operations. y <=(c(2 downto 1), d(0), d(0), d(0), c(0), 3B"101"); z=10010110, assuming z is a 8-bit STD_LOGIC_VECTOR. z <= ("10", 4 => '1', 2 downto 1 =>'1', others =>'0'); others => '0' and others => '1' fill all of the rest of the bits with 0 and 1, respectively. 33
z indicates a floating value, e.g., z is particularly useful for describing a tristate buffer, whose output floats when the enable is 0. e.g. all the tristate buffers driving a bus are OFF, the bus will float, indicated by z. VHDLs use x to indicate an invalid logic level. If a bus is simultaneously driven to 0 and 1 by two enabled tristate buffers (or other gates), the result is x, indicating contention. u indicates an unknown state e.g., a flip-flop s output initialized to u 34
In VHDL, STD_LOGIC signals are '0', '1', 'z', 'x', and 'u'. If a gate receives a floating input, it may produce an x output when it can t determine the correct output value. If a gate receives an illegal or uninitialized input, it may produce an x output. 35
If we see x or u values in simulation, this is almost always an indication of a bug or bad coding practice. In the synthesized circuit, this corresponds to a floating gate input, uninitialized state, or contention. The x or u may be interpreted randomly by the circuit as 0 or 1, leading to unpredictable behavior. 36
AND truth table More information: https://standards.ieee.org/downloads/1076/1076.2-1996/std_logic_1164-body.vhdl 37
Learn idioms, specific ways to describe various classes of logic. Combinational Logic 38
library IEEE; use IEEE.STD_LOGIC_1164.all; entity gates is port(a, b: in STD_LOGIC_VECTOR(3 downto 0); y1, y2, y3, y4, y5: out STD_LOGIC_VECTOR(3 downto 0)); end; architecture synth of gates is begin -- five different two-input logic gates -- acting on 4-bit busses y1 <= a and b; y2 <= a or b; y3 <= a xor b; y4 <= a nand b; y5 <= a nor b; end; Bitwise operators not, xor, and, or are VHDL operators. a, b, and y1 are operands. An expression is a combination of operators and operands. A complete command such as y4 <= a nand b; is called a statement, ended with a semicolon. This is called concurrent signal assignment. Anytime the inputs change, the output recomputed, thus, combinational logic. 39
synthesized circuit library IEEE; use IEEE.STD_LOGIC_1164.all; entity gates is port(a, b: in STD_LOGIC_VECTOR(3 downto 0); y1, y2, y3, y4, y5: out STD_LOGIC_VECTOR(3 downto 0)); end; architecture synth of gates is begin -- five different two-input logic gates -- acting on 4-bit busses y1 <= a and b; y2 <= a or b; y3 <= a xor b; y4 <= a nand b; y5 <= a nor b; end; 40
entity and8 is port(a: in STD_LOGIC_VECTOR(7 downto 0); y: out STD_LOGIC); end; architecture synth of and8 is begin y <= and a; -- and a is much easier to write than -- y <= a(7) and a(6) and a(5) and a(4) and -- a(3) and a(2) and a(1) and a(0); end; and in this code is a reduction operator which imply a multiple-input gate acting on a single bus. 41
library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux2 is port(d0, d1: in STD_LOGIC_VECTOR(3 downto 0); s: in STD_LOGIC; y: out STD_LOGIC_VECTOR(3 downto 0)); end; architecture synth of mux2 is begin y <= d1 when s else d0; end; Conditional signal assignments perform different operations depending on some condition. They are especially useful for describing a multiplexer. The conditional signal assignment sets y to d1 if s is 1. Otherwise it sets y to d0. Prior to the 2008 revision of VHDL, one had to write when s= '1' rather than when s. 42
A 4:1 multiplexer can select one of four inputs using multiple else clauses in the conditional signal assignment. library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux4 is port(d0, d1, d2, d3: in STD_LOGIC_VECTOR(3 downto 0); s: in STD_LOGIC_VECTOR(1 downto 0); y: out STD_LOGIC_VECTOR(3 downto 0)); end; architecture synth1 of mux4 is begin y <= d0 when s = "00" else d1 when s = "01" else d2 when s = "10" else d3; end; 43
Selected signal assignment statements to provide a shorthand when selecting from one of several possibilities. This is analogous to using a switch/case statement in place of multiple if/else statements in some programming languages. The 4:1 multiplexer can be rewritten with selected signal assignment as follows: architecture synth2 of mux4 is begin with s select y <= d0 when "00", d1 when "01", d2 when "10", d3 when others; end; 44
VHDL operator precedence Unlike Boolean algebra, logical operations have equal precedence, thus parentheses are often necessary. 45
Truth Tables Using HDL - VHDL Circuits can be designed directly from truth tables, using VHDL. library IEEE; use IEEE.STD_LOGIC_1164.all; entity ex3 is port(a, b, c: in bit; y: out bit); end; architecture truth of ex3 is signal in_bits: bit_vector (2 downto 0); begin in_bits <= a & b & c; -- concatenate input bits into bit_vector with in_bits select y<= '0' when "000", '0' when "001", '0' when "010", '1' when "011", '0' when "100", '1' when "101", '1' when "110", '1' when "111"; end; 46
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More examples on internal variables library IEEE; use IEEE.STD_LOGIC_1164.all; entity fulladder is port(a, b, cin: in STD_LOGIC; s, cout: out STD_LOGIC); end; architecture synth of fulladder is signal p, g: STD_LOGIC; begin p <= a xor b; g <= a and b; s <= p xor cin; cout <= g or (p and cin); end; Define intermediate signals, P and G Then we get, 49
A tristate buffer example library IEEE; use IEEE.STD_LOGIC_1164.all; entity tristate is port(a: in STD_LOGIC_VECTOR(3 downto 0); en: in STD_LOGIC; y: out STD_LOGIC_VECTOR(3 downto 0)); end; architecture synth of tristate is begin y <= a when en else "ZZZZ"; end; 50
Delays HDL statements may be associated with delays specified in arbitrary units. helps a simulation to predict how fast a circuit will work for debugging to understand cause and effect These delays are ignored during synthesis the delay of a gate produced by the synthesizer depends on its t pd and t cd specifications, not on numbers in HDL code. 51
Structural modeling Describe a module in terms of how it is composed of simpler modules. Example: Assemble a 4:1 multiplexer from three 2:1 multiplexers. Each copy of the 2:1 multiplexer is an instance. Multiple instances of the same module are distinguished by distinct names, lowmux, highmux, and finalmux. 52
Assemble a 4:1 multiplexer from three 2:1 multiplexers. 53
library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux4 is port(d0, d1, d2, d3: in STD_LOGIC_VECTOR(3 downto 0); s: in STD_LOGIC_VECTOR(1 downto 0); y: out STD_LOGIC_VECTOR(3 downto 0) ); end; architecture struct of mux4 is component mux2 port(d0,d1: in STD_LOGIC_VECTOR(3 downto 0); s: in STD_LOGIC; y: out STD_LOGIC_VECTOR(3 downto 0)); end component; signal low, high: STD_LOGIC_VECTOR(3 downto 0); begin lowmux: mux2 port map(d0, d1, s(0), low); highmux: mux2 port map(d2, d3, s(0), high); finalmux: mux2 port map(low, high, s(1), y); end; 54
Construct a 2:1 multiplexer from a pair tristate buffers 55
library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux2 is port(d0, d1: in STD_LOGIC_VECTOR(3 downto 0); s: in STD_LOGIC; y: out STD_LOGIC_VECTOR(3 downto 0)); end; architecture struct of mux2 is component tristate port(a: in STD_LOGIC_VECTOR(3 downto 0); en: in STD_LOGIC; y: out STD_LOGIC_VECTOR(3 downto 0)); end component; signal sbar: STD_LOGIC; begin sbar <= not s; t0: tristate port map(d0, sbar, y); t1: tristate port map(d1, s, y); end; Construct a 2:1 multiplexer from a pair tristate buffers. 56
An 8-bit wide 2:1 multiplexer is built using two of the 4-bit 2:1 multiplexers already defined, operating on the low and high nibbles of the byte. 57
library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux2_8 is port(d0, d1: in STD_LOGIC_VECTOR(7 downto 0); s: in STD_LOGIC; y: out STD_LOGIC_VECTOR(7 downto 0)); end; architecture struct of mux2_8 is component mux2 port(d0, d1: in STD_LOGIC_VECTOR(3 downto 0); s: in STD_LOGIC; y: out STD_LOGIC_VECTOR(3 downto 0)); end component; begin lsbmux: mux2 port map(d0(3 downto 0), d1(3 downto 0), s, y(3 downto 0)); msbmux: mux2 port map(d0(7 downto 4), d1(7 downto 4), s, y(7 downto 4)); end; An 8-bit wide 2:1 multiplexer is built using two of the 4-bit 2:1 multiplexers already defined, operating on the low and high nibbles of the byte. 58
Active-HDL We will use Active-HDL software to demonstrate the example programs listed here. set VHDL 1076-2008 as the default specification for the VHDL compiler. 59
Demo burning GAL 22v10 isplever Universal programmer 60