Chapter 2 Data Manipulation Computer Science An Overview Tenth Edition by J. Glenn Brookshear Presentation files modified by Farn Wang
Chapter 2 Data Manipulation 2.1 Computer Architecture 2.2 Machine Language 2.3 Program Execution 2.4 Arithmetic/Logic Instructions 2.5 Communicating with Other Devices 2.6 Other Architectures 2-2
Von Neumann s computer model John von Neumann 1903-1957
Computer Architecture Central Processing Unit (CPU) or processor Arithmetic/Logic unit Control unit Registers General purpose - data Special purpose instructions, addresses Bus Memory Motherboard 2-4
CPU and main memory connected via a bus 2-5
Stored Program Concept A program can be encoded as bit patterns and stored in main memory. From the main memory, the CPU can then extract the instructions and execute them. In turn, the program to be executed can be altered easily. 2-6
Terminology Machine instruction An instruction (or command) encoded as a bit pattern recognizable by the CPU Machine language The set of all machine instructions recognized by a machine also called instruction set 2-7
Machine Language Philosophies Reduced Instruction Set Computing (RISC) Few, simple, efficient, and fast instructions Examples PowerPC from Apple/IBM/Motorola and SPARK from Sun Microsystems Complex Instruction Set Computing (CISC) Many, convenient, and powerful instructions Example Pentium from Intel 2-8
Machine Instruction Types Data Transfer copy data from one location to another I/O instructions as a special case Arithmetic/Logic use existing bit patterns to compute a new bit patterns Control direct the execution of the program conditional? indirect? 2-9
Arithmetic/Logic Operations Logic AND, OR, XOR Masking Rotate and Shift circular shift, logical shift, arithmetic shift Arithmetic add, subtract, multiply, divide Precise action depends on how the values are encoded (two s complement versus floatingpoint). 2-10
Logic operations - Bit-wise Boolean operations 10011010 AND 11001001 10001000 10011010 OR 11001001 11011011 10011010 XOR 11001001 01010011 2-11
Rotating the bit pattern 65 (hexadecimal) one bit to the right 2-12
2015/03/17 stopped here 2-13
Adding values stored in memory 2-14
Dividing values stored in memory 2-15
The architecture of the machine described in Appendix C - an 8-bit CPU 8-bit bus and 8-bit data registers 2-16
Parts of a Machine Instruction Op-code Specifies which operation to execute Operand Gives more detailed information about the operation Interpretation of operand varies depending on op-code 2-17
A Simple Machine Language (I/II) 12 machine instructions Op-code Operand Description 1 RXY LOAD reg. R from cell XY. 2 RXY LOAD reg. R with XY. 3 RXY STORE reg. R at XY. 4 0RS MOVE R to S. 5 RST ADD S and T into R. (2 s comp.) 6 RST ADD S and T into R. (floating pt.) A-18
A Simple Machine Language (II/II) 12 machine instructions Op-code Operand Description 7 RST OR S and T into R. 8 RST AND S and T into R. 9 RST XOR S and T into R. A R0X ROTATE reg. R X times. B RXY JUMP to XY if R = reg. 0. C 000 HALT. A-19
The composition of an instruction for the machine 2-20
Decoding the instruction 35A7 2-21
Microprograms in the 8-bit CPU A tiny processor executing a microprogram to interpret instructions 2-22
Microprogramming hardware layers ( Maurice Wilkes (1951-2010) in ROM or PLA sometimes in flash memory IBM ers call it firmware. no more ad-hoc circuitry High-level programs Compilers CPU machine code CPU control unit microcode nanocode circuits 2-23
An encoded version of the instructions THE ADD program ( ) 2-24
Program Execution ( Controlled by two special-purpose registers Program counter address of next instruction Instruction register current instruction Machine Cycle Fetch Decode Execute 2-25
The machine cycle ( 2-26
Multiplexer & demultiplexer( 2-27
Decoding the instruction B258 2-28
Figure 2.10 The program from Figure 2.7 stored in main memory ready for execution 2-29
Performing the fetch step of the machine cycle 2-30
Performing the fetch step of the machine cycle (cont d) 2-31
Machine cycles - running examples PC IR ALU do x = x-1; while (x!=0) ; 11 A0 R0 R1 R2 RF bus 20 A0 mvc R0, 0 00 A1 A2 mov R1, AE A3 A4 mvc R2, -1 A5 A6 add R1, R1, R2 A7 A8 br R1, AC A9 AE 22 FF 51 12 B1 AC B0 A6 C0 00 03 AA br R0, A6 AB AC halt AD AE 2-
Machine cycles running examples - A0fetch1 PC IR ALU do x = x-1; while (x!=0) ; A0 R0 R1 R2 RF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A0fetch2 PC IR ALU A1 20 do x = x-1; while (x!=0) ; R0 R1 R2 RF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A0fetch3 PC IR ALU do x = x-1; while (x!=0) ; A1 20 R0 R1 R2 RF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A0fetch4 PC IR ALU do x = x-1; while (x!=0) ; A2 2000 R0 R1 R2 RF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A0decode PC IR ALU do x = x-1; while (x!=0) ; A2 2000 R0 R1 R2 RF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A0execute PC IR ALU do x = x-1; while (x!=0) ; A2 2000 R0 R1 R2 RF 00 bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A2fetch1 PC IR ALU do x = x-1; while (x!=0) ; A2 2000 R0 R1 R2 RF 00 bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A2fetch2 PC IR ALU A3 1100 do x = x-1; while (x!=0) ; R0 R1 R2 RF 00 bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A2fetch3 PC IR ALU do x = x-1; while (x!=0) ; A3 1100 R0 R1 R2 RF 00 bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A2fetch4 PC IR ALU A4 do x = x-1; while (x!=0) ; 11AE R0 R1 R2 RF 00 bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A2decode PC IR ALU A4 do x = x-1; while (x!=0) ; 11AE R0 R1 R2 RF 00 bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A2execute ALU PC A4 IR do x = x-1; while (x!=0) ; 11AE R0 R1 R2 RF 00 bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A2execute ALU PC A4 IR do x = x-1; while (x!=0) ; 11AE R0 R1 R2 RF 00 03 bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A4fetch1 PC IR ALU A4 do x = x-1; while (x!=0) ; 11AE R0 R1 R2 RF 00 03 bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A4fetch2 PC IR ALU A5 do x = x-1; while (x!=0) ; 22AE R0 R1 R2 RF 00 03 bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A4fetch3 PC IR ALU A5 do x = x-1; while (x!=0) ; 22AE R0 R1 R2 RF 00 03 bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A4fetch4 PC IR ALU A6 do x = x-1; while (x!=0) ; 22FF R0 R1 R2 RF 00 03 bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A4decode PC IR ALU A6 do x = x-1; while (x!=0) ; 22FF R0 R1 R2 RF 00 03 bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A4execute PC IR ALU A6 do x = x-1; while (x!=0) ; 22FF R0 R1 R2 RF 00 03 FF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A6fetch1 PC IR ALU A6 do x = x-1; while (x!=0) ; 22FF R0 R1 R2 RF 00 03 FF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A6fetch2 PC IR ALU A7 do x = x-1; while (x!=0) ; 51FF R0 R1 R2 RF 00 03 FF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A6fetch3 PC IR ALU A7 do x = x-1; while (x!=0) ; 51FF R0 R1 R2 RF 00 03 FF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A6fetch4 PC IR ALU A8 5112 do x = x-1; while (x!=0) ; R0 R1 R2 RF 00 03 FF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A6decode PC IR ALU A8 5112 do x = x-1; while (x!=0) ; R0 R1 R2 RF 00 03 FF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A6execute PC IR ALU A8 5112 do x = x-1; while (x!=0) ; R0 R1 R2 RF 00 02 FF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A8fetch1 PC IR ALU A8 5112 do x = x-1; while (x!=0) ; R0 R1 R2 RF 00 02 FF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A8fetch2 PC IR ALU A9 do x = x-1; while (x!=0) ; B112 R0 R1 R2 RF 00 02 FF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A8fetch3 PC IR ALU A9 do x = x-1; while (x!=0) ; B112 R0 R1 R2 RF 00 02 FF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A8fetch4 PC IR ALU AA do x = x-1; while (x!=0) ; B1AC R0 R1 R2 RF 00 02 FF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A8decode PC IR ALU AA do x = x-1; while (x!=0) ; B1AC R0 R1 R2 RF 00 02 FF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - A8execute PC IR ALU AA do x = x-1; while (x!=0) ; B1AC R0 R1 R2 RF 00 02 FF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - AAfetch1 PC IR ALU AA do x = x-1; while (x!=0) ; B1AC R0 R1 R2 RF 00 02 FF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - AAfetch2 PC IR ALU AB do x = x-1; while (x!=0) ; B0AC R0 R1 R2 RF 00 02 FF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - AAfetch3 PC IR ALU AB do x = x-1; while (x!=0) ; B0AC R0 R1 R2 RF 00 02 FF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - AAfetch4 PC IR ALU AC do x = x-1; while (x!=0) ; B0A6 R0 R1 R2 RF 00 02 FF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - AAdecode PC IR ALU AC do x = x-1; while (x!=0) ; B0A6 R0 R1 R2 RF 00 02 FF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Machine cycles running examples - AAexecute PC IR ALU A6 do x = x-1; while (x!=0) ; B0A6 R0 R1 R2 RF 00 02 FF bus 20 A0 mvc R0, 0 00 A1 11 A2 mov R1, AE AE A3 22 A4 mvc R2, -1 FF A5 51 A6 add R1, R1, R2 12 A7 B1 A8 br R1, AC AC A9 B0 AA br R0, A6 A6 AB C0 AC halt 00 AD 03 AE 2-
Communicating with Other Devices Controller An intermediary apparatus that handles communication between the computer and a device Specialized controllers for each type of device General purpose controllers USB and FireWire for PC Port The point at which a device connects to a computer Memory-mapped I/O CPU communicates with peripheral devices as though they were memory cells 2-70
Controllers attached to a machine s bus 2-71
A conceptual representation of memorymapped I/O 2-72
Computer-System Operation I/O devices and the CPU can execute concurrently. Each device controller is in charge of a particular device type. Each device controller has a local buffer.
Computer-System Operation CPU moves data from/to main memory to/from local buffers I/O is from the device to local buffer of controller. Device controller informs CPU that it has finished its operation by causing an interrupt.
Interaction of CPU with I/O devices I/O can be from devices, environment, networks Two ways to check if an I/O event happens Polling Periodically check if the signal (bit patterns in a memory cell or register) for an event has raised. Interrupt 2-75
Interaction of CPU with I/O devices Two ways to check if an I/O event happens Polling Interrupt Through a few interrupt signal lines to CPU can be disabled by a mask register to disable some interrupt signal lines. At the decoding cycle of each machine instruction execution, check if some unmasked interrupt lines are 1 s. If some are, branch to an address (interrupt vector) already stored for the corresponding interrupt lines. 2-76
Interrupt checking in machine cycles 1 CPU 0 mask register 1 Memory 2-77
Interrupts Interrupt transfers control to the interrupt service routine generally, through the interrupt vector, which contains the addresses of all the service routines. Interrupt architecture must save the address of the interrupted instruction. Incoming interrupts are disabled while another interrupt is being processed to prevent a lost interrupt.
Interrupt Handling The operating system preserves the state of the CPU by storing registers and the program counter. Determines which type of interrupt has occurred polling vectored interrupt system Separate segments of code determine what action should be taken for each type of interrupt
Interrupt Timeline
I/O Structure Synchronous After I/O starts, control returns to user program only upon I/O completion. Wait instruction idles the CPU until the next interrupt Wait loop (contention for memory access). At most one I/O request is outstanding at a time, no simultaneous I/O processing. Asynchronous
I/O Structure Synchronous Asynchronous After I/O starts, control returns to user program without waiting for I/O completion. System call request to the operating system to allow user to wait for I/O completion. Device-status table contains entry for each I/O device indicating its type, address, and state. Operating system indexes into I/O device table to determine device status and to modify table entry to include interrupt.
Communicating with Other Devices (continued) Direct memory access (DMA) Main memory access by a controller over the bus Von Neumann Bottleneck Insufficient bus speed impedes performance Handshaking The process of coordinating the transfer of data between components 2-83
Communicating with Other Devices (continued) Parallel Communication Several communication paths transfer bits simultaneously. Serial Communication 2-84
Communicating with Other Devices (continued) Parallel Communication Serial Communication Bits are transferred one after the other over a single communication path. 2-85
Data Communication Rates Measurement units Bps Bits per second Kbps Kilo-bps (1,000 bps) Mbps Mega-bps (1,000,000 bps) Gbps Giga-bps (1,000,000,000 bps) Bandwidth Maximum available rate Multiplexing + data-compression for performance 2-86
Other Architectures Technologies to increase throughput Pipelining Overlap steps of the machine cycle Parallel Processing Use multiple processors simultaneously SISD No parallel processing MIMD Different programs, different data Multi-core CPU multiple CPU in the same chip SIMD Same program, different data 2-87
Parallel computing bit-level 8-bit CPU 16-bit CPU 32-bit CPU instruction level pipelining (superscalar) 2-88
Parallel computing - memory and communications Non-Uniform Memory Access (NUMA) architecture Access time to different addresses is different. 2-89
Parallel computing - Classes Multi-core Symmetric multiprocessing Distributed computing Cluster computing 2-90
Parallel computing - Classes Massive parallel processing Cray 1 ILLIAC 4 2-91
Parallel computing - Classes Grid computing distributed computing loose-coupled hetreogeneous geographically dispersed non-interactive workload through middleware Cloud computing? 3 rd party services of infrastructure, platform, software from the internet 2-92
Parallel computing - hyper-threading Two logical processor sharing one core. Intel Pentium 4 2-93