INDEX OF VERILOG MODULES add and subtract behavioral, 221 structural, 221 adder, Floating-point, 250 adders behavioral, 215 carry look-ahead, 258 CLA, modules for radix-4, 261 CLA, radix-4, 260 full adder, 213 ripple-carry, 215 six-input, 270 arbiter assign implementation, 167 casex implementation, 168 combination lock control, 354 datapath, 353 complex, fixed-point multiplier, 277 counter incrementing datapath, 332 state table, 332 by 3, 337 UDL multiplexer implementation, 335 shared adder, 334 two adder, 334 D flip-flop, 305 decoder, 152 4 to 16, 155 divide-by-3 FSM, 416 divider, 229 encoder assign implementation, 162 case implementation, 163 16:4, 164 thermometer, 165 equality comparator, 171 three-way, 172 FIFO synchronizer, 585 FIR filter, 284 Gray-code counter 3-bit, 586 4-bit, 580 Huffman decoder, 428 Huffman encoder, 425 interconnect bus, 506 crossbar, 2 2, 509 light flasher 1 factor master, 364 timer, 365 2 factor counter, 369 master, 368 magnitude comparator behavioral, 172 iterative, 172 majority function, 50 test script, 50 microcode FSM branch and store, 399 ROM and sequencer, 391 ROM only, 384 multiple-of-3 bit cell, 188 testbench, 190 top level, 189 multiplexer assign implementation, 157 binary with case, 159 binary with decoder, 158 case implementation, 157 multiplier Booth recoder, 265 Booth top level, 264 floating-point, 247 unsigned four-bit, 225 pipeline register double buffer, 492 global stall, 490 prime plus 1 assign implementation, 134 case implementation, 129 casex implementation, 133 decimal, synthesized, 136 decimal with don t cares, 136 decoder implementation, 155 multiplexer implementation, 161 structural, 135 synthesized, 131 testbench, 137 testbench, go/no-go, 139 priority arbiter, 194 programmable, 170 priority encoder arbiter and encoder, 168 casex implementation, 169 processor, 407, 408 ALU, 406 pulse-filler FSM, 308 RAM, 179 representation converter fixed- to floating-point, 281 floating- to fixed-point, 282 ROM assign and reg implementation, 177 case implementation, 176 seven-segment decoder case implementation, 142 constant definitions, 141 inverse, 143 shift register LRL, 339 LSB only, 338 variable, 341 shifter barrel, 173 left, 173 thermometer detector assign implementation, 134 case implementation, 132 casex implementation, 133 structural implementation, 135 testbench, 140
610 of Verilog modules thermostat, 14 tic-tac-toe, combinational empty, 199 select 3, 199 testbench, 200 top level, 196 two-in-array, 197 two-in-row, 198 tic-tac-toe, sequential, 423 timer, 337 tomorrow days in month, 191 next day of week, 190 top level, 192 traffic-light controller factored combiner, 375 light FSM, 376 master, 374 simple definitions, 305 definitions, one-hot, 305 FSM, 304 testbench, 306 Universal shifter/counter, 341 vending machine combined, 351 controller, 346, 347 datapath, 348 testbench, 349 top-level, 345
SUBJECT INDEX, 48, 41, 41 absolute error, 236 absorption property, 42 accelerated life test, 444 accuracy, numerical, 237 activity factor, 96 adder carry look-ahead, 255 pipelined, 484 ripple-carry, 214 addition, 210 fixed-point, 241 floating-point, 247 address space, 524 alignment, floating-point, 247 allocator, crossbar, 508 AND, 41 switch circuit, 56 annihilation axiom, 42 AOI, 69 CMOS gate, 69 logical effort, 86 sizing, 85 arbiter, 165 bus, 505 look-ahead, 257 arithmetic logic unit (ALU), 404 ASIC, 27 associative property, 42 barrel shifter, 173 behavioral Verilog, 130 binary numbers, 207 binary point, 239 binary signal, 4 binary-coded decimal numbers, 208 Boolean algebra, 41 axioms, 42 properties, 42 Booth recoding, 260 radix-4, 262 radix-8, 264 radix-16, 264 bottleneck, 494 boundary scan, 441 branch multi-way, 394 two-way, 389 broadcast, bus, 507 bubble rule, 67 buffer, 6 bug tracking, 438 built-in-self-test, 442 bus, 505 arbiter, 505 multiple destinations, 507 split transaction, 507 bus notation, 150 cache, 524 direct-mapped, 526 eviction, 526 fully associative, 525 line size, 525 write policy, 527 CAD tools, 32 CAM, 525 capacitance, gate, 62 carry look-ahead, see look-ahead change control, 23 channels, 510 checking models, 144 circuit boards, 30 clock, 293 clock domain, 576 clock gating, 97 CMOS gate, 66 color, subtractive representation of, 11 combination lock, 348 combinational logic composition, 104 definition, 103 combining property, 42 commutative property, 42 comparator, 12, 170 complementation property, 42 composition of subsystems, 13 compressor, 269 concept development, 23 consensus property, 42 constraint file, 181 static timing, 325 contamination delay, 314 counter, 331 UDL, 333 cover, logic function, 114 coverage, 435 critical path, 88 crossbar, 507 allocator, 508 cube, representation, see logic representations data sheet, 181 datapath, 331 vending machine, 346 day of year, representing, 10 decimal numbers, 207 decoder, 150 SRAM, row, 516 use in logic implementation, 154 delay contamination, 314 with fan-out, 82 gate, 79 large load, 83 logic chain, 87 optimizing, 89 propagation, 314 wire, repeated, 93 wire, unbuffered, 92 De Morgan s theorem, 42 denormalized numbers, 245 DES cracker partitioning, 457 specification, 452 timing, 472 design process CAD tool flow, 32 general, 21 system, 449 dimension-order routing, 510 directed test, 437
612 Subject index distributive property, 42 divide-by-3 FSM, 414 divide and conquer, 195 division, 226 double buffering, 489 drain, 61 DRAM, 517 access scheduling, 524 access sequence, 517 atom, 519 interface, 517 precharge, 518 timing, 518 dual function, 44 Earle latch, 549 encoder, 161 encoding binary-weighted, 10 Gray, 19 thermometer, 10 energy dissipation, 96 EPROM, 177 equality comparison, 170 error, numerical absolute, 236 relative, 237 escape pattern, 30 event flow, 470 exhaustive test, 437 exponent, 243 fan-in, 84 fan-out, 82 fault model, 439 feasibility study, 25 FIFO, 581 find first 1 (FF1), see arbiter finite-state machine (FSM), 293 factoring, 360 implementation, 300 Verilog, 303 fixed-function logic, 16 fixed-point numbers, 238 flip-flop CMOS, 554 contamination delay, 318 D, 293, 317 derivation, 557 hold time, 318 implementation, 551 propagation delay, 318 pulsed, 561 RS, 292, 535 setup time, 317 flits, 512 floating-point numbers, 243 flow control, 371, 463 flow table, 534 FO4, 82 formal verification, 438 FPGA, 29 front end, analog, 15 full adder, 211 fundamental mode, 535 funnel shifter, 173 generate signal, 212 look-ahead, 255 gradual underflow, 245 grant matrix, 508 Gray code, 580 grid, 29 half adder, 210 hardware, 15 hazards, combinational, 120 dynamic, 121 static-0, 121 static-1, 121 head-of-line blocking, 522 hexadecimal, base-16, 208 high impedance, 72 hold time calculating, 550, 553 flip-flop, 318 latch, 548, 554 SRAM, 516 hold-time violations, 318 homing sequence, 310 Huffman decoder, 427 Huffman encoder, 423 idempotence property, 42 identity axiom, 42 idioms of digital design, 183 illegal state, 563 probability of entry, 567 implementation coverage, 436 implicant of a logic function, 108 implied 1, 244, 253 instantiation, module, 129 instruction types, 397 branch, 390 store, 397 intellectual property, 182 interconnect, 504 bus, see bus crossbar, see crossbar networks, 510 interface always valid, 461 isochronous, 468 packetized, 465 partitioning, 465 periodically valid, 462 pull timing, 463 push timing, 463 ready valid, 463 serial, 465 static, 462 inversion bubble, 48 inverter, see NOT iterative circuit, 166 JTAG, 441 Karnaugh map, 112 asynchronous, 537 latch, 548 derivation, 555 tri-state, 553 latency, 480 length, gate, 60 light flasher, 360 load balance, 494 locality, 525 logic diagram, 47 logic representations cube, 108 incomplete, 116 Karnaugh map, 112 normal form, 45, 107 sum of products, 45 logical effort, 84 look-ahead, 166, 255 LSB, 208 magnitude comparator, 171 look-ahead, 257 majority function, 44 CMOS gate, 70 switch network, 57 mantissa, 243 master FSM, 361 master slave FSMs, 371 master slave partitioning, 456 maxterm, 118 Mealy state machine, 297 memory bank conflicts, 523 banked, 519 bit-sliced, 519 hierarchy, 524 interleaved, 521 primitive, 515 metastability, 564
Subject index 613 convergence, 566 demonstration, 570 microcoded FSM, 383 microinstruction, 385 minimum cycle time, 318 minterm, 46, 107 model view controller partitioning, 456 module, 50, 129 monotonic functions, 66 Moore state machine, 297 Moore s law, 33 MOS transistor current, 62 electrical model, 62 operation, 61 speed, 64 switch model, 59 MSB, 208 multicast, bus, 507 multiple-of-3 circuit, 187 multiplexer, 155 binary-select, 158 function implementation with, 161 SRAM, column, 516 tri-state, 73, 156 multiplication, 223 Booth recoding, 260 complex numbers, 275 fixed-point, 242 floating-point, 245 Wallace tree, 265 music player partitioning, 457 specification, 454 timing, 473 NAND, 48 CMOS gate, 67 logical effort, 85 schematic, 48 sizing, 84 negation axiom, 42 nested timing, 466 NFET, 61 noise, 5 accumulation, 6 analog, 6 restoration, 6 noise margin, 7 NOR, 48 CMOS gate, 67 logical effort, 85 schematic, 48 sizing, 85 normal form, see logic representations normalization, 243 NOT, 41 CMOS gate, 67 delay, 79 energy, 96 power, 96 sizing, 81 transfer curve, 64 1 s complement, 216 one-hot code, 150 one-hot decoder, 150 opcode, 394 OR, 41 switch circuit, 56 oscillation, asynchronous, 534 overflow, 216 2 s complement, 219, 220 packet, 504 packetization, 466 parasitic capacitance, 90 partial product, 223 partitioning control and data, 342 system, 456 pass/fail simulation, 139 patch, microcode, 383 perfect induction, 43 PFET, 61 pipeline, 371, 479 adder, 484 double-buffered, 489 examples, 482 FIFO buffering, 494 stalls, 488 pipeline partitioning, 456 PLA (programmable logic array), 180 Pong partitioning, 456 specification, 451 timing, 471 port, SRAM, 516 power dynamic, 96 scaling, 97 static, 97 power gating, 97 precision, numerical, 237 predecoder, 152 prime implicant, 110 essential, 110 priority arbiter, 192 priority encoder, 167 processor, 15, 403 product implementation plan, 25 product-of-sums implementation, 118 program counter, 389 PROM, 176 propagate signal, 212 look-ahead, 255 propagation delay, 314 SRAM, 516 pulldown network, 67 pullup network, 67 quantized representation, 10 race, asynchronous, 534, 540 critical, 540 RAM (random access memory), 177 random test, 437 range fixed-point, 239 floating-point, 244 reduction, 164 register, 300 regression testing, 26 relative error, 237 repeater, 93 representation function, 236 resistance, source, 62 resolution, 237 fixed-point, 239 floating-point, 243 resource partitioning, 456 risks, 24 ROM (read-only memory), 173 function implementation with, 174 rounding, 237 router, 510 scaled numbers, 240 scaling, transistor, 33 scan chain, 441 SDDR3, 519 sequencer, microcode, 387 sequential circuits, 291 asynchronous, 533 synchronous, 293 serialization, 465 setup time calculating, 550, 552 flip-flop, 317 latch, 548, 554 SRAM, 516 setup-time violations, 318 seven-segment decoder, 124, 141 inverse, 143 shift register, 338 shifters, 173
614 Subject index shmoo plot, 443 sign extension, 221 sign-magnitude numbers, 216 signaling analog, 5 binary, 4 multi-bit, 9 signed numbers, 216 simulation, Verilog, 32, 137 sizing, logic gates, 84 skew, clock, 321 slack, timing, 320 software, 15, 405 SOS detection FSM, 415 source, 61 spatial locality, 525 specification, 22 system, 450 specification coverage, 435 speculation, 473 SRAM, 515 timing, 516 stable state, 534 stall, see pipeline standard cell, 27 state, 292 state assignment, 299 binary, 299 one-hot, 299 state diagram, 295 state equivalence, 556 state register, 300 state table, 295 straw man specification, 22 structural Verilog, 130 stuck-at fault, 439 subroutines, 400 subtractor, 220 sum of products, see logic representations switch circuit, 55 symmetric functions, 70 synchronization failure, 563 synchronizer, 576 brute-force, 577 FIFO, 581 sequence, 577 state, 577 synthesis, Verilog, 14, 130 system specification, 450 system timing, 461 temporal locality, 525 test patterns, 138 test plan, 26 test suite, 435 test vector, 439 testbench, 137 thermometer encoding, see encoding throughput, 479 tic-tac-toe, 193 sequential, 422 timer, 336 timing, interface, 461, see also interface timing analysis tools, 324 timing diagram, 292 timing table, 469 toggle circuit, 536 tomorrow circuit, 189 topology, interconnect, 510 total path effort, 89 tournament arbiter, 192 traffic-light controller factored, 367 unfactored, 296 trajectory map, 537 transfer curve, dc, 7 transient state, 534, 537 transistor, see MOS transistor tri-state circuits, 72 truncation, 237 truth table, 41, 105 2 s complement, 217 unit test, 26 unsigned numbers, 216 V 0,4 V 1,4 V IH,4 V IL,4 V max,4 V min,4 V NMH,7 V NML,7 V OH,4 V OL,4 value function, 236 vending machine FSM, 342 verification, 26, 435 Verilog, 14 Boolean expressions, 49 Verilog keywords!= (inequality), 170!== (four-state not equal), 139 << (left shift), 152 == (equality), 170 === (four-state equality), 139 >> (right shift), 152? : (conditional), 191 [X:Y], 129 % (modulo), 189 (or reduction), 164 (or), 50 & (and reduction), 164 & (and), 50 + (add), 215 - (subtract), 220 ˆ (xor), 50 ˆ(xnor), 170 {k{x}} (replication), 157 {x,y} (concatenation), 144 # (delay), 50, 137 (not), 50 always @, 130 always @(posedge), 305 always @(*), 130 and, 135 assign, 50, 133 case, 130 casex, 132 define, 141 endmodule, 14, 129 initial, 50, 137 input, 14, 129 instantiation, 131 module, 14, 129 nand, 135 nor, 135 numbers, 142 or, 135 output, 14, 129 parameter, 151 reg, 130 repeat, 137 signed, 275 wire, 14, 130 x, 132 xnor, 135 xor, 135 z, 73 virtual channels, 512 Wallace tree, 265 weighted number representation, 207 width, gate, 60 wires, 92 write buffer, 527 input, 108 output, 116 XNOR, 170 XOR, 47 CMOS gate, 71 switch circuit, 58 z state, 73