Generatore di parità. LIBRARY ieee; USE ieee.std_logic_1164.all ; ENTITY xor2 IS PORT( A, B : in std_logic ; Y : out std_logic ) ; END xor2 ;

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LIBRARY ieee; USE ieee.std_logic_1164.all ; ENTITY xor2 IS PORT( A, B : in std_logic ; Y : out std_logic ) ; END xor2 ; ARCHITECTURE arch1 OF Xor2 IS BEGIN Y <= A XOR B ; END arch1 ; LIBRARY ieee ; USE ieee.std_logic_1164.all ; Generatore di parità ENTITY parity IS GENERIC (W:integer:=8); PORT( D : in std_logic_vector(w-1 DOWNTO 0) ; OddParity : out std_logic ) ; END parity ; ARCHITECTURE arch1 OF parity IS COMPONENT xor2 PORT( A, B : in std_logic ; Y : out std_logic ) ; END COMPONENT ; SIGNAL P: std_logic_vector(0 TO W-2) ; -- SIGNAL P: std_logic_vector(0 TO 6) ; BEGIN g: FOR i IN 0 TO W-2 GENERATE -- g: FOR i IN 0 TO 6 GENERATE g0: IF (i = 0) GENERATE u0: xor2 PORT MAP(D(0),D(1),P(0)); END GENERATE g0 ; g1: IF ((i > 0) AND (i <= W-2)) GENERATE -- g1: IF ((i > 0) AND (i <= 6)) GENERATE u1: xor2 PORT MAP(P(I-1),D(I+1),P(I)); END GENERATE g1 ; END GENERATE g ; OddParity<=P(W-2); --OddParity<=P(6); END arch1 ;

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fa IS PORT( a, b : in std_logic ; cin : in std_logic ; cout : out std_logic ; sum : out std_logic ) ; END fa ; Adder a 24 bit ARCHITECTURE arch1 OF fa IS BEGIN sum <= (a XOR b) XOR cin ; cout <= (a AND b) OR ((a OR b) AND cin) ; END arch1 ; LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY add24bit IS PORT( a, b : in std_logic_vector(23 DOWNTO 0) ; cout : out std_logic ; cin : in std_logic ; sum : out std_logic_vector(23 DOWNTO 0) ) ; END add24bit ; ARCHITECTURE arch1 OF add24bit IS COMPONENT fa PORT( a : in std_logic ; b : in std_logic ; cin : in std_logic ; sum : out std_logic ; cout : out std_logic ) ; END COMPONENT ; SIGNAL c: std_logic_vector(23 DOWNTO 1) ; BEGIN g: FOR i IN 0 TO 23 GENERATE g0: IF (i = 0) GENERATE x0: fa PORT MAP(a(0), b(0), cin, sum(0), c(1)) ; END GENERATE g0 ; g1: IF ((i > 0) AND (i < 23)) GENERATE x0: fa PORT MAP(a(i), b(i), c(i), sum(i), c(i+1)) ; END GENERATE g1 ; g2: IF (i = 23) GENERATE x0: fa PORT MAP(a(23), b(23), c(23), sum(23), cout) ; END GENERATE g2 ; END GENERATE g ; END arch1 ;

Operatori Gli operatori permettono di formare espressioni complesse, e.g. : res <= a AND NOT(B) OR NOT(a) AND b; Precedenze in ordine decrescente: Miscellaneous operators: **, abs, not Multiplication operators: *, /, mod, rem Sign operator: +, - Addition operators: +, -, & Shift operators: sll, srl, sla, sra, rol, ror Relational operators: =, /=, <, <=, >, >= Logical operators: AND, OR, NAND, NOR, XOR, XNOR

Operatori:Esempi Concatenazione: & VARIABLE shifted, shiftin : BIT_VECTOR(0 TO 3);... shifted := shiftin(1 TO 3) & '0'; 0 1 2 3 SHIFTIN 1 0 0 1 SHIFTED Elevamento a potenza ** 0 0 1 0 x := 5**5 -- 5^5, OK y := 0.5**3 -- 0.5^3, OK x := 4**0.5 -- 4^0.5, Illegal y := 0.5**(-2) -- 0.5^(-2), OK

VHDL Objects There are four types of objects in VHDL Constants Variables Signals Files The scope of an object is as follows : Objects declared in a package are available to all VHDL descriptions that use that package Objects declared in an entity are available to all architectures associated with that entity Objects declared in an architecture are available to all statements in that architecture Objects declared in a process are available only within that process

VHDL Objects: Constants Name assigned to a specific value of a type Allow for easy update and readability Declaration of constant may omit value so that the value assignment may be deferred Facilitates reconfiguration Declaration syntax : CONSTANT constant_name : type_name [:= value]; Declaration examples : CONSTANT PI : REAL := 3.14; CONSTANT SPEED : INTEGER;

VHDL Objects:Variables Provide convenient mechanism for local storage E.g. loop counters, intermediate values Scope is process in which they are declared All variable assignments take place immediately No delta or user specified delay is incurred Declaration syntax: VARIABLE variable_name : type_name [:= value]; Declaration examples : VARIABLE opcode : BIT_VECTOR(3 DOWNTO 0) := "0000"; VARIABLE freq : INTEGER;

VHDL Objects:Signals Used for communication between VHDL components Real, physical signals in system often mapped to VHDL signals ALL VHDL signal assignments require either delta cycle or user-specified delay before new value is assumed Declaration syntax : SIGNAL signal_name : type_name [:= value]; Declaration and assignment examples : SIGNAL brdy : BIT; brdy <= '0' AFTER 5ns, '1' AFTER 10ns;

VHDL Objects:Files Files provide a way for a VHDL design to communicate with the host environment File declarations make a file available for use to a design Files can be opened for reading and writing The package STANDARD defines basic file I/O routines for VHDL types

Files Il VHDL definisce gli oggetti file, dei tipi di dato associati e delle operazioni TYPE file_type IS FILE OF type_mark; PROCEDURE READ(FILE identifier : file_type; value : OUT type_mark); PROCEDURE WRITE(FILE identifier : file_type; value : IN type_mark); FUNCTION ENDFILE(FILE identifier : file_type) RETURN BOOLEAN; File declarations FILE identifier : file_type [[OPEN mode] IS file_name ]; Il VHDL usa il package TEXTIO della library STD per manipolare file di testo USE STD.TEXTIO.ALL;

Procedure del package TEXTIO TEXTIO definisce un tipo di dato LINE su cui eseguire operazioni di read e write TEXTIO definisce un tipo di datotext per I FILE da utilizzare con I file ASCII Le procedure definited sono: Readline(f,k) legge una line dal file f e la mette nel buffer k Read(k,v,) Legge un valore v da k Write(k,v,...) Scrive il valore v sulla LINE k Writeline(f,k) Scrive la LINE k sul file f Endfile(f) restituisce TRUE alla fine del file f

Data Types All declarations of VHDL ports, signals, and variables must specify their corresponding type or subtype Types Access Composite Scalar Array Record Integer Real Enumerated Physical

VHDL Data Types: Scalar Types Integer Minimum range for any implementation as defined by standard: - 2,147,483,647 to 2,147,483,647 Example assignments to a variable of type integer : ARCHITECTURE test_int OF test IS BEGIN PROCESS (X) VARIABLE a: INTEGER; BEGIN a := 1; -- OK a := -1; -- OK a := 1.0; -- illegal END PROCESS; END test_int;

VHDL Data Types: Scalar Types (Cont.) Real Minimum range for any implementation as defined by standard: -1.0E38 to 1.0E38 Example assignments to a variable of type real : ARCHITECTURE test_real OF test IS BEGIN PROCESS (X) VARIABLE a: REAL; BEGIN a := 1.3; -- OK a := -7.5; -- OK a := 1; -- illegal a := 1.7E13; -- OK a := 5.3 ns; -- illegal END PROCESS; END test_real;

VHDL Data Types:Scalar Types (Cont.) Enumerated User specifies list of possible values Example declaration and usage of enumerated data type : TYPE binary IS ( ON, OFF );... some statements... ARCHITECTURE test_enum OF test IS BEGIN PROCESS (X) VARIABLE a: binary; BEGIN a := ON; -- OK... more statements... a := OFF; -- OK... more statements... END PROCESS; END test_enum;

Time is the only physical type predefined in VHDL standard VHDL Data Types:Scalar Types (Cont.) Physical Require associated units Range must be specified Example of physical type declaration : TYPE resistance IS RANGE 0 TO 10000000 UNITS ohm; -- ohm Kohm = 1000 ohm; -- i.e. 1 KΩ Mohm = 1000 kohm; -- i.e. 1 MΩ END UNITS;

VHDL Data Types:Composite Types Array Used to group elements of the same type into a single VHDL object Range may be unconstrained in declaration Range would then be constrained when array is used Example declaration for one-dimensional array (vector) : VARIABLE X : data_bus; VARIABLE Y : BIT; TYPE data_bus IS ARRAY(0 TO 31) OF BIT; 0...element indices... 31 0...array values... 1 Y := X(12); -- Y gets value of element at index 12

VHDL Data Types:Composite Types (Cont.) Example one-dimensional array using DOWNTO : TYPE reg_type IS ARRAY(15 DOWNTO 0) OF BIT; VARIABLE X : reg_type; VARIABLE Y : BIT; 15...element indices... 0 0...array values... 1 Y := X(4); -- Y gets value of element at index 4 DOWNTO keyword must be used if leftmost index is greater than rightmost index

VHDL Data Types: Composite Types (Cont.) Records Used to group elements of possibly different types into a single VHDL object Elements are indexed via field names Examples of record declaration and usage : TYPE binary IS ( ON, OFF ); TYPE switch_info IS RECORD status : BINARY; IDnumber : INTEGER; END RECORD; VARIABLE switch : switch_info; switch.status := ON; -- status of the switch switch.idnumber := 30; -- e.g. number of the switch

VHDL Data Types:Subtypes Subtype Allows for user defined constraints on a data type e.g. a subtype based on an unconstrained VHDL type May include entire range of base type Assignments that are out of the subtype range are illegal Range violation detected at run time rather than compile time because only base type is checked at compile time Subtype declaration syntax : SUBTYPE name IS base_type RANGE <user range>; Subtype example : SUBTYPE first_ten IS INTEGER RANGE 0 TO 9;

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