DPDK s Best Kept Secret: Micro-benchmarks M Jay Mthrajan.Jayakmar@intel.com DPDK Smmit - San Jose 2017
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Agenda Why shold I care abot DPDK Micro-benchmarks? What do they benchmark? How do I rn them?
Not all slots are made eqal Ensre that yo have plgged in yor NIC card in most optimal slot Not all slots are made eqal!
How many lcores, yo think, are there in this 2 socket server? 64 lcores? 96 lcores? More than 100 lcores?
Qestion: What can be Improved here? CPU 0 CPU 1 6
Improvements -n 4 CPU 0 CPU 1 I/O Plgged in CPU1 s Slot How mch memory do yo see in CPU1 node? ZERO! CPU 0 has only One Channel memory poplated. 7
In Which Socket lcore # 50 resides? Socket 0 or Socket 1? More than 100 lcores Qestion: In which socket yo think lcore# 50 resides? socket 0? Or socket 1? Socket 0? Socket 1? Assme NIC is Plgged in socket 0 Will the performance be best or sb-optimal?
Why Shold I Care Abot DPDK Micro-benchmarks? We thoght lcore # 50 resides in socket 0. Bt actally, yo can see it is in socket 1. So, NIC in socket 0 is actally sb-optimal. How to qantitatively ensre that system is set for optimal performance?
QUIZ: Cores Within A Socket All In Same Loop?
Demo
Cores Within A Socket Not eqal proximity
Prior to application level benchmarking.. Withot tightening these, if yo start developing yor application And on top of that, if yo start measring application level performance Root case analysis is made nnecessarily complex Instead what if.. What if yo can do basic benchmarking of key performant elements / ops Yo will bild strong fondation first Will help yo develop Applications confidently towards overall higher performance
What Objects, What Operations to benchmark? In other words, what are the key high performant objects and operations? Objects: Ring Mem pool Mbf Operations: Mem copy Hash Operations Flow Classification
Test_hash_mltiwriter_main( ) Hash Mlti-writer Transactional Memory
Tests: Ring, PMD, Table
Roter, Memcpy, Hash
Tests: Crypto, Event, Flow Classify
Mempool
SPSC MPMC Time Taken
Call To Action: Where To Find Them & How It Measres?
Optimization Notice Optimization Notice Intel s compilers may or may not optimize to the same degree for non-intel microprocessors for optimizations that are not niqe to Intel microprocessors. These optimizations inclde SSE2, SSE3, and SSSE3 instrction sets and other optimizations. Intel does not garantee the availability, fnctionality, or effectiveness of any optimization on microprocessors not manfactred by Intel. Microprocessor-dependent optimizations in this prodct are intended for se with Intel microprocessors. Certain optimizations not specific to Intel microarchitectre are reserved for Intel microprocessors. Please refer to the applicable prodct User and Reference Gides for more information regarding the specific instrction sets covered by this notice. Notice revision #20110804 22
Qestions? M Jay Mthrajan.Jayakmar@intel.com