Testable SOC Design Sungho Kang 2001.10.5
Outline Introduction SOC Test Challenges IEEE P1500 SOC Test Strategies Conclusion 2
SOC Design Evolution Emergence of very large transistor counts on a single chip Mixed technologies on the same chip Creation of Intellectual Property (IP) Reusable IP-based design Boundary Scan TAP Controller Logic BIST Memory BIST`Test Access DSP Core IP Core IO Pad CPU Core UDL ROM DRAM IO Pad Data Path IP Core IP Core 3
IP Core Types Soft Core (RTL) Leave much of the implementation to the designer Flexible and process-independent Hard Core (Technology dependent layout) Predictable area and performance, but lack of flexibility Firm Core (Netlist) Offer a compromise between the two Each type of core has different modeling and test requirements 4
Problems of Conventional Testing Potential yield losses as Cycle time of the manufactured devices becomes comparable to ATE timing accuracy Increasing cost of ATE driven by Increasing pin count High frequency features 5
SOC Test Challenges System integrator may have very limited knowledge of the adopted core Core provider may not know which test method, what types of faults, and what level of fault coverage to use Test of the embedded IP core is the joint responsibility of both core provider and system integrator Deeply embedded cores limit access to core port Mixed Technologies The basic requirement is that test must not slow down overall growth of semiconductor and computing industries 6
IEEE P1500 Standardize a core test architecture Define a core test interface Facilitate test reuse for embedded cores Facilitate core test interoperability to improve efficiency of test between core provider and core users Scope Standardize core test mechanisms for core access and isolation SOC test access mechanism is defined by the system integrator The core test method is defined by the core provider Task Forces Core Test Language Scaleable Architecture Compliance Definition Terminology Documentation Mergeable Cores test 7
Core Test Language (CTL) Define language constructs to describe the test aspects of cores CTL allows black-boxing of a core CTL can be described at any hierarchical level CTL enable for Core creator describes core test and constraints DFT provider develops test integration tools Core integrator captures SOC test architecture Chip CTL{ si0 si1 D[0...4] Core so0 so1 q[0 2] } This is the way to scan This is the timing requirement This is what you do to get into quiet mode This is what you do to test the shadow logic wsi wip_ctrl wrck wso 8
Scaleable Architecture Define a standard wrapper plus interface to on-chip test access mechanism Define Test Control Mechanism Dynamic control (control protocols) Static control ( mode: internal, external, isolation) Define Test Access Mechanism Internal VS external test signals Tapped VS non-tapped cores Core Wrapper Boundary Register WSI Bypass WIR Wrapper Boundary WSO Cells WIP Controls & Clock 9
System Chip with P1500 Wrapped Cores TAM-Source User Defined Test Access Mechanism TAM-Sink TAM-In TAM-Out TAM-In TAM-Out Standard P1500 Standard P1500 Chip Inputs Core 1 Core N Chip Outputs Core Test Wrapper WSO 1 WSI N Core Test Wrapper WSI 1 Wrapper control WSO N P1500 WIP TAM Source/Sink System Chip From chip I/O, test bus/rail/port, BIST, etc.. TAM In/Out 0 to n lines for parallel and/or serial test data, or test control P1500 Wrapper Interface Port(WIP) From chip-level TAP controller, chip I/0, 10
Dual Compliance Concept IEEE P1500 Unwrapped Core which does not have a complete IEEE 1500 wrapper, but does have an IEEE CTL description on the basis on which the core could be made IEEE 1500 Wrapped (either manually or automatically by tools) IEEE P1500 Wrapped Incorporates complete IEEE P1500 wrapper function Complete IEEE 1500 CTL description describing how to test the core(including how to operate the wrapper) 11
SOC Test Composite Test Individual test for each IP core, UDL, interconnect logic and wiring Test Scheduling To meet SOC requirements such as total test time, power dissipation, area overhead To avoid affecting the initialization and final contents of individual cores Sufficient fault coverage, overall test cost, time-to-market 12
IP Testing Test Ready Core Ease integration and test reuse Resolve access issues through design recommendations Test architecture flexibility during integration Supply all required test information Minimize Test bandwidth Test volume Test application time 13
IP Testing DFT Architecture Memory BIST Logic BIST Scan Boundary scan SoC Test Controller Logic BIST Memory BIST Test Access Test Methodology Stuck-at testing Delay testing Iddq testing IO Pad DSP Core CPU Core UDL IP Core ROM DRAM IO Pad IP Core Data Path IP Core 14
Test Access No Direct Physical Access Method Test access mechanism is required Test Access Mechanism Transports test from source to core and from core to sink Provides features to test the hardware in between the IP cores Isolates IP core Today s chip is tomorrow s core 2nd Generation Core Test Access 1st Generation Core Test Control I/F Test Control I/F 3rd Generation Core Test Control Interface 15
Hierarchical Test Access Testing taped core and wrapped core with the same test access mechanism Direct access to the wrapper WIR can be enabled, while the instruction register within the TAPed core can only be accessed through the TAP finite state machine Board level P1149.1 features are preserved Parallel TAM IEEE 1149.1 Features Taped Core Serial TAM Test Controller Wrapped Core IEEE 1149.1 Features TDI TCK TMS TDO 16
SOC Test Controller Control various core types Achieve efficient test scheduling Achieve effective test data access TAM TAM TAM TAM BIST Source Sink SoC Test Controller 17
DFT of SOC 18
Conclusion Solving the test problems will be critical to producing SOC For efficient SOC test, not only DFT at the core design but also DFT at the core integration must be considered 19