EECS 579: Built-in Self-Test 3. Regular Circuits

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1 EECS 579: Built-in Self-Test 3 Outline Implementing BIST by regularization Adder ALU RAM Commercial BIST approaches LOCSD STUMPS CSTP Case Study Bosch AE11 microcontroller John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 1 Regular Circuits Circuits composed of (nearly) identical cells with (nearly) uniform interconnections Structured as n-dimensional iterative logic arrays or trees Regular circuits tend to be easy to test Examples Random-access memories (RAMs and ROMs) Arithmetic circuits: adders, multipliers, etc. Data-transfer circuits: (de)multiplexers, decoders, etc. Nearly regular circuits can often be made regular for testing purposes (regularization) John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 2

2 Regular Circuits and BIST (Nearly) identical test patterns implying small, easily generated test sets C C C (Nearly) identical responses allowing use of equality checkers as response monitors John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 3 Example: Ripple-Carry Adder All CF faults in an N-bit RC adder can be detected by a constant number of test patterns for any N, implying that it is C-testable C 3 C 2 C 1 C C 3 C 2 C 1 C John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 4

3 Example: Ripple-Carry Adder For BIST, an N-bit RC adder can be tested using 2N + 6 patterns that produce identical responses from all cells, implying that it is I-testable. Faults can be detected by comparing the cell outputs C 3 C 2 C 1 C C 3 C 2 C 1 C John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 5 BIST via Regularization Add logic as necessary to allow temporary creation of a regular array for self-testing Modify the cells as necessary to make the regularized array C- and/or I-testable Input data TEST Input data Test generation and application logic C 0 Reg'ized Reg'ized C 1 C m cell cell Reg'ized cell Output data Original circuit Response sync. and comparison logic Output data ERROR Self-testing design John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 6

4 Nearly Regular ALU: 74X381 C X Control logic C C C C Four-bit datapath logic (bit-sliced) John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 7 Regularized Version of 74X381 From C X Added control lines C C C C Added gates (shaded) John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 8

5 BIST Implementation of 74X381 Regularized 1-bit ALU modules Test pattern generator based on NLFSR TEST CLOCK C X Duplicate copy of C X C C C C 0 Response shift register and equality checker Error latch ERROR1 ERROR2 John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 9 Regularizing a Tree Circuit: 74X154 I 1 I 2 I 3 I 4 E Original cir cuit:1-out-of-16 decoder/demultiplexer Requires O(2 n ) = 32 tests to detect all SSL faults Test R I 1 I 2 I 3 I 4 E Regularized cir cuit Requires O(n) = 11 tests to detect all SSL faults John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 10

6 BIST for RAMs Testing Problems High component count and density Complex fault types, e.g., pattern sensitivity Long testing times to achieve high fault coverage: O(N k ) for an N-bit RAM, 1 k 2. Large overhead or limited fault coverage for self-testing via conventional techniques BIST Approaches EC/ED code circuits (concurrrent) Special nonconcurrrent test logic that exploits the RAM s inherent regularity John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 11 RAM Layout Data in/out Address Row decoder array Sense amplifiers array Data buffer Address buffer Self-testing col. decoder Refresh control Control Row decoder array Sense amplifiers array John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 12

7 RAM as Nearly-Regular Array C X C 1 C 2 C m Address Data Control Control logic Row dec. Row dec. Sense amp Col. dec. Sense amp Sense amp Col. dec. Sense amp Sense amp Col. dec. Sense amp John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 13 Self-Testing RAM [You and Hayes 88] Modified standard RAM with on-chip TG and RM logic Tests are derived from standard RAM tests and are highly regular Array cells are normal storage subarrays with modified peripheral circuitry RAM behaves like a shift register during testing Many cells are tested in parallel to reduce testing time Test Derivation Complete test subsequences are derived for all expected RAM faults 1. Apply read/write excitation to set of cells in all storage arrays 2. Read test cells and background pattern 3. Modify background pattern for next test step Individual test subsequences are overlapped to form a composite C/Istyle test for an entire storage subarray John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 14

8 Self-Testing RAM Address Row decoder array Sense amplifiers array C Data in/out Data buffer Address buffer Refresh control Control Row decoder Equality checker Self-testing col. decoder Equality checker array Sense amplifiers array C Test generation & control Set Error test mode John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 15 Self-Testing RAM The RAM is made fully self-testing for all recognized failure modes Testing time is O(R 0.5 ) where R is the number of cells in a storage subarray C Area overhead due to BIST is a few percent of total area for storage capacities in the multimegabit range Two or three extra I/O pins needed to initiate self-testing and observe test responses John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 16

9 LOCST (LSSD On-Chip Self-Test) SISR = Single-input signature register (LFSR) SRL = shift register latch SRSG = shift register sequence generator (LFSR) Centralized and separate BIST (LSSD boundary) scan paths around the CUT Serial, LFSR-based test pattern generation and response compression John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 17 STUMPS External logic MISR = Multiple-input signature register (LFSR) PRPG = Pseudorandom pattern generator (LFSR) STUMPS = Self-Test Using MISR and Parallel SRSG [IBM 1982] External logic Centralized and separate BIST Multiple scan paths without boundary scan Designed to have low overall testing time John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 18

10 CSTP (Circular Self-Test Path) Mixes conventional and special self-test registers Self-test registers are have three modes: normal, scan, and test. In the test mode, the system data is XORed with scan data Self-test cell s 0 s 1 s 2 s 3 s 4 All I/O lines are linked in a circular (boundary) scan path John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 19 CSTP (contd.) Features Initializable registers not scanned TG and response compression done in scan path Advantages: Low area overhead Easy design Simple test control Drawbacks Low fault coverage John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 20

11 Case Study: Bosch AE11 Microcontroller Single-chip, self-testing microcontroller designed to detect hardware faults rapidly under all operating conditions Intended for safety-critical applications like automotive control Compatible with Intel bit ISA; 4-KB RAM and I/O modules Self-testing Features: Parity checking throughout the system Parity checking and ALU parity prediction in the CPU datapath Program control-flow checking via signature monitoring Self-checking address decoding logic in the RAM Programmable watchdog timer Pseudorandom test and I DDQ testing of peripheral modules Power supply and temperature monitoring Test control employing boundary scan and a TAP controller John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 21 Bosch AE11 Microcontroller (contd.) Test controller start BIST Test access port (TAP) break 3 run_adc adc_ok 5 run_alu run_bist run_iddq alu_ok 2 Analog-digital converter (ADC) bist_ok run_bist run_iddq 2 Error flags Serial I/O Watchdog timer Misc. I/O modules Central processing unit (CPU) ALU RAM CPU control LFSRs System bus John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 22

12 Bosch AE11 Microcontroller (contd.) CPU Testing Datapath uses parity prediction, which has low cost and is compatibile with the AE11 s overall use of parity codes. Control unit applies parity checking to control words Software control-flow checking is supported: Signatures are computed during compilation and are inserted automatically into programs. Special AE11 instructions monitor these signatures. RAM Testing The AE11 s fault latency requirements rule out conventional RAM BIST methods which are slow and destroy stored data Parity check bit are added to address and data buses RAM parity checkers are self-checking Special BIST logic detects word line and address decoder faults Special circuits detect bridging faults, including resistive shorts John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 23 Bosch AE11 Microcontroller (contd.) I/O Testing The I/O subsystemalso uses parity checking Peripheral modules are tested on-line via BIST logic and I DDQ testing that employs on-chip current monitors. Test Control Testing functions are handled by a test controller that conforms to the IEEE boundary scan standard The special BIST logic uses pseudorandom test and signature generation implemented by LFSRs in the CPU and MISRs in the I/O modules The pseudorandom test patterns are believed to provide protection against unknown or non-targeted hardware faults, as well as standard SSL faults. John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 24

13 Bosch AE11 Microcontroller (contd.) Test Management Start-up tests check that the major subsystems, CPU, RAM and peripheral modules, are operational In normal operation, concurrent checking circuits flag the errors when they occur CPU is interrupted periodically to execute test procedures such as the I DDQ tests and various functional tests Performance and Cost Estimated to achieve more than 99.7% coverage of modeled faults and errors Less than 35% chip area overhead Less than 15% performance loss John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 22 Page 25