VHDL for FPGA Design. by : Mohamed Samy

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Transcription:

VHDL for FPGA Design by : Mohamed Samy

VHDL Vhdl is Case insensitive myvar = myvar = MYVAR IF = if = if Comments start with -- Comments can exist anywhere in the line Semi colon indicates the end of statements Vhdl Design Units Packages Library Entity Architecture

Library All VHDL objects ultimately reside in libraries By definition, a library is a collection of analyzed design units Work and std are the two libraries available to every design unit Libraries and Packages comprise the VHDL Design Management structure This is somehow analogous to directories and subdirectories

Library & Packages A library can be considered as a place where the compiler stores information about a design project. A VHDL package is a file or module that contains declarations of commonly used objects, data type, component declarations, signal, procedures and functions. To specify the library and package, use the library and the use keywords. For example to include the std_logic_1164 package that exists in the library ieee Library ieee; use ieee.std_logic_1164.all; The.all extension indicates to use all of the ieee.std_logic_1164 package.

Multiple Architecture Multiple architectures can exist for each entity These may represent different stages of the design process or different approaches to the same functionality (optimization for speed verus area, etc.)

How to identify any hardware? A B DU1 and DU3 F B A C DU2 and F A B or F For a given interface we can have many functionalities To identify a given design unit: Interface (input/output ports) Input-output relation (the DU functionality)

VHDL Design Unit Entity Describes the external interface of a hardware module Black Box entity <entity_name> is port ( <port_name> : <mode> <type>; <other ports>... ); End entity;

VHDL Design Unit Architecture An architecture describes the internal operation of its associated (primary) entity A given architecture represents one possible implementation for its associated entity, multiple architectures can exist for each entity Half Adder architecture <arch_name> of <entity_name> is -- architecture body end <arch_name>; Full Adder

Entity: entity <entity_name> is port ( <port_name> : <mode> <type>; <other ports>... ); End entity; Modes : In : input to this device Out : output from this device Inout : input to or output from this device Buffer : output from device and can be read inside the device

Illegal Port Usage Signal Defined As Out Cannot Be Used As Signal Connected to Internal Device. entity (W,X,Y: in bit; A,B: out bit);

Entity: Data types : wire : bit ---- 0 or 1 std_logic ------------------- std_ulogic ------------------- entity <entity_name> is port ( <port_name> : <mode> <type>; <other ports>... ); End entity; U -- Uninitialized X -- Forcing Unknown 0 -- Forcing Zero 1 -- Forcing One Z -- High Impedance W -- Weak Unknown L -- Weak Zero H -- Weak One - -- Don t Care bus : bit_vector ( range ) -> 001 std_logic_vector ( range ) -> 001 range: 0 to 7 3 downto 0 Note: std_logic and std_ulogic are defined in IEEE.STD_LOGIC_1164

Entity: (cont.) Example: full adder Entity fulladder is port ( x : in bit ; y : in bit ; z : in bit ; c : out bit ; o : out bit ) ; End fulladder; x y z fulladder c o Direction Data type

Architecture: A design unit associated with an entity which describes its internal operation or organization. Multiple architectures may be defined for a single entity Example: Architecture arch of fulladder is declarative area Begin concurrent statements are written here End arch; Declarative area: to declare signals, components and data types

Architecture: (cont.) Statement types: 1 2 A C Concurrent: Boolean equation. when else. With select. Process Generate Instances B Sequential: Boolean equation. If else. case when loops. wait.

Don t forget Concurrent statements (Default) Executed in parallel With select When else Process statements Generate statements Sequential statements (within Process) Executed in sequence If statement Case statement loop statement Wait statement Note : Sequential statements must be used within process

Architecture Concurrent statements Boolean When-else With-select Process

Concurrent statements: 1. Boolean equation: s <= a xor b and c; Note: Use of parentheses is absolutely essential to specify operator precedence. Only the not operator has inherently higher precedence among logical operators.

Architecture: (cont.) Example: Example: full adder Architecture arch of fulladder is Begin o <= x xor y xor z; c <= (x and y) or (z and (x xor y)); End arch; x y z fulladder c o

Concurrent statements: 2. When. Else: <sig1> <= value1 when condition1 else value2 when condition2 else. valuen; a Architecture behave of mux is Begin F <= a when sel = 00 else b when sel = 01 else c; End behave ; b c Sel(1:0) F What is the result if the last else statement doesn t exist?

Concurrent statements: 3. With. select: With < signal1> select Signal2 <= value1 when choice1, value2 when choice2,. valuen when others ; Architecture behave of mux is Begin With sel select F <= a when 00, b when 01, c when others; End behave; b c a Sel(1:0) F What is the result if there is no when others?

Skills check Try the following: Bus Mux Modified Bus Mux A(7:0) B(7:0) C(7:0) D(7:0) F(7:0) Ssel(2:0) G Bsel(1:0)

Concurrent statements: A process contains statements that are executed sequentially The order of the statements impacts the final result Process (sensitivity_list) list of sequential statements end process ; List of signals, any change in any of them causes the process statement to be executed.

Language Structure architecture RTL of ENTITY_1 is concurrent statements ; process sequential statements ; end process ; concurrent statements ; process sequential statements ; end process ; end architecture RTL ;

Signal assignment inside process The signal assignment statement Z <= A causes a transaction to be scheduled This means; the current value of A is read and scheduled to be driven onto Z when the process suspends process (...) Z <= A ; F <= G ; X <= F;... end process ;

Architecture Sequential statements Boolean Case If Loops Wait

Sequential statements: 1. Boolean equation: s <= a xor b xor c; Architecture behave of fulladder is Begin process (?) (x,y,z) o <= x xor y xor z; c <= (x and y) or (z and (x xor y)); end process; End behave ; Signals in sensitivity list create implied wait condition x y z fulladder c o

Sequential statements: 2. Case when: case <signal_name> is when value => list of sequential statements; when value => list of sequential statements; when others => list of sequential statements; end case; ENTITY mux IS PORT( a, b, c, d: in bit; sel: IN bit_vector(1 downto 0); F: OUT bit); END ENTITY mux; ARCHITECTURE rtl OF mux IS process (a,b,c,d,sel) (?) is is CASE sel IS WHEN "00" => F <= a; WHEN "01" => F <= b; WHEN "10" => F <= c; WHEN "11" => F <= d; END CASE; END PROCESS ; END ARCHITECTURE rtl; a b c d Sel(1:0) What about when others? F

Sequential statements: Case when: case <signal_name> is when value =>list of sequential statements; when value =>list of sequential statements; when others =>list of sequential statements; end case; ENTITY mux IS PORT( a, b, c, d: IN bit; s: IN bit_vector(1 downto 0); x: OUT bit); END ENTITY mux; ARCHITECTURE rtl OF mux IS BEGIN sl: PROCESS (a,b,c,d,sel) IS BEGIN CASE s IS WHEN "00" => x <= a; WHEN "01" => x <= b; WHEN "10" => x <= c; WHEN "11" => x <= d; END CASE; END PROCESS sl; END ARCHITECTURE rtl; ENTITY mux IS PORT( a, b, c, d: IN bit_vector (3 DOWNTO 0); s: IN bit_vector (1 DOWNTO 0); x: OUT bit_vector (3 DOWNTO 0)); END ENTITY mux; ARCHITECTURE rtl OF mux IS BEGIN sl: PROCESS (a,b,c,d,s) IS BEGIN CASE s IS WHEN "00" => x <= a; WHEN "01" => x <= b; WHEN "10" => x <= c; WHEN "11" => x <= d; END CASE; END PROCESS sl; END ARCHITECTURE rtl;

Two-input Exclusive OR function A process example for a 2-input exclusive-or function is illustrated below. For this function, there are two input signals, in1 and in2, and one output signal. x_or : sig1 <= in1 xor in2; Concurrent signal assignment: output is updated when signals on the right change x_or : process (in1, in2) is sigl <= in1 xor in2; end process x_or; Signal assignment in process: output is updated when process suspends

Sequential statements: 3. if. Else: If <condition> then list of sequential statements; Elsif <condition> then list of sequential statements; Elsif <condition> then list of sequential statements;.. End if;

Sequential statements: ENTITY latch IS PORT( d, clk: IN bit; q, nq: OUT bit); END ENTITY latch; ARCHITECTURE behav OF latch is BEGIN p1: PROCESS (d, clk) BEGIN IF clk = '1' THEN q <= d; nq <= NOT(d); END IF; END PROCESS p1; END behav; if <condition> then list of sequential statements Elsif <condition> then list of sequential statements End if; Library ieee; use ieee.std_logic_1164.all; ENTITY D_FF IS PORT( d, clk: IN std_logic; q, nq: OUT std_logic); END ENTITY D_FF; ARCHITECTURE behav OF D_FF is BEGIN p1: PROCESS (d, clk) BEGIN IF rising_edge(clk) THEN q <= d; nq <= NOT(d); END IF; END PROCESS p1; END behav; Is d required in sensitivity list?

Sequential statements: Library ieee; use ieee.std_logic_1164.all; entity D_FF_Asynch_rst is port( d, clk: in std_logic; q: out std_logic); end entity; architecture behav of D_FF_Asynch_rst is process (clk, rst) If rst = 0 then q <= 1 ; Else if falling_edge (clk) then q <= d; end if; End if; end process; end behav; Library ieee; use ieee.std_logic_1164.all; entity D_FF_Synch_rst is port( d, clk: in std_logic; q, nq: out std_logic); end entity ; architecture behav of D_FF_Synch_rst is process (clk) if falling_edge (clk) then if (rst = 1 ) q <= 0 ; nq <= 1 ; else q <= d; nq <= not(d); end if; End if; end process; end behav;

Sequential statements: entity latch_asynch_rst is port (d, clk: in bit; q: out bit); end entity; architecture behav of latch_asynch_rst is process (d, clk, rst) if rst = 1 then q <= 0 ; else if clk = '1' then q <= d; end if; end if; end process; end behav; entity latch_synch_rst is port (d, clk: in bit; q: out bit); end entity; architecture behav of latch_synch_rst is process (d, clk, rst) if clk = '1' then if rst = 1 then q <= 0 ; else q <= d; end if; end if; end process; end behav;

Sequential statements: q doesn t change architecture behav of D_FF_Asynch_rst_clkEnable is PROCESS (clk, rst) BEGIN If rst = 0 then q <= 1 ; Else IF rising_edge (clk) THEN if en = 1 then q <= d; end if; END IF; End if; END PROCESS; END behav; q is high impedance architecture behav of D_FF_Asynch_rst_clkEnable is PROCESS (clk, rst) BEGIN If rst = 0 then q <= 1 ; Else IF rising_edge (clk) THEN if en = 1 then q <= d; else q <= Z ; end if; END IF; End if; END PROCESS; END behav;

Sequential statements: ARCHITECTURE behav OF D_FF_gated_Clk IS BEGIN PROCESS (en, clk, rst) BEGIN If rst = 0 then q <= 1 ; Else if en = 1 then IF rising_edge (clk) then q <= d; end if; END IF; End if; END PROCESS; END behav;

Concurrent vs. Sequential Statements Concurrent Sequential entity XNOR2 is port (A, B: in std_logic; Z: out std_logic); end XNOR2; architecture concurrent of XNOR2 is -- signal declaration (of internal signals X, Y) signal X, Y: std_logic; X <= A and B; Y <= (not A) and (not B); Z <= X or Y; End concurrent; entity XNOR2 is port (A, B: in std_logic; Z: out std_logic); end XNOR2; architecture sequential of XNOR2 is XNOR2 : Process (A,B) if ((A = 0 and B = 0 ) (A = 1 and B = 1 )) then Z <= 1 ; else Z <= 0 ; end if; end process XNOR2; end sequential;

Skills check Out1? architecture... process ( ) OUT1 <= A ; OUT1 <= B ;... end process ; end architecture ; The last assignment takes effect architecture... OUT1 <= A ; OUT1 <= B ;... end architecture ; Some form of resolution is required for the output signal OUT1

Don t forget Concurrent statements (Default) Executed in parallel With select When else Process statements Generate statements Sequential statements (within Process) Executed in sequence If statement Case statement loop statement Wait statement Note : Sequential statements must be used within process

Assignment Write VHDL code for 3X8 Decoder? Write VHDL code for 3X8 Encoder? What is the difference between std_logic and std_ulogic data types? Prepare yourself for a quick test?

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