Jae Wook Lee. SIC R&D Lab. LG Electronics

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Transcription:

Jae Wook Lee SIC R&D Lab. LG Electronics

Contents Introduction Why power validation on mobile application processor? Then, what to validate? Who is in charge of validation? Power Validation Components of power Lower power techniques and validation challenge Type of power debugging Why leakage power became so important? Scenario power Low power validation essentials Correlation effort High volume manufacturing Summary

Why are we validating power on mobile AP? Heat Sink, Cooling Fan [Source: http://anandtech.com] [Source: http://www.embedded.com/design/mcus-processors-and-socs] Cooling fan inside a mobile phone? Maximum power consumption on a mobile phone < several watts

Why are we validating power on mobile AP? Skin surface temperature while using a mobile phone Users want longer battery life! [Source: http://www.eetimes.com/document.asp?doc_id=1279666] [Source: http://thebestsmartphones.org/iphone/the-iphone-5-review/]

Then, what to validate? Various low power techniques are used when mobile AP are developed. [Source: http://www.synopsys.com/company/publications/synopsysinsight/pages/art4-low-power-issq2-12.aspx]

Who is in charge of validation? Previously, one person, but now a team is needed with a good collaboration. [Source: http://www.synopsys.com/company/publications/synopsysinsight/pages/art4-low-power-issq2-12.aspx]

Components of power Power = Static Power + Dynamic Power (+Short Circuit Power) Major leakage components - Gate tunneling leakage - Sub-threshold leakage - Junction leakage Dynamic power - Charging/discharging Short circuit power - Shoot-through power [Source: http://electronicdesign.com/power/understanding-low-power-ic-design-techniques] So, expecting simple validation?

Low-power techniques and validation challenge Multi-Vt optimization Leakage power PG, DVFS Scenario power, DVFS, Minimum Vdd [Source: http://www.tela-inc.com/products/poweroptimization/leakage-speed-tradeoffs/] Low Vdd Standby Power management, PG [Source: http://soccentral.com/results.asp?catid=488&entryid=25950] MCMM Scenario power, Dynamic power [Source: http://www.pcworld.com/article/2010642/meet-clover-trailintels-chip-for-mid-range-windows-8-tablets-and-hybrids.html] [Source: http://low-powerdesign.com/article_mentor_narayananjilla.htm]

Type of power debugging Leakage power validation Block (CPU, GPU, ISP, PLL, SRAM, etc.) Power-gating efficiency SoC Dynamic power validation In-house power-virus Industrial standard power-virus: i.e. Dhrystone Benchmark tests DVFS (Dynamic Voltage and Frequency Scaling) validation Adaptive/Dynamic voltage scaling considering process variation Scenario power validation including idle/stand-by power validation IR-drop/PMIC-droop validation Low-power validation, power-management validation, etc.

Why leakage power becomes so important? We cannot disregard leakage power any more! Leakage current has a strong dependency on Voltage Temperature Process [Source: http://www.eetimes.com/] Leakage power while enjoying a game? Voltage condition in DVFS scheme? Necessitates power-gating with multiple power domains low leakage cells for non-critical paths good power-management in both AP and S/W

Why leakage power becomes so important? Leakage current is a good indicator of process along with Vth in power and performance optimization process tuning improving yield or reducing test cost Leakage (in log scale) Performance (1/Vth)

Type of power debugging DVFS/DVS/AVS [Source: http://www.cadence.com/community/blogs/lp/archive/2010/08/24/dynamic-power-management-closed-loop-voltage-scaling.aspx] Open-loop scaling requires statistical silicon data using a tester safe margin from coarse granularity Closed-loop scaling validating HPM better optimization [Source: http://www.eetimes.com/document.asp?doc_id=1202563]

Power Scenario power validation 3G Talk, Web browsing, Camera burst-shot, Idle, 1080p playing, etc. Usage Case 1 Usage Case 2 Usage Case 3 Usage Case 4 Usage Case 5 Usage Case 6

Low power validation essentials Debugging tools/environment Thermal control Understanding DFT, clock network, and power management Measurement technique [Source: http://www.extremetech.com/extreme/166413-post-postpc-the-new-materials-tech-and-cpu-designs-that-will-reviveoverclocking-and-enthusiast-computing] Statistical analysis [Source: http://www.semiwiki.com/forum/content/405-moore%92s-law-semiconductordesign-manufacturing.html]

Correlation effort Correlation among three parties are essential in early validation stage Degree of confidence Various benchmarks and usage scenario vs. volume data Power Management/Power Estimation Design Kit/Platform board Production Tester/ATE [Source: http://www.logicbricks.com] [Source: http://www1.verigy.com/ate]

High volume manufacturing How to guarantee the power consumption of each AP? Killing/Screening parts: When? Yield? Proper test contents with good correlation Volume data analysis Dynamic Voltage and Frequency Scaling support Test hole/escape between HVM and system board test Test time is also important! [Source: http://anandtech.com/show/5365/intels-medfield-atom-z2460-arrive-for-smartphones]

Summary Validating power in mobile AP becomes important, especially leakage power Validating low-power features/techniques and MMMC (Multi-mode multicorner) is always challenging Analog value, not pass/fail: many of iterations Statistical analysis for better judgment become essential Improving power estimation accuracy/confidence in defining a new project