Review: Abstract Implementation View

Review: Abstract Implementation View Split memory (Harvard) model - single cycle operation Simplified to contain only the instructions: memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and, or, slt control flow instructions: beq, j PC Register Reg r File Reg r Reg r Data Data Data Data Sequential components (PC, RegFile, ) are edge triggered state elements are written on every clock cycle; if not, need explicit write control signal - write occurs only when both the write control is asserted and the clock edge occurs 33 Lec 4. Fall 22

Example Let s modify the ISA and remove the ability to specify an offset for memory access instructions. Specifically, the load-store instructions would contain only two registers. In other words, all MIPS load-store instructions with offsets would become pseudoinstructions and would be implemented using two instructions: lw $t, 4($t) => 33 Lec 4.2 Fall 22

Example cont d control 6-bit offset 8 7 7 r Register r 2 Data File Write r Data 2 overflow zero Data Data Sign 6 Extend 32 Mem 33 Lec 4.3 Fall 22

Creating a Single Datapath from the Parts Assemble the datapath segments from the last lecture, add control lines as needed, and design the control path Fetch, decode and execute each instructions in one clock cycle single cycle design no datapath resource can be used more than once per instruction, so some must be duplicated (e.g., why we have a separate and Data ) to share datapath elements between two different instruction classes will need multiplexors at the input of the shared elements with control lines to do the selection Cycle time is determined by length of the longest path 33 Lec 4.4 Fall 22

Fetch, R, and Access Portions PC 4 lw r Register r 2 Data File Write r Data 2 R control ovf zero lw / sw Data Data R Sign 6 Extend 32 Mem 33 Lec 4.5 Fall 22

Multiplexor Insertion PC 4 r Register r 2 Data File Write r Data 2 Src control ovf zero Data Data Sign 6 Extend 32 Mem 33 Lec 4.6 Fall 22

ing the Branch Portion Branch not taken, R, lw /sw PC 4 r Register r 2 Data File Write r Data 2 R Sign 6 Extend 32 Shift left 2 Src lw / sw control ovf zero PCSrc Data Data Mem lw R 33 Lec 4.7 Fall 22

ing the Selecting the operations to perform (, Register File and read/write) ling the flow of data (multiplexor inputs) Information comes from the 32 bits of the instruction Observations R-type: 3 25 2 5 5 op rs rt rd shamt funct op field always in bits 3-26 3 25 2 5 I-Type: op rs rt address offset addr of two registers to be read are always specified by the rs and rt fields (bits 25-2 and 2-6) addr. of register to be written is in one of two places in rt (bits 2-6) for lw; in rd (bits 5-) for R-type instructions base register for lw and sw always in rs (bits 25-2) offset for beq, lw, and sw always in bits 5-33 Lec 4.8 Fall 22

(Almost) Complete Single Cycle Datapath 4 Shift left 2 PCSrc Src PC Instr[3-] Instr[25-2] Instr[2-6] Instr[5 -] r Register r 2 Data File Write r Data 2 ovf zero Data Data Instr[5-] Sign 6 Extend 32 control Mem Instr[5-] Op 33 Lec 4.9 Fall 22

's operation based on instruction type and function code control input (Binvert + Operation) Function and or add subtract set on less than 33 Lec 4. Fall 22

, Con t ling the makes use of multiple levels of decoding main control unit generates the Op bits control unit generates control inputs Instr op funct Op desired action control input lw xxxxxx sw xxxxxx beq xxxxxx add add subt subtract and and or or slt slt 33 Lec 4. Fall 22

33 Lec 4.2 Fall 22 Truth Table F F F2 F3 F4 F5 Op Op Op Op Op2 Can make use of more don t cares since Op does not use the encoding since F5 and F4 are always Logic comes from the K-maps

Combinational Logic From the truth table can design the logic Op control block Op Op F3 Operation2 F (5 ) F2 F F Operation Operation Operation 33 Lec 4.3 Fall 22

(Almost) Complete Datapath with Unit 4 Op Instr[3-26] Unit Branch Src Shift left 2 PCSrc Mem PC Instr[3-] Instr[25-2] Instr[2-6] Instr[5 -] r Register r 2 Data File Write r Data 2 ovf zero Data Data Instr[5-] Sign 6 Extend 32 control Instr[5-] 33 Lec 4.4 Fall 22

R-type Data/ Flow 4 Instr[3-26] Op Unit Branch Src Shift left 2 PCSrc Mem PC Instr[3-] Instr[25-2] Instr[2-6] Instr[5 -] r Register r 2 Data File Write r Data 2 ovf zero Data Data Instr[5-] Sign 6 Extend 32 control Instr[5-] 33 Lec 4.5 Fall 22

Store Word Data/ Flow 4 Op Instr[3-26] Unit Branch Src Shift left 2 PCSrc Mem PC Instr[3-] Instr[25-2] Instr[2-6] Instr[5 -] r Register r 2 Data File Write r Data 2 ovf zero Data Data Instr[5-] Sign 6 Extend 32 control Instr[5-] 33 Lec 4.6 Fall 22

Load Word Data/ Flow 4 Op Instr[3-26] Unit Branch Src Shift left 2 PCSrc Mem PC Instr[3-] Instr[25-2] Instr[2-6] Instr[5 -] r Register r 2 Data File Write r Data 2 ovf zero Data Data Instr[5-] Sign 6 Extend 32 control Instr[5-] 33 Lec 4.7 Fall 22

Branch Data/ Flow 4 Op Instr[3-26] Unit Branch Src Shift left 2 PCSrc Mem PC Instr[3-] Instr[25-2] Instr[2-6] Instr[5 -] r Register r 2 Data File Write r Data 2 ovf zero Data Data Instr[5-] Sign 6 Extend 32 control Instr[5-] 33 Lec 4.8 Fall 22

Main Unit Instr Src MemReg RegWr MemRd MemWr Branch Op Op R-type lw sw beq 33 Lec 4.9 Fall 22

Unit Logic From the truth table can design the Main logic Instr[3] Instr[3] Instr[29] Instr[28] Instr[27] Instr[26] R-type lw sw beq Src Mem Branch Op Op 33 Lec 4.2 Fall 22

ing the Jump Operation 4 Instr[25-] 26 Op Instr[3-26] Shift left 2 Unit 28 Branch 32 PC+4[3-28] Jump Src Shift left 2 PCSrc Mem PC Instr[3-] Instr[25-2] Instr[2-6] Instr[5 -] r Register r 2 Data File Write r Data 2 ovf zero Data Data Instr[5-] Sign 6 Extend 32 control Instr[5-] 33 Lec 4.2 Fall 22

Single Cycle Implementation Cycle Time Unfortunately, though simple, the single cycle approach is not used because it is inefficient Clock cycle must have the same length for every instruction What is the longest path (slowest instruction)? 33 Lec 4.22 Fall 22

Critical Paths Calculate cycle time assuming negligible delays (for muxes, control unit, sign extend, PC access, shift left 2, wires) except: and Data (2ns) and adders (2ns) Register File access (reads or writes) (ns) Instr. I Mem Reg Rd Op D Mem Reg Wr Total R-type 2 2 6 load 2 2 2 8 store 2 2 2 7 beq 2 2 5 jump 2 2 33 Lec 4.23 Fall 22

Where We are Headed Problems with single cycle datapath design uses clock cycle inefficiently and what if we had a more complicated instruction like floating point multiply? wasteful of area Another approach use a smaller cycle time have different instructions take different numbers of cycles a multicycle datapath: PC Data (Instr. or Data) IR MDR r Register r 2Data File Write r Data 2 A B out 33 Lec 4.24 Fall 22

Complete Datapath 4 Instr[25-] 26 Op Instr[3-26] Shift left 2 Unit 28 32 PC+4[3-28] Branch Jump Src Shift left 2 PCSrc Mem PC Instr[3-] Instr[25-2] Instr[2-6] Instr[5 -] r Register r 2 Data File Write r Data 2 ovf zero Data Data Instr[5-] Sign 6 Extend 32 control Instr[5-] 33 Lec 4.25 Fall 22

Example I: R instruction Signal Setting Signal Setting Op Jump AlUOp Branch Mem Src 33 Lec 4.26 Fall 22

Example I: lw instruction Signal Setting Signal Setting Op Jump AlUOp Branch Mem Src 33 Lec 4.27 Fall 22

Example I: sw instruction Signal Setting Signal Setting Op Jump AlUOp Branch Mem Src 33 Lec 4.28 Fall 22

Example I: beq instruction Signal Setting Signal Setting Op Jump AlUOp Branch Mem Src 33 Lec 4.29 Fall 22

Example II: cycle length Calculate cycle time assuming negligible delays (for muxes, control unit, sign extend, PC access, shift left 2, wires) except: and Data (2ns) (2ns) Register File access (reads or writes) (ns) er for PC+4 (5ns) er for branch address computation (5ns) 33 Lec 4.3 Fall 22

Example III: Describe the effect that a single stuck-at- fault (I.e., regardless of what it should be, the signal is always ) would have on the multiplexors in the single-cycle datapath. Which instruction, if any, would still work? Consider each of the following faults separately: =, Src =, =, Zero = ; 33 Lec 4.3 Fall 22

Example IV: We wish to add the instruction addi to the singlecycle datapath. any necessary datapaths and control signals. Signal Setting Signal Setting Op Jump AlUOp Branch Mem Src 33 Lec 4.32 Fall 22

Complete Datapath 4 Instr[25-] 26 Op Instr[3-26] Shift left 2 Unit 28 32 PC+4[3-28] Branch Jump Src Shift left 2 PCSrc Mem PC Instr[3-] Instr[25-2] Instr[2-6] Instr[5 -] r Register r 2 Data File Write r Data 2 ovf zero Data Data Instr[5-] Sign 6 Extend 32 control Instr[5-] 33 Lec 4.33 Fall 22

Example V: add jal 4 Instr[25-] 26 Op Instr[3-26] Shift left 2 Unit 28 32 PC+4[3-28] Jump Branch Src Shift left 2 PCSrc Mem PC Instr[3-] 3 Instr[5 -] Instr[25-2] Instr[2-6] r Register r 2 Data File Write r Data 2 ovf zero Data Data Instr[5-] Sign 6 Extend 32 control Instr[5-] 33 Lec 4.34 Fall 22

Example V: add jal (cont d) Signal Setting Signal Setting Op Jump AlUOp Branch Mem Src 33 Lec 4.35 Fall 22