Users Guide: Fast IP Lookup (FIPL) in the FPX Gigabit Kits Workshop /22 FIPL System Design Each FIPL Engine performs a longest matching prefix lookup on a single 32-bit IPv4 destination address FIPL Engine Controller scales to required lookup throughput with minimal hardware resource usage Instantiate required number of parallel lookup engines 4 engines in current configuration (2.4 Gb/s link) Pipeline memory accesses FIPL Wrapper Buffers packets Supports up to 4 virtual ports Control Processor Handles data structure updates PP TI Switch Fabric PP TI CP Physical Links TI FIPL Engine Controller FIPL Engine FIPL Engine FIPL Wrapper Packet I/O SRAM Interface Control Processor Packet I/O
Design Overview SRAM Extract IP Headers Request Grant SRAM Interface Remap VCIs for IP packets IP Lookup Engine counter On-Chip Cell Store SRAM 2 Packet Reassembler RAD FPGA Control Cell Processor LC NID FPGA SW Performance Evaluation Used gate-level simulation with ModelSim MHz system clock Configured a FIPL Engine Controller to enable one to eight FIPL engines based on the contents of a control cell Initialized tree bitmap data structure with 6,564 entries from the Mae-West routing table (July 2, 2 snapshot) Measured lookup latency and throughput for test sequences of 248 random destination addresses Addresses stored in on-chip memory read by FIPL Engine Controller Measured lookup latency and throughput for various update loads 2
Throughput and latency performance Millions of lookups per second 9 8 7 6 5 4 3 2 Theoretical Worst-case Throughput Mae West Throughput Theoretical Worst-case Avg. Lookup Latency Mae West Avg. Lookup Latency 2 3 4 5 6 7 8 #offiplengines 9 8 7 6 5 4 3 2 Average Lookup Latency (ns) Update performance Millions of lookups per second 9 8 7 6 5 4 3 2, updates per second, updates per second, updates per second No updates 2 3 4 5 6 7 8 #offiplengines 3
Performance on WU Research Platform Based on results, a 4 engine configuration was targeted to the WUGS/FPX research platform Sustained.988 Gb/s throughput on single-cell packets = 4.7 M packets/sec Limited by 2 Gb/s switch interface of FPX (32-bit at 62.5 MHz) Verified using bandwidth monitoring software, the cell multiplying feature of the WUGS, and four traffic sources sending at different rates with corresponding 24-bit prefix entries in the route table Utilizes only 8% of available logic resources and 2.5% of onchip memory resources 4 FIPL Engines and FIPL Engine Controller utilizes 6% of logic resources FIPL Wrapper utilizes 2% of logic resources and 2.5% of on-chip memory resources Current Work: MSR Integration SRAM Updates CCP Register Set Updates & Status DQ Status & Rate Control Control Path Data Path SRAM Register Set SRAM AAL LC SW Pkt-ptr Shim Header ISAR Mgmt Filters FIPL Hdr update Ref. counter Discard pkt. Packet Storage Manager (includes free space list) Q-Mgr OSAR O-SW AAL5 LC SW SDRAM SDRAM 4
Default FIPL Configuration Current FIPL Wrapper configured for future MSR integration (all parameters modifiable via control cell) Listens for IP traffic on 4 sub-ports (SP SP3) Sub-port VCI determined by an input base VCI (Ibase_VCI) and a sub-port index (SPI) Sub-port VCI = Ibase_VCI + SPI Defaults: Ibase_VCI = x8 (28) SP=,SP=,SP2=2,SP3=3 SP_VCI = x8 (28), SP_VCI = x8 (29), Similar operation for outgoing VC resolution For current use, explicitly specify outgoing VCI as Next Hop References Scalable IP Lookup for Programmable Routers,, John W. Lockwood, Todd Sproull, Jonathan S. Turner, David B. Parlour, WUCS--33, /. Generalized RAD Module Infrastructure of the Field Programmable Port Extender (FPX) Version 2.,, John W. Lockwood, Naji Naufel, WUCS-TM--6, 7/. Generalized RAD Module Interface Specification of the Field Programmable Port Extender (FPX) Version 2.,, John W. Lockwood, Sarang Dharmapurikar, WUCS-TM--5, 7/. FPX Website: www.arl.wustl.edu/arl/projects/fpx 5
FIPL Switch Initialization FIPL Switch Initialization Switch Configuration -> GBNSC Restart Switch Configuration -> Switch Reset Switch Configuration -> Configure all VCIs Switch Configuration -> Set ALL ports to Hardware Mode Switch Configuration -> Configure a Unidirectional VC Incoming Port: 3 Incoming VC: 28 Outgoing Port: 2 Outgoing VC: 28 Switch Configuration -> Configure a Unidirectional VC Incoming Port: 2 Incoming VC: 54 Outgoing Port: 3 Outgoing VC: 54 Switch Configuration -> Configure a Unidirectional VC Incoming Port: 2 Incoming VC: 55 Outgoing Port: 3 Outgoing VC: 55 6
FIPL Control Software FPX Applications Start Application NCHARGE on all ports FPX Applications Start Application FIPL Memory Manager (Port 2, Stack ) FIPL Upload bitfile Download rad_fipl_msr.v2e.cclk.bit from: http://www.arl.wustl.edu/~det3/talks/ Save to Desktop FPX Applications Upload a file: Browse to Desktop and select file 7
FIPL Programming the RAD Configuration Memory Updates Complete Configuration (filename given after upload) FIPL Adding Routes Fast IP Lookup -> Route Add IP Address:.22.33.44 Net Mask: 24 Next Hop: 54 8
FIPL Sending Test Packets () Create Cells IPv4 IP Address:.22.33.44 Protocol: 4 TTL: 255 VCI: 28 Random Data Create Cell Receive on 54 FIPL Sending Test Packets (2) 9
Route Modify and Delete Modify Route.22.33.44/24 55 Create Cell.22.33.44 (transmit on 28) Receive on 55 Receive on 54 (should timeout, no cell received) Add Route.22.55.66/6 54 Create cell.22.33.44 Should still receive on 55 (not 54) Delete Route.22.33.44/24 Create cell.22.33.44 Should now receive on 54