Novel Hardware Architecture for Fast Address Lookups

Transcription

1 Novel Hardware Architecture for Fast Address Lookups Pronita Mehrotra Paul D. Franzon Department of Electrical and Computer Engineering North Carolina State University This research is supported by

2 Outline Background & Motivation Description of the Scheme Example for a 1-way Implementation Building SRAM/DRAM data Searching an address Hardware Implementation of the Scheme Performance Memory Consumption Conclusions 1

3 Background Optical Burst Switching Using Just In Time protocol OBS Edge Node OBS Switch OBS Switch OBS Edge Node MCNC/NCSU project OBS Switch OBS Switch CALLING HOST CALLING SWITCH CALLED SWITCH CALLED HOST SETU P OBS Edge Node Network Core Switches SETUP ACK SETUP CROSSCONNECT CONFIGURED RELEASE OPTICAL BURST SETUP CONNECT My group Network Processor for OBS.. CROSSCONNECT CONFIGURED FOR EXPLICIT RELEASE CONNECT CONNECT RELEASE

4 Network Processor Architecture JIT Message Engine Register Access Block STAGE 1 STAGE STAGE STAGE 4 STAGE ME-In Controller STAGE STAGE 8 ME-Out Controller CRC Checker ACK/NACK Generator Input Message Buffer 8 Input Port Message Parser Port Assignment Forwarding Engine Forwarding Engine Field Update Module Connection State Checker Output Port Requester Message Reassembly CRC Generator Output Message Buffer Data Bus Request Buffer Output Data Register 8 Request Arbiter Output Port

5 Motivation The bottleneck of the forwarding engine is the route lookup Speed Reduce the number of lookups esp. in main memory icurrent routing tables have over 100,000 entries Store in DRAMs idram random accesses are slow ( 0-ns) Scalability Reduce the amount of memory required to store data itree Based Schemes most efficient Applies to all routers, not just OBS 4

6 Motivation Content Addressable Memories (CAMs) are still not large enough for large routing tables Current CAM sizes 1MB Multiple CAMs need to be used in the design Cost of CAMs is still high compared to DRAMs MB of DRAM costs $0 1MB of T-CAM costs $00

7 Problem Definition Routers store prefixes and not IP addresses To determine the next hop, the longest matching prefix needs to be determined Example: Destination address = , 1011, all match Longest prefix match is Next hop address = Prefix Next Hop

8 Proposed Scheme using Compaction Since DRAM accesses are fairly expensive, limit the number of DRAM accesses The next hop information is needed only once the trie has been traversed fully Separate the data (next hops) from the trie-path information An on-chip SRAM can store a representation of the trie to allow fast traversals The off-chip DRAM contains the next hop addresses which is required only once at the end

9 Proposed Scheme Using Compaction Store path information in a smaller ( 0x than forwarding table), faster, wide on-chip SRAM Few SRAM and one DRAM lookups Compact Trie node/path information: 1 node has child 0 leaf node A lookup can be done every 0-ns (14-1 million lookups per second) 8

10 Simplified Example Tree SRAM data Example: Address = DRAM data stop DRAM row = # 1s encountered (row 1) DRAM col = Output port = 4

11 Proposed Scheme Using Compaction On-chip SRAM and Off-chip DRAM A wide on-chip SRAM For 40,000 prefixes in the routing table, the required SRAM size is less than 0kB sets of these memories can be used to hide the update operations iupdates performed via embedded CPU Pipelined SRAM and DRAM operation Only 1 DRAM lookup in all cases One lookup can be done every 0-ns 14-1 million lookups per second Multiple DRAMs can be used to increase the lookup rate 10

12 Example for a 1-way Implementation Prefix Length Next Hop Prefix Length Next Hop Sorting The entries are first sorted in ascending order Each entry is read and expanded (for trie completion) and added to the trie structure Breadth first search of the trie structure is done to generate the SRAM data 11

13 Example: Building the Trie 1 Prefix Next Hop

14 Example: Building SRAM data x x x x x x x x

15 14 SRAM and DRAM contents SRAM and DRAM contents Level 0 Bit Pattern Sum 0x0000 0x0000 0x0000 0x8000 0x0008 0x0000 0x80 0x0000 0x1000 0x8000 0x0000 0x0000 0x0000 Level 1 Level Level SRAM Contents DRAM Contents The 1 corresponding to the root node is neglected while building the SRAM data Breadth-first search is performed to generate the bit pattern 1

16 Example: Searching the Trie Input Address: ( ) ( ) 0x Level 0 Sum of 1 s = ( ) 0x0000 0x0000 0x x8000 Level 1 Sum of 1 s = 0 1

17 1 Example: Searching the Example: Searching the Trie Trie Level 0x x8000 ( ) Sum of 1 s = 0 Level 0x x0000 ( ) Total number of 1 s before and including the 1 in level gives the DRAM row number where the next hop addresses are stored In our case row = Column = 0000 DRAM data 1

18 Hardware Implementation address Bit Extraction Mask Generation Sum Of 1 s DRAM On-Chip SRAM CPU To generate the mask, a decoder followed by a cross-bar like circuit is used E.g. Address Field = 0010 Mask = E.g. Address Field = 0011 Mask = Sum of 1 s is done using a bank of adders 1

19 Hardware Implementation Traversal in SRAM is further pipelined into two stages (for a 1-way implementation) Traverse Level 1-4 in SRAM Traverse Level -8 in SRAM Read Next Hop From DRAM 4ns 4ns 4ns Each traversal in SRAM goes through two stages Extract bits and read the SRAM row Generate Mask and Compute the sum of 1 s Each stage takes under 8ns to give a total traversal time of 1ns Extract bits, Read SRAM Generate Mask, Sum of 1 s 18

20 Memory Requirement Site Entries SRAM (KB) DRAM (MB) Trie Memory (MB) Bytes per entry MaeEast, MaeWest, PacBell, Paix 1, AADS 1, For a 1-way implementation: Amount of SRAM is about 1 byte per entry for all routing tables About 00x reduction in memory from SRAM to DRAM Average Bytes/Entry = M/ln(M), where M is the degree of the trie 1

21 Memory Requirement for different degrees Site Degree = 1 Degree = 8 Degree = 4 Degree = SRAM (KB) DRAM (MB) SRAM (kb) DRAM (MB) SRAM (kb) DRAM (MB) SRAM kb) DRAM (MB) MaeEast MaeWest PacBell Paix AADS Efficiency of memory consumption increases as the degree of the trie decreases Less wastage during trie completion Total latency would increase with smaller degree as more SRAM accesses required 0

22 Conclusions Proposed a trie-based routing scheme using compaction SRAM stores a representation of the trie and is used only for trie traversal ismall on-chip SRAM ( KB for >0,000 entries) Off chip DRAM stores next hop information ionly one DRAM access is required The throughput is limited by the random access time of the DRAM i14-1 million lookups per second Multiple/Multibank DRAMs allow further improvement Implemented and tested in hardware FPGA & ASIC ie.g. 0. sq.mm. of logic in 0. µm process 1