Universität Dortmund. IO and Peripheral Interfaces

IO and Peripheral Interfaces

Microcontroller System Architecture Each MCU (micro-controller unit) is characterized by: Microprocessor 8,16,32 bit architecture Usually simple in-order microarchitecture, no FPU Memory RAM (from 512B to 256kB) FLASH (from 512B to 1MB) Peripherals DMA Timer Interfaces Digital Analog Interconnect AHB system bus (ARM-based MCUs) APB peripheral bus (ARM-based MCUs) Example: STM32F101 MCU

MCU Interfaces Digital Several protocols for inter-chip communication Serial communication protocols UART, I 2 C, SPI, USB, Meant for short distances inside the box / on-board Low complexity Low cost Low speed ( a few Mb/s at the fastest ) Serial communication is employed where it is not practical, either in physical or cost terms, to move data in parallel between systems.

Memory-Mapped Peripherals Peripherals such as external interfaces in a microcontroller system are accessible via memory-mapped registers: for peripheral configuration for I/O addresses Memory Map Cortex-M3 MCU core memory mapped load/store

Memory-Mapped Peripherals Suppose our purpose is to blink a LED (i.e., a GPIO pin): GPIOC_LED0_ADDR

Memory-Mapped Peripherals Suppose our purpose is to blink a LED (i.e., a GPIO pin): STORE GPIOC_LED0_ADDR,0x1 GPIOC_LED0_ADDR

Microcontroller External Pins Configuration MCUs are often pin-limited Not enough I/O pins for all I/O peripherals and functions! Pins have to be multiplexed (shared) between peripherals and functions Most pins can be configured for several functions: As input or output pin As an interrupt pin Setup a pull-up / pull-down internal resistor (NO floating pins!) Assigned as general-purpose I/O (GPIO) or to a specific peripheral Digital peripherals such as UARTs, SPIs, I2Cs Analog peripherals such as ADCs or DACs

Microcontroller External Pins Configuration Example to understand how this functionality works in a MCU the specific circuit and register may change wildly between MCUs Memory-Mapped registers Function Select Register PxSEL Interrupt Edge Select Register PxIES Interrupt Enable Register PxIE Interrupt Flag Register PxIFG Direction Register PxDIR PAD 1 Output Register PxOUT Input Register PxIN 7 6 5 4 3 2 1 0

Digital (Serial) Interfaces

UART

UART - 1 Stands for Universal Asynchronous Receiver- Transmitter sometimes also found as USART (Universal Synchronous- Asynchronous Receiver Transmitter) Used to interface MCUs with other computing devices: Communication with other processors, a PC (e.g. a serial terminal) Used to interface the microcontroller with others transmission bus as: RS232, RS485, USB, CAN BUS, KNX, LonWorks ecc. Used to connect MCUs with modems and transceivers as telephone modems, Bluetooth, Wi-Fi, GSM/GPRS/HDPSA

UART - 2 Essentially a parallel2serial (TX), serial2parallel (RX) converter couple e.g. using shift registers for P2S conversion Asynchronous: no common clock shared Each device has its own local clock, typically running faster than the bit rate (e.g. 8x faster) The phase of the receiver clock is locked onto the edge of the transmitted data Highly configurable parity / no parity data framing (e.g number of stop bits, number of payload bits) simplex, full-duplex or half-duplex

UART: baud rate vs bit rate UART communication speed is defined by its symbol rate measured in baud: 1 baud = 1 symbol per second in UART, a symbol has two values (0/1) -> 1 bit this number includes both data payload and protocol bits (e.g. parity, framing) this number is also called physical or gross bit rate Ref. Wikipedia Bit rate page This can cause some confusion Some people use bit rate for UART when referring only to payload bits In some devices (e.g. modems) one symbol might correspond to more bits - > baud rate is not the same as gross bit rate Bottom line: to be 100% clear, always talk of baud rate when referring to UART, and remember that in UART 1 symbol = 1 bit

UART: Interface Protocol 1. In idle, the transmission line is driven to 1

UART: Interface Protocol 1 start bit 2. The transfer begins with a start bit: the transmission line is driven to 0

UART: Interface Protocol 1 start bit 5-9 data bits 2. Then, a symbol of 5 to 9 bits is transmitted: most often, 8 bits (1 ASCII character) the symbol size is defined by the application and known a-priori with respect to the communication

UART: Interface Protocol 1 start bit 4-8 data bits 1 parity bit 3. One of the data bits can be used for parity: odd parity even parity in this case, 4-8 bits can be used for data

UART: Interface Protocol 1 start bit 4-8 data bits 1 parity bit 1-2 stop bits 4. Finally, 1-2 stop bits: Transmission line brought back to 1 1 or 2 stop bits depending on application

UART: Parity bit A parity bit, or check bit is a bit added to the end of a string of binary code that indicates whether the number of bits in the string with the value one is even or odd. Parity bits are used as the simplest form of error detecting code. There are two variants of parity bits: even parity bit and odd parity bit. In the case of even parity, for a given set of bits, the occurrences of bits whose value is 1 is counted. If that count is odd, the parity bit value is set to 1, making the total count of occurrences of 1's in the whole set(including the parity bit) an even number. If the count of 1's in a given set of bits is already even, the parity bit's value remains 0. In the case of odd parity, the situation is reversed. For a given set of bits, if the count of bits with a value of 1 is even, the parity bit value is set to 1 making the total count of 1's in the whole set(including the parity bit) an odd number. If the count of bits with a value of 1 is odd, the count is already odd so the parity bit's value remains 0. Even parity is a special case of a cyclic redundancy check (CRC), where the 1-bit CRC is generated by the polynomial x+1.

UART: Handshake The UART protocol can also include a handshake: request-to-send (RTS) signal from the MCU to the device means that the MCU can accept new data clear-to-send (CTS) signal from the device to the MCU means that the device can send new data signals have dual meaning if seen from the other point of view exchange happens when CTS and RTS are both asserted

UART or USART? UART = Universal Asynchronous Receiver Transmitter USART = Universal Synchronous Asynchronous Receiver Transmitter A USART can act in Asynchronous mode just like a UART. But it has the added capability of acting Synchronously. This means that the data is clocked. The clock is either recovered from the data itself or sent as an external signal. Asynchronous Serial Transmission data transmitted without having to send a clock signal: special bits added to each word to synchronize the sending and receiving units. No extra-wire needed extra bits typically added Start Bit, Stop Bit, Parity Bit Data rate typically fixed in agreement sender / receiver Synchronous Serial Transmission requires that the sender and receiver share a clock, i.e. the sender provides a clock or other timing signal so that the receiver knows when to read the next bit of the data. data is sent on one wire while a clock is sent on a different wire. It is usually more efficient because only data bits are transmitted between sender and receiver rather than extra bits like start bit, stop bits, etc.

UART or USART? UART UART requires only data signal In UART, data is normally transmitted one byte at a time. USART In USART, synchronous mode requires both data and a clock. In USART, synchronous data is normally transmitted in the form of blocks. In UART, data transfer speed is set around specific values like 4800, 9600, 38400 bps,etc. UART speed is limited around 115200 bps Full duplex Synchronous mode allows for a higher DTR (data transfer rate) than asynchronous mode does, if all other factors are held constant. USART is faster than 115kb Half duplex

I2C

I2C: Inter-Integrated Circuit Bus - 1 Usually pronounced I-Squared-C Introduced by Philips (now NXP Semiconductors) in 1982 Used for communication with external peripherals, for example: EEPROMs thermal sensors real-time clocks Also used as a control interface for signal processing devices with separate data interfaces, for example: radio frequency tuners video decoders and encoders audio processors

I2C: Inter-Integrated Circuit Bus - 2 Three supported speed modes: slow (under 100 Kbps) fast (400 Kbps) high-speed (3.4 Mbps) in I 2 C v.2.0 Maximum inter-ic distance of about 3 meters (for moderate speeds, less for high-speed) Can support multi-master mode For complex applications Communication is always started by a master, both in singlemaster and multi-master mode Half-duplex synchronous communication scheme the master of the communication generates the clock (SCL) on which data (SDA) is synchronized

I2C: Inter-Integrated Circuit Bus - 3 Based on two lines: SCL (serial clock) SDA (serial data) Pull-Up resistors, Pull-Down by open-drain drivers Wired-AND: if any driver pulls down, the line is low (avoids short circuits) Any module on the bus can act as master, slave or both typical case: MCU is the master, peripherals/sensors are slaves

I2C: Interface Protocol In idle, both SCL and SDA are pulled-up to 1

I2C: Interface Protocol 1. To start the communication, the master: asserts the start bit (SDA 1 0 transition while SCL is still 1) then, it starts generating the SCL clock except for the start and stop bits, SDA transitions only when SCL is 0

I2C: Interface Protocol 2. The master transmits the slave address: broadcasted to all devices on the I 2 C bus used to select the target slave either 7 bits or 10 bits (newer devices 7 bits address space is small!) in the example, the address is 7 b1000001

I2C: Interface Protocol 3. The master transmits a direction bit: a 0 for master slave (write) transfer a 1 for slave master (read) transfer in the example, suppose a write transfer

I2C: Interface Protocol 4. The slave then acknowledges reception: by driving SDA to 0 if not acknowledged, the transaction must be repeated by the master

I2C: Interface Protocol 5. The master transmits its data payload: each payload packet is 8 bits there might be more than one packet, depending on application in the example, data payload is 8 b00110100

I2C: Interface Protocol 6. The slave acknowledges reception of the data packet: 1 ack bit every 8 payload bits slave must acknowledge each packet

I2C: Interface Protocol 7. At the end of the transfer, the master transmits a stop bit: first, it sets SDA to 0 then it releases SCL (i.e. it lets it go to 1) finally, it releases SDA which also goes to 1

I2C: Interface Protocol Reads work similarly, but data transfer ack roles are reversed: the slave drives SDA when transmitting the data byte the master acknowledges the transfer

I2C: Clock Stretching Slave can ask for more time to process a bit by clock stretching: drive SCL to 0 if in need of more processing time

SPI

SPI: Serial Peripheral Interface - 1 Introduced by Motorola (now Freescale Semiconductors) for the MC68HCxx line of microcontrollers Use cases are generally similar to I 2 C Generally faster than I 2 C (up to several Mbit/s) Short-distance (i.e. on printed circuit boards) Single-master, multiple slave needs one chip select per slave device (no broadcast addressing) Full-duplex synchronous communication scheme master drives the clock (SCLK or SCK) clock polarity (i.e. write/read edges) and phase depend on specific application!

SPI: Serial Peripheral Interface - 2 Based on two data and two control lines: MISO (master-in, slave-out data) MOSI (master-out, slave-in data) SCK (clock) CSN (chip select, one per slave usually active low) Names are not standard, beware! Some possible alternatives: SDI (SPI data in) instead of MISO SDO (SPI data out) instead of MOSI SCLK, CLK, SPC, instead of SCK

SPI: Serial Peripheral Interface - 3 Full-duplex transfer: data is streamed between master and slave shift-registers / FIFO buffers: the master pushes the content of its buffer to the slave via MOSI the slave pushes the content of its buffer to the master via MISO Processing / sensing / happens in between (dashed line)

SPI: Interface Protocol - 1 Four operating modes, varying by clock polarity (CPOL) and phase (CPHA): polarity sets the initial value of the SPI clock signal phase defines the edge at which MOSI is switched and the one at which MISO is sampled

SPI: Interface Protocol - 2 Master completely in charge of transfer no ack, no clock stretching contrarily to I 2 C More complex behavior than simple data streaming can be mapped on top of SPI protocol e.g. command + address + data streaming

SPI vs I2C For point-to-point, SPI is simple and efficient Less overhead than I 2 C due to lack of addressing, plus SPI is fullduplex. For multiple slaves, each slave needs separate slave select signal SPI requires more effort and more hardware than I 2 C Quad-SPI also exists 4x the bandwidth, often used by Flash drives (up to 200 Mbit/s!!!) SPI I 2 C

Configurations Daisy-chain configuration vs Independent configuration Other difference with I2C Push-pull drivers (as opposed to open drain) provide good signal integrity and high speed

system cost with more Host package pins and more PCB layers. The next-generation: I3C 10 An evolution of I2C proposed by the MIPI alliance (2016/7) Designed to fit applications currently using I2C, SPI, UART Many operating modes, I2C backward-compatibility also supported without some of the most «exotic» features such as SCL stretching supporting also (mainly) push-pull drivers 12 Targets high data rate and energy efficiency 4 5 6 7 8 9 11 In addition to the main interface other signals may be needed, such as dedicated interrupts, chip select sign and enable and sleep signals. This increases the required number of Host GPIOs, and that in turn drives As time passes and the number of sensors increases, this situation is becoming increasingly difficul support and manage. The MIPI I3C interface has been developed to ease sensor system design architectures in mobile wire products by providing a fast, low cost, low power, two-wire digital interface for sensors. Out-of-Band Interrupt I3C Main Master Host Controller May be SDR-Onl y I3C Bus (SDA & SCL) I 2 C Slave I3C Slave Figure 1 I3C System Diagram Legacy I 2 C Sensor(s) I3C Sensor(s) May be SDR-Only I3C Secondary Master I3C Smart Sensor(s) / Hub(s) / Engine(s) May be SDR-Only

The next generation: I3C 2

The next generation: I3C 3 I2C backward compatible High-Data Rate (SPI-like) Broadcast message Similar to I2C, but dynamic address

A few words on JTAG and SWD JTAG (Joint Test Action Group) or IEEE 1149.1 IEEE Standard Test Access Port and Boundary- Scan Architecture Variant: SWD Serial Wire Debug Why? Increasing board complexity Shorter product lifecycle Traditional test equipment not anymore adequate Loss of physical access Fine-pitch components SMTs, BGAs Increased board density High-speed signaling

JTAG Replace traditional boundary scan Debug interface to embedded processor - read registers, - set breakpoint, - single-stepping Abbreviation Signal TCK TMS TDI TDO TRST Test Clock Description Synchronizes the internal state machine operations Test Mode State Test mode selection Test Data In Test Data Out Test Reset Represents the data shifted into the device's test or programming logic. It is sampled at the rising edge of TCK when the internal state machine is in the correct state. Represents the data shifted out of the device's test or programming logic and is valid on the falling edge of TCK when the internal state machine is in the correct state An optional pin which, when available, can reset the TAP controller's state machine Daisy chain to control open and short circuit

Lecture Summary Reviewed hw/sw mechanisms to interface between components (inter-chip I/O) We focused mainly on serial digital interfaces (I 2 C, SPI, UART, JTAG)