8K X 8 BIT LOW POWER CMOS SRAM

Similar documents
AS6C6264 8K X 8 BIT LOW POWER CMOS SRAM REVISION HISTORY. Feb

8K X 8 BIT LOW POWER CMOS SRAM

FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 1 of 13

MARCH/2008, V 1.0 Alliance Memory Inc. Page 1 of 12

AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM

MIC1832. General Description. Features. Applications. Typical Application

CAT28C17A 16K-Bit CMOS PARALLEL EEPROM

CAT28C K-Bit Parallel EEPROM

SY89645L. General Description. Features. Block Diagram. Applications. Markets. Precision Low Skew, 1-to-4 LVCMOS/LVTTL-to-LVDS Fanout Buffer

Control Circuitry 2 M1. Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408)

MIC706P/R/S/T, MIC708R/S/T

Features. Applications

74AC11139 DUAL 2-LINE DECODER/DEMULTIPLEXER

MIC705/706/707/708. General Description. Features. Applications. Typical Application. µp Supervisory Circuit

Figure 1: TSSOP-24 ( Top View ) Figure 2: TQFN 4x4-24 ( Top View )

Reset Output. Active high Active low Active high Active low

Features VCC MIC1810 RESET RESET

SN54LVTH16240, SN74LVTH V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

PCA bit multiplexed/1-bit latched 5-bit I 2 C EEPROM DIP switch

DSC Q0093. General Description. Features. Applications. Block Diagram. Crystal-less Configurable Clock Generator

Features. Description. Applications. Pin Configuration PI4ULS3V Bit Bi-directional Level Shifter for open-drain and Push-Pull Application

MIC826. General Description. Features. Applications. Typical Application

74ABT General description. 2. Features and benefits. 3. Ordering information. Quad 2-input AND gate

PCA bit multiplexed/1-bit latched 6-bit I 2 C EEPROM DIP switch

Control Circuitry 2 M1. Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408)

SN54F38, SN74F38 QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS

A 4 A 3 A 2 ROW DECODER 64K x 16 RAM Array I/O 1 I/O X 2048 I/O 9 I/O 16

2-Mbit (128K x 16) Static RAM

AS6C K X 8 BIT LOW POWER CMOS SRAM

PTN3310/PTN3311 High-speed serial logic translators

MB85R M Bit (128 K 8) Memory FRAM CMOS DS E DESCRIPTIONS FEATURES FUJITSU SEMICONDUCTOR DATA SHEET

MB85R K (32 K 8) Bit. Memory FRAM DS E CMOS DESCRIPTIONS FEATURES PACKAGES FUJITSU SEMICONDUCTOR DATA SHEET

Features. Description. Pin Description. Pin Configuration. Pin Name Pin No. Description PI6ULS5V9511A. Hot Swappable I2C Bus/SMBus Buffer

I/O 0 I/O 7 WE CE 2 OE CE 1 A17 A18

SM Features. General Description. Typical Application MHz/312.5MHz and MHz/156.25MHz LVDS Clock Synthesizer.

12-Mbit (512 K 24) Static RAM

DUAL TTL-to-DIFFERENTIAL PECL TRANSLATOR

MF1 MOA4 S50. Contactless Chip Card Module Specification. This document gives specifications for the product MF1 MOA4 S50.

LB1868M. Specifications Absolute Maximum Ratings at Ta = 25 C. Monolithic Digital IC 2-phase Brushless Fan Motor Driver. Ordering number : EN6203A

256K-Bit PARALLEL EEPROM

1.8V/3.0V Single-PLL Clock Generator AK8150C

64K (8K x 8) Battery-Voltage Parallel EEPROM with Page Write and Software Data Protection AT28BV64B

USB/Charger and Over-Voltage Detection Device

LB1868. Specifications Absolute Maximum Ratings at Ta = 25 C. Monolithic Digital IC 2-phase Brushless Fan Motor Driver. Ordering number : EN6202A

SM Features. General Description. Applications. Block Diagram

Features. Applications

74AC11240 OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS

1.8V/3.0V Single-PLL Clock Generator

Features. Applications

SM General Description. Features. Block Diagram. ClockWorks TM 125MHz LVDS / 125 MHz HCSL Ultra-Low Jitter Frequency Synthesizer

SN54BCT760, SN74BCT760 OCTAL BUFFERS/DRIVERS WITH OPEN-COLLECTOR OUTPUTS

HT93LC46 CMOS 1K 3-Wire Serial EEPROM

SN54ALS32, SN54AS32, SN74ALS32, SN74AS32 QUADRUPLE 2-INPUT POSITIVE-OR GATES

Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408)

Features. Applications

PESDxU1UT series. 1. Product profile. Ultra low capacitance ESD protection diode in SOT23 package. 1.1 General description. 1.

NAND32GW3F4A. 32-Gbit (4 x 8 Gbits), two Chip Enable, 4224-byte page, 3 V supply, multiplane architecture, SLC NAND flash memories.

ASM5P2308A. 3.3 V Zero-Delay Buffer

ZLED7002. Toggle (Side-Step) Dual-Channel LED Driver. Datasheet. Features. Brief Description. Benefits. Available Support. Physical Characteristics

High Current Power Switch

Features. Description. Applications. Block Diagram PT7M3808. Fixed Voltage Diagram. Adjustable Voltage Diagram(PT7M3808G01)

TMR1202. General Description. TMR Bipolar Switch. Features and Benefits. Applications

Working around ERR7026 according to application needs

XRD87L85 Low-Voltage CMOS 8-Bit High-Speed Analog-to-Digital Converter

4-Mbit (512K x 8) Static RAM

QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUICKSWITCH DOUBLE-WIDTH BUS SWITCH

PI3B3253. Description. Features. Pin Configuration (QSOP, TSSOP) Block Diagram. Pin Configuration (UQFN) Truth Table (1)

CAT22C Bit Nonvolatile CMOS Static RAM

DATASHEET 4D SYSTEMS. Embedded Audio-Sound Module TURNING TECHNOLOGY INTO ART SOMO-14D. Document Date: 5 th February 2013 Document Revision: 1.

SM6008-HSTR. Features. Description. Agency Approvals. Applications. Absolute Maximum Ratings. Schematic Diagram. Ordering Information

APX803/D 3-PIN MICROPROCESSOR RESET CIRCUIT. Description. Pin Assignments. Features. Applications APX803. ( Top View ) SOT23. ( Top View ) SOT23R GND

Register Programmable Clock Generator AK8141


SM8022-HSTR. Features. Description. Agency Approvals. Applications. Absolute Maximum Ratings. Schematic Diagram. Ordering Information

Features. Applications. Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408)

Am27C128. Advanced Micro Devices. 128 Kilobit (16,384 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM FINAL

MOS INTEGRATED CIRCUIT

Low forward voltage Ultra small SMD plastic package Low capacitance Flat leads: excellent coplanarity and improved thermal behavior.

TC4049BP,TC4049BF, TC4050BP,TC4050BF

Features. Applications

AN469 I 2 C I/O ports INTEGRATED CIRCUITS. Author: Bob Marshall 2001 Aug 15 ABSTRACT

NWP2081T. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Half-bridge driver IC

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

MOS INTEGRATED CIRCUIT

GreenChip synchronous rectifier controller. The TEA1792TS is fabricated in a Silicon-On-Insulator (SOI) process.

Low forward voltage Ultra small SMD plastic package Low capacitance Flat leads: excellent coplanarity and improved thermal behavior

SN54ALS04B, SN54AS04, SN74ALS04B, SN74AS04 HEX INVERTERS

PRTR5V0U2X. 1. Product profile. Ultra low capacitance double rail-to-rail ESD protection diode in SOT143B. 1.1 General description. 1.

MIC2790/1/3. General Description. Features. Applications. Typical Application

LOW-VOLTAGE 10-BIT BUS SWITCH

N25S830HAT22IT. 256 kb Low Power Serial SRAMs. 32 k x 8 Bit Organization

MIC2790/1/3. General Description. Features. Applications. Typical Application

4-Channel 1-wire Dimming LED Driver with Ultra Low Dropout Current Source

Features. Applications

LOW-VOLTAGE OCTAL BUS SWITCH

SP233A,SP310A and SP312A

DSC2033. Low-Jitter Configurable Dual LVDS Oscillator. General Description. Features. Block Diagram. Applications

R&E International A Subsidiary of Microchip Technology Inc.

MIC2560. General Description. Features. Applications. Typical Application. PCMCIA Card Socket V CC and V PP Switching Matrix

Table 1 summarizes the supported device attribute differences between KSZ9021GN and KSZ9031MNX PHY devices. Device Attribute KSZ9021GN KSZ9031MNX

Transcription:

FEATURES 8192 x 8 bit static CMOS RAM 70 ns Access Times Common data inputs and outputs Three-state outputs Typ. operating supply current o 70 ns: 10 ma Standby current: o < 2 μa at Ta 70 C Data retention current at 2 V: o < 1 μa at Ta 70 C TTL/CMOS-compatible Automatic reduction of power dissipation in long Read or Write cycles Power supply voltage 5 V Operating temperature ranges: o 0 to 70 C o -40 to 85 C ESD protection > 2000 V (MIL STD 883C M3015.7) Latch-up immunity > 100 ma Packages: PDIP28 (600 mil) SOP28 (330 mil) DESCRIPTION The is a static RAM manufactured using a CMOS process technology with the following operating modes: - Read - Standby - Write - Data Retention The memory array is based on a 6- transistor cell. The circuit is activated by the rising edge of E2 (at E1 = L), or the falling edge of E1 (at E2 = H). The address and control inputs open simultaneously. According to the information of W and G, the data inputs, or outputs, are active. In a Read cycle, the data outputs are activated by the falling edge of G, afterwards the data word read will be available at the outputs DQ0 - DQ7. After the address change, the data outputs go High-Z until the new read information is available. The data outputs have no preferred state. If the memory is driven by CMOS levels in the active state, and if there is no change of the address, data input and control signals W or G, the operating current (at IO = 0 ma) drops to the value of the operating current in the Standby mode. The Read cycle is finished by the falling edge of E2 or W, or by the rising edge of E1, respectively. Data retention is guaranteed down to 2 V. With the exception of E2, all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required. This gate circuit allows to achieve low power standby requirements by activation with TTLlevels too. If the circuit is inactivated by E2 = L, the standby current PIN CONFIGURATION PIN DESCRIPTION MARCH/2009 ALLIANCE MEMORY PAGE 1 of 10

BLOCK DIAGRAM TRUTH TABLE MARCH/2009 ALLIANCE MEMORY PAGE 2 of 10

CHARACTERISTICS All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of VI, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times, in which cases transition is measured } 200 mv from steady-state voltage. a. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied.exposure to absolute maximum rating conditions for extended periods may affect reliability b. Maximum voltage is 7 V c. Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s. MARCH/2009 ALLIANCE MEMORY PAGE 3 of 10

MARCH/2009 ALLIANCE MEMORY PAGE 4 of 10

MARCH/2009 ALLIANCE MEMORY PAGE 5 of 10

TEST CONFIGURATION FOR FUNCTIONAL CHECK MARCH/2009 ALLIANCE MEMORY PAGE 6 of 10

MARCH/2009 ALLIANCE MEMORY PAGE 7 of 10

The information describes the type of component and shall not be considered as assured characteristic. Terms of delivery and rights to change design reserved. MARCH/2009 ALLIANCE MEMORY PAGE 8 of 10

ORDERING INFORMATION Alliance Organization VCC Range Package Operating Temp Speed ns -70SCN 8K x 8 4.5-5.5V 28pin 330 mil SOP Commercial~ 0 C 70 C 70-70SIN 8K x 8 4.5-5.5V 28pin 330 mil SOP Industrial ~ -40 C - 85 C 70-70PCN 8K x 8 4.5-5.5V 28pin 600 mil P-DIP Commercial~ 0 C 70 C 70-70PIN 8K x 8 4.5-5.5V 28pin 600 mil P-DIP Industrial ~ -40 C - 85 C 70 PART NUMBERING SYSTEM AS6C 6264 A -70 X X N SRAM prefix Device Number: Low Power (64K) Die Rev Access Time Package Option: P=28pin 600mil PDIP S=28pin 330mil SOP Temperature Range: C = Commercial (0 to 70 C) I = Industrial (-40 to + 85 C) N = Lead Free RoHS compliant part MARCH/2009 ALLIANCE MEMORY PAGE 9 of 10

Alliance Memory, Inc 511 Taylor Way, San Carlos, CA 94070, USA Phone: 650 610 6800 Fax: 650 620 9211 www.alliancememory.com Copyright Alliance Memory All Rights Reserved Copyright 2009 Alliance Memory, Inc. All rights reserved. Our three point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at anytime, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. MARCH/2009 ALLIANCE MEMORY PAGE 10 of 10