Contents 1 Basic of Test and Role of HDLs 2 Verilog HDL for Design and Test

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Transcription:

1 Basic of Test and Role of HDLs... 1.1 Design and Test... 1.1.1 RTL Design Process... 1.1.2 Postmanufacturing Test... 1.2 Test Concerns... 1.2.1 Test Methods... 1.2.2 Testability Methods... 1.2.3 Testing Methods... 1.2.4 Cost of Test... 1.3 HDLs in Digital System Test... 1.3.1 Hardware Modeling... 1.3.2 Developing Test Methods... 1.3.3 Virtual Testers... 1.3.4 Testability Hardware Evaluation... 1.3.5 Protocol Aware ATE... 1.4 ATE Architecture and Instrumentation... 1.4.1 Digital Stimulus and Measure Instruments... 1.4.2 DC Instrumentation... 1.4.3 AC Instrumentation... 1.4.4 RF Instrumentation... 1.4.5 Ate... 1.5 Summary... 1 1 1 4 8 9 11 13 13 15 15 15 16 16 16 17 17 17 17 18 18 19 20 2 Verilog HDL for Design and Test... 2.1 Motivations of Using HDLs for Developing Test Methods... 2.2 Using Verilog in Design... 2.2.1 Using Verilog for Simulation... 2.2.2 Using Verilog for Synthesis... 2.3 Using Verilog in Test... 2.3.1 Good Circuit Analysis... 2.3.2 Fault List Compilation and Testability Analysis... 2.3.3 Fault Simulation... 2.3.4 Test Generation... 2.3.5 Testability Hardware Design... 21 21 22 22 23 24 24 24 25 26 26 xi

xii 3 2.4 Basic Structures of Verilog... 2.4.1 Modules, Ports, Wires, and Variables... 2.4.2 Levels of Abstraction... 2.4.3 Logic Value System... 2.5 Combinational Circuits... 2.5.1 Transistor-Level Description... 2.5.2 Gate-Level Description... 2.5.3 Equation-Level Description... 2.5.4 Procedural Level Description... 2.5.5 Instantiating Other Modules... 2.6 Sequential Circuits... 2.6.1 Registers and Shift Registers... 2.6.2 State Machine Coding... 2.7 A Complete Example (Adding Machine)... 2.7.1 Control/Data Partitioning... 2.7.2 Adding Machine Specification... 2.7.3 CPU Implementation... 2.8 Testbench Techniques... 2.8.1 Testbench Techniques... 2.8.2 A Simple Combinational Testbench... 2.8.3 A Simple Sequential Testbench... 2.8.4 Limiting Data Sets... 2.8.5 Synchronized Data and Response Handling... 2.8.6 Random Time Intervals... 2.8.7 Text IO... 2.8.8 Simulation Code Coverage... 2.9 PLI Basics... 2.9.1 Access Routines... 2.9.2 Steps for HDL/PLI Implementation... 2.9.3 Fault Injection in the HDL/PLI Environment... 2.10 Summary... 27 28 29 29 30 30 31 32 32 34 36 36 36 42 42 42 43 48 48 49 50 51 51 52 53 54 56 57 57 59 62 62 Fault and Defect Modeling... 3.1 Fault Modeling... 3.1.1 Fault Abstraction... 3.1.2 Functional Faults... 3.1.3 Structural Faults... 3.2 Structural Gate Level Faults... 3.2.1 Recognizing Faults... 3.2.2 Stuck-Open Faults... 3.2.3 Stuck-at-0 Faults... 3.2.4 Stuck-at-1 Faults... 3.2.5 Bridging Faults... 3.2.6 State-Dependent Faults... 3.2.7 Multiple Faults... 3.2.8 Single Stuck-at Structural Faults... 3.2.9 Detecting Single Stuck-at Faults... 63 63 64 67 68 71 71 72 72 73 73 75 75 77 83

xiii 3.3 Issues Related to Gate Level Faults... 3.3.1 Detecting Bridging Faults... 3.3.2 Undetectable Faults... 3.3.3 Redundant Faults... 3.4 Fault Collapsing... 3.4.1 Indistinguishable Faults... 3.4.2 Equivalent Single Stuck-at Faults... 3.4.3 Gate-Oriented Fault Collapsing... 3.4.4 Line-Oriented Fault Collapsing... 3.4.5 Problem with Reconvergent Fanouts... 3.4.6 Dominance Fault Collapsing... 3.5 Fault Collapsing in Verilog... 3.5.1 Verilog Testbench for Fault Collapsing... 3.5.2 PLI Implementation of Fault Collapsing... 3.6 Summary... 84 84 85 85 86 86 86 87 89 91 92 95 95 97 100 101 4 Fault Simulation Applications and Methods... 4.1 Fault Simulation... 4.1.1 Gate-Level Fault Simulation... 4.1.2 Fault Simulation Requirements... 4.1.3 An HDL Environment... 4.1.4 Sequential Circuit Fault Simulation... 4.1.5 Fault Dropping... 4.1.6 Related Terminologies... 4.2 Fault Simulation Applications... 4.2.1 Fault Coverage... 4.2.2 Fault Simulation in Test Generation... 4.2.3 Fault Dictionary Creation... 4.3 Fault Simulation Technologies... 4.3.1 Serial Fault Simulation... 4.3.2 Parallel Fault Simulation... 4.3.3 Concurrent Fault Simulation... 4.3.4 Deductive Fault Simulation... 4.3.5 Comparison of Deductive Fault Simulation... 4.3.6 Critical Path Tracing Fault Simulation... 4.3.7 Differential Fault Simulation... 4.4 Summary... 103 103 103 104 105 111 111 111 112 113 114 117 122 124 127 131 133 137 137 140 141 141 5 Test Pattern Generation Methods and Algorithms... 5.1 Test Generation Basics... 5.1.1 Boolean Difference... 5.1.2 Test Generation Process... 5.1.3 Fault and Tests... 5.1.4 Terminologies and Definitions... 5.2 Controllability and Observability... 5.2.1 Controllability... 5.2.2 Observability... 143 143 143 145 146 147 147 148 148

xiv 5.2.3 Probability-Based Controllability and Observability... 5.2.4 SCOAP Controllability and Observability... 5.2.5 Distances Based... 5.3 Random Test Generation... 5.3.1 Limiting Number of Random Tests... 5.3.2 Combinational Circuit RTG... 5.3.3 Sequential Circuit RTG... 5.4 Summary... 148 155 160 160 160 163 171 174 174 6 Deterministic Test Generation Algorithms... 6.1 Deterministic Test Generation Methods... 6.1.1 Two-Phase Test Generation... 6.1.2 Fault-Oriented TG Basics... 6.1.3 The D-Algorithm... 6.1.4 PODEM (Path-Oriented Test Generation)... 6.1.5 Other Deterministic Fault-Oriented TG Methods... 6.1.6 Fault-Independent Test Generation... 6.2 Sequential Circuit Test Generation... 6.3 Test Data Compaction... 6.3.1 Forms of Test Compaction... 6.3.2 Test Compatibility... 6.3.3 Static Compaction... 6.3.4 Dynamic Compaction... 6.4 Summary... 175 175 176 177 182 191 196 197 198 200 201 201 204 209 211 211 7 Design for Test by Means of Scan... 7.1 Making Circuits Testable... 7.1.1 Tradeoffs... 7.1.2 Testing Sequential Circuits... 7.1.3 Testability of Combinational Circuits... 7.2 Testability Insertion... 7.2.1 Improving Observability... 7.2.2 Improving Controllability... 7.2.3 Sharing Observability Pins... 7.2.4 Sharing Control Pins... 7.2.5 Reducing Select Inputs... 7.2.6 Simultaneous Control and Observation... 7.3 Full Scan DFT Technique... 7.3.1 Full Scan Insertion... 7.3.2 Flip-Flop Structures... 7.3.3 Full Scan Design and Test... 7.4 Scan Architectures... 7.4.1 Full Scan Design... 7.4.2 Shadow Register DFT... 7.4.3 Partial Scan Methods... 7.4.4 Multiple Scan Design... 7.4.5 Other Scan Designs... 213 213 213 214 215 215 216 217 218 219 221 222 225 226 227 234 244 245 245 248 251 253

xv 7.5 RT Level Scan Design... 7.5.1 RTL Design Full Scan... 7.5.2 RTL Design Multiple Scan... 7.5.3 Scan Designs for RTL... 7.6 Summary... 253 253 254 258 258 259 8 Standard IEEE Test Access Methods... 8.1 Boundary Scan Basics... 8.2 Boundary Scan Architecture... 8.2.1 Test Access Port... 8.2.2 Boundary Scan Registers... 8.2.3 TAP Controller... 8.2.4 The Decoder Unit... 8.2.5 Select and Other Units... 8.3 Boundary Scan Test Instructions... 8.3.1 Mandatory Instructions... 8.4 Board Level Scan Chain Structure... 8.4.1 One Serial Scan Chain... 8.4.2 Multiple-Scan Chain with One Control Test Port... 8.4.3 Multiple-Scan Chains with One TDI, TDO but Multiple TMS... 8.4.4 Multiple-Scan Chain, Multiple Access Port... 8.5 RT Level Boundary Scan... 8.5.1 Inserting Boundary Scan Test Hardware for CUT... 8.5.2 Two Module Test Case... 8.5.3 Virtual Boundary Scan Tester... 8.6 Boundary Scan Description Language... 8.7 Summary... 261 261 262 262 263 267 271 271 271 272 277 278 278 279 279 281 281 283 285 290 292 294 9 Logic Built-in Self-test... 9.1 BIST Basics... 9.1.1 Memory-based BIST... 9.1.2 BIST Effectiveness... 9.1.3 BIST Types... 9.1.4 Designing a BIST... 9.2 Test Pattern Generation... 9.2.1 Engaging TPGs... 9.2.2 Exhaustive Counters... 9.2.3 Ring Counters... 9.2.4 Twisted Ring Counter... 9.2.5 Linear Feedback Shift Register... 9.3 Output Response Analysis... 9.3.1 Engaging ORAs... 9.3.2 One s Counter... 9.3.3 Transition Counter... 9.3.4 Parity Checking... 9.3.5 Serial LFSRs (SISR)... 9.3.6 Parallel Signature Analysis... 295 295 295 297 297 298 300 300 300 301 302 303 312 312 312 314 316 316 317

xvi 9.4 BIST Architectures... 9.4.1 BIST-related Terminologies... 9.4.2 A Centralized and Separate Board-level BIST Architecture (CSBL)... 9.4.3 Built-in Evaluation and Self-test (BEST)... 9.4.4 Random Test Socket (RTS)... 9.4.5 LSSD On-chip Self Test... 9.4.6 Self-testing Using MISR and SRSG... 9.4.7 Concurrent BIST... 9.4.8 BILBO... 9.4.9 Enhancing Coverage... 9.5 RT Level BIST Design... 9.5.1 CUT Design, Simulation, and Synthesis... 9.5.2 RTS BIST Insertion... 9.5.3 Configuring the RTS BIST... 9.5.4 Incorporating Configurations in BIST... 9.5.5 Design of STUMPS... 9.5.6 RTS and STUMPS Results... 9.6 Summary... 319 319 10 Test Compression... 10.1 Test Data Compression... 10.2 Compression Methods... 10.2.1 Code-based Schemes... 10.2.2 Scan-based Schemes... 10.3 Decompression Methods... 10.3.1 Decompression Unit Architecture... 10.3.2 Cyclical Scan Chain... 10.3.3 Code-based Decompression... 10.3.4 Scan-based Decompression... 10.4 Summary... 345 348 347 347 357 362 363 365 366 372 372 372 11 Memory Testing by Means of Memory BIST... 11.1 Memory Testing... 11.2 Memory Structure... 11.3 Memory Fault Model... 11.3.1 Stuck-At Faults... 11.3.2 Transition Faults... 11.3.3 Coupling Faults... 11.3.4 Bridging and State CFs... 11.4 Functional Test Procedures... 11.4.1 March Test Algorithms... 11.4.2 March C- Algorithm... 11.4.3 MATS+ Algorithm... 11.4.4 Other March Tests... 375 375 376 377 377 379 380 380 320 321 322 324 325 326 328 329 329 330 330 326 338 340 343 343 343

11.5 xvii MBIST Methods... 11.5.1 Simple March MBIST... 11.5.2 March C- MBIST... 11.5.3 Disturb MBIST... 11.6 Summary... 381 381 385 387 391 391 Appendix A Using HDLs for Protocol Aware ATE... 393 Appendix B Gate Components for PLI Test Applications... 397 Appendix C Programming Language Interface Test Utilities... 399 Appendix D IEEE Std. 1149.1 Boundary Scan Verilog Description... 403 Appendix E Boundary Scan IEEE 1149.1 Virtual Tester... 411 Appendix F Generating Netlist by Register Transfer Level Synthesis (NetlistGen)... 423 Index... 427

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