EEM870 Embedded System and Experiment Lecture 4: SoC Design Flow and Tools

EEM870 Embedded System and Experiment Lecture 4: SoC Design Flow and Tools Wen-Yen Lin, Ph.D. Department of Electrical Engineering Chang Gung University Email: wylin@mail.cgu.edu.tw March 2013

Agenda Introduction System Level Design HW/SW Co-Design EDA Tools in SoC Design HW/SW Partitioning Algorithm Design and Conceptual Prototyping HW/SW Co-Simulation Platform Architect, CoWare ESL Design Platform-Driven Design Capabilities SPD, CoWare (SPW, Synopsys) Overview Solutions Analysis Libraries Options Seamless, Mentor Graphics Overview Coherent Memory Server Dynamic Optimization C-Bridge Technology System-Level Prototyping 2

Introduction 3

System Level Design A Top-Down Process Started from Algorithm Design & Architecture Design Algorithm Design: Computation Requirement => complexity & expandability Architecture Design: Computation units Communication elements Architecture planning HW/SW Co-Design Platform-driven ESL Design 4

HW/SW Co-Design Cost Estimation HW/SW partitioning & tasks assignment Partitioning based on spec. and IP(reuse) HW ASICs, FPGAs SW Programs in processors Communication elements as interfaces between SW and HW entities Come out few candidates for performance estimation Performance Estimation Tasks and entities assignments Performance modeling and evaluation HW & SW developments can be done separately by well design in System level and good partitioning. 5

EDA Tools in SoC Design System Level Design Platform Architect, CoWare SPD, CoWare HW/SW Co-Verification Seamless, Mentor Graphics Virtual Component Co-Design VCC, Cadence Hardware Implementation Behavior Compiler, Synopsys VERA, Synopsys Formality, Synopsys 6

Agenda Introduction System Level Design HW/SW Co-Design EDA Tools in SoC Design HW/SW Partitioning Algorithm Design and Conceptual Prototyping HW/SW Co-Simulation Platform Architect, CoWare ESL Design Platform-Driven Design Capabilities SPD, CoWare (SPW, Synopsys) Overview Solutions Analysis Libraries Options Seamless, Mentor Graphics Overview Coherent Memory Server Dynamic Optimization C-Bridge Technology System-Level Prototyping 7

Hardware/Software Partitioning Algorithm Design Product application Algorithm Functional Blocks Functional Blocks Function Verification Architecture Design 8

Hardware/Sotware Partitioning Conceptual Prototyping Cost Model Types and numbers of computation units Memory block size Task Assignments Performance Model Dynamic Behavior Communication Elements 9

Hardware/Software Co-Simulation Challenge: How to incorporate IPs into system verification and simulations? Development environment for Hardware/Software Co-Simulation to reduce the gaps between IP providers and IP integrators 10

Hardware/Software Co-Simulation 11

Hardware/Software Co-Simulation Each IP comes with its own models and verification tools Hardware/Software Co-Simulation platform => Multi-Layer IP Model 12

Agenda Introduction System Level Design HW/SW Co-Design EDA Tools in SoC Design HW/SW Partitioning Algorithm Design and Conceptual Prototyping HW/SW Co-Simulation Platform Architect, CoWare ESL Design Platform-Driven Design Capabilities SPD, CoWare (SPW, Synopsys) Overview Solutions Analysis Libraries Options Seamless, Mentor Graphics Overview Coherent Memory Server Dynamic Optimization C-Bridge Technology System-Level Prototyping 13

ESL Design & Verification Electronic System Level (ESL): an emerging electronic design methodology that focuses on the higher abstraction level. Traditional EDA design flow from RTL to GDS II is no longer for sufficient for a complex System-on-a-Chip. The utilization of appropriate abstractions in order to increase comprehension about a system, and to enhance the probability of a successful implementation of functionality in a cost-effective manner. To model the behavior of the entire system using a high-level language such as C, C++, or MATLAB. ESL can also be accomplished through the use of SystemC as an abstract modeling language. Now an established approach at most of the world s leading Systemon-a-chip (SoC) design companies, and is being used increasingly in system design. 14

Platform-driven ESL Design Nowadays SoC design is a complex system Processor Centric Processors, memories, busses, peripherals, etc. Needs a platform to facilitate the ESL design methodology. Figure: Design risk without platform-driven ESL 15

CoWare Platform Architect SystemC Platform Capture and Architecture Analysis for Platform-driven ESL Design What is SystemC? A system-level modeling language A set of C++ classes and macros providing an evendriven simulation kernel in C++ Concurrent process simulation Used for system-level modeling, architectural exploration, performance modeling, software development, functional verification, and high-level synthesis Often associated with ESL design and with Transaction-level modeling (TLM) Rather not be HDL but a bridge between system behavior modeling and RTL code development. 16

CoWare Platform Architect Highlights Rapid capture and configuration of hierarchical SoC platforms Superior architecture and performance analysis for SystemC Rapid exploration of complex interconnect and memory architectures SystemC platform-level debug and transaction analysis Advanced simulation, debug, and analysis for software development. Comprehensive SystemnC IP Model availability 17

CoWare Platform Architect Platform Creator Hierarchical SoC Platform http://www.screencast.com/t/yti2nmnio 18

CoWare Platform Architect For architectural analysis, Platform Architect provides Analyze cycle-accurate performance Study throughput and bottlenecks Look at bus switching and cache usage to reduce power Optimize bus & memory architecture 19

CoWare Platform Architect For functional analysis, Platform Architect provides: Look at system response and task scheduling Analyze processor loading to drive partitioning Profile software for optimization Cross-correlate different views to extract powerful information 20

CoWare Platform Architect Summary Platform Architect is focused on making SystemC platform capture and architecture analysis for platform-driven ESL design a reality for SoC architects and design teams. Platform Architect Benefits Deliver differentiated, superior products by finding the optimal hardwaresoftware partitioning, interconnect and memory architecture Reduce product development risk while avoiding expensive over-engineering by confirming the architecture meets all performance, power and cost requirements prior to implementation Differentiate by automating on-chip interconnect implementation, allowing design resources to focus on value-added functions Easily create system-level models of platform subsystems for rapid evaluation, customization, and design-in. Bring better SoC-based convergent products to market, faster 21

Agenda Introduction System Level Design HW/SW Co-Design EDA Tools in SoC Design HW/SW Partitioning Algorithm Design and Conceptual Prototyping HW/SW Co-Simulation Platform Architect, CoWare ESL Design Platform-Driven Design Capabilities SPD, CoWare (SPW, Synopsys) Overview Solutions Analysis Libraries Options Seamless, Mentor Graphics Overview Coherent Memory Server Dynamic Optimization C-Bridge Technology System-Level Prototyping 22

CoWare Signal Processing Designer Overview Value Now, part of SPW - Synopsys System Level Development Tool Implementing Algorithm for Platform-Driven ESL Design. C-based modeling and simulation environment. Facilitates structured modeling and model reuse across design teams. Tightly integrated with Coware Platform Architect and CoWare Processor Designer products Optimization of the system cost and system performance Systematic approach to verification and implementation into H/W and S/W ESL (Electronic System Level) Design and Verification: model the behavior of the entire system using a high-level language Demo: Throughput Analysis of a Signal Captured from Signal Analyzer 23

SPD - Solutions Hierarchical Block Diagram Editor Straight forwarded design concept for large system design. A library of 4000+ blocks available Quickly assemble the basic algorithms and set the parameters for a specific application. 24

SPD - Solutions Simulation Manager Simulation is necessary for system optimization Optimal scheduling sequence Optimal individual operations Pre-packaged libraries provided as a reference for the standard, e.g. HSDPA Total system design may integrates with hundreds of complex individual algorithms. Library management and control help to keep track of the design evolution and facilitate structured reuse of designs. Support server farms with load balancing utilities 25

SPD - Solutions Polymodeling Floating-point number representations in initial system optimization. Fixed-point representation for final system implementation on cost and performance optimization Polymodeling allows switching between floating-point and fixed-point representations in a single model. 26

SPD - Solutions Easy integration of C-source codes, Matlab models, etc. Source codes are all available on 4000+ models in the library for modification Verified model can be exported for CoWare Platform Architect usage. Processor model generate by CoWare Processor Designer can be integrated to facilitae the verification. 27

SPD - Analysis Interactive analysis supported by predefined analysis widget, such as multi-trace oscilloscopes, Signal Generators, Spectrum Analyzers, etc.) 28

SPD - Analysis Rich set of plot functions for Post-simulation analysis 29

SPD - Libraries SPW Communication Library Commonly used communication functions Modulators, demodulators, adaptive equalizers, error correction, filtering, channel models, etc. Available on both floating and fixed point models Including RF and Smart Antenna models Power Amplifiers, mixers, oscillators MIMO systems, diversity antenna systems, etc. DVB-S and DVB-H reference models. WCDMA Library WiMax Library GSM/GPRS/EDGE Library CDMA2000 Library WLAN/WPAN Library Multimedia Libarary 30

SPD - Options Hardware Design System (HDS) Accelerate hardware design, verification and analysis Graphical RTL design capabilities Analog-Mixed Signal (AMS) co-simulation with Cadence Incisive. Supports RTL simulation from Cadence and Mentor. Supports RTL synthesis products from Synopsys and Cadence. 31

HDS Key Benefits Bridges the gap between design levels behavioral, architectural, ASIC/FPGA To create the fastest available path from drawing board system-level constructs to silicon. Generates HDL from block libraries Importing HDL into HDS for integrated verification Drastically reduces development and verification time Supporting both bottom-up and top-down flows Enables IP reuse Providing RTL design capabilities with parameterized design capture Simplified debugging and monitoring Easy to create a system testbench 32

Agenda Introduction System Level Design HW/SW Co-Design EDA Tools in SoC Design HW/SW Partitioning Algorithm Design and Conceptual Prototyping HW/SW Co-Simulation Platform Architect, CoWare ESL Design Platform-Driven Design Capabilities SPD, CoWare Overview Solutions Analysis Libraries Options Seamless, Mentor Graphics Overview Coherent Memory Server Dynamic Optimization C-Bridge Technology System-Level Prototyping 33

Seamless HW/SW Co-Verification Mentor Graphics Full visibility and control of hardware and software execution Efficient debug of hardware, firmware, and software early in the design process Dynamic performance optimizations Support over 100 embedded controllers and DSPs Single point of control for hardware and software simulation 34

Seamless Features Enable to create a virtual prototype of a complete embedded system Fully verify the hardware/software interface, accelerate the debug of firmware, and analyze the performance of your chosen implementation Software simulation objects in standard binary formats. Validating hardware-centric software and firmware function with the embedded hardware Embedded software can be used as a test bench Works with RTL that exactly represents the final implementation. Instruction-Set Simulator (ISS) to improve software simulation efficiency. However ISS can be negated if the ISS needs to communicate with the logic simulator on every cycle Coherent Memory Server 35

Seamless Integrated Environment 36

Seamless Coherent Memory Server The Coherent Memory Server is a cosimulation interface between hardware and software instances that provide access paths to memory from both the ISS and the logic simulator The Coherent Memory Server supports: Multi-processor designs and processors with multiple address spaces Wide range of commonly used memory management techniques such as interleaving, remapping, error code correction and parity checking. 37

Seamless Dynamic Optimation The Seamless environment supports: A set of options which routes memory requests from the ISS to the Coherent Memory Server, either directly, or via the logic simulator Dynamic optimizations Optimization allow: The designer to switch between direct access and high-validity simulation The freedom to choose which areas of memory are optimized, and when they are optimized without the need to halt or restart simulation 38

Seamless C-Bridge Technology System level prototyping Accelerate verification C API for abstract bus communication Mixed C and RTL design simulation Cycle accurate bus modeling Control pin interface between C and HDL design 39

System-level Prototyping Using C-Bridge 40

Reference http://www.synopsys.com http://www.mentor.com/seamless 41