Advances in 3D Simulations of Chip/Package/PCB Co-Design Richard Sjiariel, CST AG
Co-design environment Signal Integrity and timing Thermal analysis and stress Power Integrity and noise analysis EMC/EMI and radiation
Analysis across Chip/Package/PCB Nanometer scale Multi Gb PCB systems Need for co-design
Co-design Chip/interposer Board/Package Simplistic approach to CPB co-simulation may miss critical physics of the chip-package and package-board interactions. High-order electromagnetic interactions in the CPB system have a critical impact on the system integrity.
Co-design methodologies 1) Cascading approaches field based (continuity of E/H field and reference plane where propagating more is TEM) - PCB and Package Co/Design and Co/Optimization S-parameters based considering all pins (signal/pwr/gnd vias) 2) Simulation of the full system (Full 3D EM solvers or hybrid solvers)
S-Parameter Based Electric wall and ports at the interface Source: Zhaoqing Chen, General Co-Design Approach to Multi-Level Package Modeling based on Individual Single-Level Package Full-Wave S-Parameter Modeling Including Signal and Power/Ground Ports, ECTC 2012
Test Case (1/2) PCB + Package Package Signal vias PCB Signal vias PWR/GND vias PWR/GND vias Signal vias
Test Case (2/2) Package PCB The effect of the discrete port is de-embedded from the S-parameters of both PCB and package using c=-0.11pf
Results: Full Model vs. Cascaded Ins./return loss NEXT/FEXT (+) Very small difference between full model vs. cascaded model (-) Methodology difficult to use (prone to errors) when dealing with realistic models with many signal/power/gnd vias
PCB/Package Co-Design Pkg1: 2.5x2.5cm 21 layers Pkg2: 2.8x2.5cm, 21 layers
Geometry Details 1, 2 input-output 3, NEXT 4, FEXT 3 1 Multiple 3D geometries and RPDs: PTH BGA and bumps Micro vias..etc 4 2
PCB vs Channel (PCB + Package) S11 full channel S11 PCB only S21 PCB only S21 full channel pkg1 PCB pkg2 Insertion loss S21-5 to 8dB difference in attenuation Return loss S11 large discrepancy in range 2-8GHz showing underestimation of impedance match for PCB model
Statistics Hardware(Nehalem) GPU Simulation Time/h Speed-up factor 1 node 0 96 1 8 node cluster 0 19 5.1 4 node cluster 8 3.2 30
Chip Modeling IBIS SPICE CPM/SPICE CAD EM modeling
Chip/Package/Board (CPB) Co-Design The anti-resonance peak occurs at the cross point of package inductance and chip capacitance. This is called chip-package anti-resonance. Source: R. Kobayashi et al, Effects of Critically Damped Total PDN Impedance in Chip-Package-Board Co-Design, IEEE EMC Conference, Pittsburgh 2012.
IBIS/SPICE Workflow Example DIE PKG Socket PCB Fixtures IBIS SPICE Signal Net Power Plane Pogo Pin Signal Trace Power Plane SMA Cable Scope
3D Model Victim Line Aggressor Lines 372x205mm large, 17 layers PCB Epsr=3.9, tgδ0.035 6 layers package with bond wires
Full System simulation PCB + package+ pogo pin Chip/ASIC
Comparison: Insertion Loss (Single Ended) Package + board + all nets = 3.16db Package + board + single net +-2.9db Package + board + all nets = 3.16db Package + board + all nets Package + board + single net Package only
Transient Response Co-Simulation Port 17 represents an output result at PCB More realistic result helps to find the correct parameter for equalizer
Surface Currents Surface current at 1GHz
Strong coupling with neighbor nets Package/pogo pin to PCB (vertical) coupling Time Domain Field Monitor
SPICE/CPM A CPM (Chip Power Model) is a compact SPICE model of the full-chip power delivery network (PDN). It contains spatial and temporal current switching profiles, as well as parasitic of the non-linear on-chip devices +
CPM model validation Automatic assignment of current profiles/ports CST DS results SPICE results
SPICE/CPM Workflow Example PCB package 86x86mm 6 layer PCB epsr=3.57, tgδ=0.025 die
CPB System Co-Simulation Drivers (IBIS) PCB + package SPICE + Current profiles
Current Profiles Currents feeding into package Switching current at chip
Current seems to be confined in island, but it progressively couples to the rest of the structure Field Monitor
Surface Current Distribution f=1ghz f=1ghz f=10ghz f=10ghz
EMC/EMI Analysis Farfield monitor probes at 3m
Summary Importance of chip/package/board (CPB) co-design is highlighted and its integration into various simulation workflows is discusses True transient co-simulation is a key feature for CPB co-design 3D packages with embedded chips 3D system integration 3D full wave simulation is only choice for accurate results