RTL Coding General Concepts

RTL Coding General Concepts

Typical Digital System 2

Components of a Digital System Printed circuit board (PCB) Embedded d software microprocessor microcontroller digital signal processor (DSP) ASIC Programmable Logic Device (PLD) FPGA, etc. 3

Building Digital Systems 4

Computer-Aided Design Can't design FPGAs by hand Way too much logic to manage, hard to make changes Hardware description languages Specify functionality of logic at a high levelel Validation: high-level simulation to catch specification errors Verify pin-outs and connections to other system components Low-level to verify mapping and check performance Logic synthesis Process of compiling HDL program into logic gates and flip-flopsflops Technology mapping Map the logic onto elements available in the implementation technology (LUTs for Xilinx FPGAs) 5

CAD Tool Path (cont d) Placement and routing Assign logic blocks to functions Make wiring connections Timing i analysis - verify paths Determine delays as routed Look at critical paths and ways to improve Partitioning and constraining If design does not fit or is unroutable as placed split into multiple chips If design it too slow prioritize critical paths, fix placement of cells, etc. Few tools to help with these tasks exist today Generate programming files - bits to be loaded into chip for configuration 6

HDL Approach 7

Advantages of HDLs Allows designers to talk about what the hardware should do without actually designing g the hardware itself, or in other words HDLs allow designers to separate behavior from implementation at various levels of abstraction Designers can develop an executable functional specification that documents the exact behavior of all the components and their interfaces Designers can make decisions about cost, performance, power, and area earlier in the design process Designers can create tools which automatically manipulate the design for verification, synthesis, optimization, etc. 8

What Is a Hardware Description Language? g A Hardware Description Language (HDL) is a high level programming language that offers special constructs with which hyou can model dlmicroelectronic circuits. These special language constructs permit you to: Describe the operation of a circuit at various levels of abstraction The behavior of a circuit The function of a circuit The structure of a circuit Describe the timing of a circuit Express the concurrency of circuit operation 9

Features in Common HDLs share several features in common: An HDL usually contains both low level and high level constructs for modeling hardware at multiple levels of abstraction An HDL permits you to describe the timing characteristics and requirements of the hardware With an HDL you can express the concurrency of the hardware operation Software programming languages typically have no concept of time. In hardware, there are delays associated with going from an input to an output. An HDL allows you to model these delays because it has a concept of time. 10

Why Use an HDL? There are several benefits to using an HDL to describe your design: An HDL facilitates t a top down design methodology using synthesis You can design at a high implementation independent level You can delay decisions on implementation details You can easily explore design alternatives You can solve architectural problems before implementation You can automate mapping of your high level description to a technologyspecific implementation An HDL provides greater flexibility You can re use earlier design components You can move your design between multiple vendors and tools An HDL permits you to take advantage of mature software design practices You can more quickly capture your design intent You can more easily manage your design data 11

HDL is NOT a Software Programming Language! Software Programming Language Language which can be translated into machine instructions and then executed on a computer Hardware Description Language Language with syntactic and semantic support for modeling the temporal behavior and spatial structure of hardware 12

VHDL or Verilog? VHDL Commissioned in 1981 by Department of Defense; Now an IEEE standard Initially created for ASIC Synthesis Strongly typed; potential for verbose code Strong support for package management and dlarge designs ADA-like verbose syntax, lots of redundancy Design is composed of entities each of which can have multiple architectures Gate-level, dataflow, and behavioral modeling. Synthesizable subset. Harder to learn and use Verilog Created by Gateway Design Automation in 1985; Now an IEEE standard Initially an interpreted language for gatelevel simulation Less explicit typing (e.g., compiler will pad arguments of different widths) No special extensions for large designs C-like concise syntax Design is composed of modules which have just one implementation Gate-level, dataflow, and behavioral modeling. Synthesizable subset. Easy to learn and use 13

Verilog Example 14

VHDL Example 15

Why Verilog HDL is more Popular? Verilog HDL is a general purpose hardware description language that is easy to learn and easy to use. It is similar in syntax to the C programming language. Designers with C programming experience will find it easy to learn Verilog HDL. Verilog HDL allows different levels of abstraction to be mixed in the same model. Thus, a designer can define a hardware model in terms of switches, gates, RTL, or behavioral code. Also, a designer needs to learn only one language g for stimulus and hierarchical design. Most popular logic synthesis tools support Verilog HDL. This makes it the language of choice for designers. All fabrication vendors provide Verilog HDL libraries for post logic synthesis simulation. Thus, designing a chip in Verilog HDL allows the widest choice of vendors. The Programming Language Interface (PLI) is a powerful feature that allows the user to write custom C code to interact with the internal data structures of Verilog. Designers can customize a Verilog HDL simulator to their needs with the PLI. 16

Verilog History 1980 s: Gateway Design Automation developed Verilog 1990: Cadence acquired Gateway 1991: Cadence released Verilog to the public domain. Open Verilog International (OVI) formed to: Evolve and maintain Verilog Promote the use of Verilog 1995: IEEE ratified the Verilog LRM (Std. 1364) 2001: IEEE updated the Verilog LRM 17

Verilog Applications The Verilog HDL is used by: System architects doing high level system simulations Verification engineers writing advanced tests for all levels els of simulation ASIC and FPGA designers writing RTL code for synthesis Library developers describing ASIC or FPGA cells, or higher level components 18

Verilog Supported Levels of Abstraction The Verilog HDL supports three main levels of abstraction: Behavioral Describes a system by the flow of data between its functional blocks Defines signal values when they change Register Transfer Level (RTL) or Functional Describes a system by the flow of data and control signals between and within ihi its functional blocks Defines signal values with respect to a clock Structural Describes a system by connecting predefined components Uses technology specific, low level components when mapping from an RTL description to a gate level netlist, such as during synthesis 19

The Behavioral Level 20

The RTL Level 21

The Structural Level 22

One Language for All Levels 23