Term Paper for EE 680 Computer Aided Design of Digital Systems I Timber Wolf Algorithm for Placement. Imran M. Rizvi John Antony K.

Transcription

1 Term Paper for EE 680 Computer Aided Design of Digital Systems I Timber Wolf Algorithm for Placement By Imran M. Rizvi John Antony K. Manavalan

2 TimberWolf Algorithm for Placement Abstract: Our goal was to study the TimberWolf package and algorithm for the VLSI design problems, specifically placement. The TimberWolf package is based on simulated annealing which is a probabilistic, iterative improvement technique. The iterative improvement does not allow for acceptance of a state whose energy is higher than the current state s energy, which means that once it is stuck into a local minimum it can t get out; simulated annealing allows the provision to accept states with higher energies in hope that it will get out of local minimums. The TimberWolf is an extension of the simulated annealing with certain constraints and restrictions on the cost functions, cooling schedule, move set and solution space. Introduction: Placement is the process of arranging the circuit on a layout surface. The process of placement consists of finding the optimal physical locations for the VLSI cells on the given layout area if we are provided with the dimensions of the cells, the collection of nets joining them, and the Input/Output ports on the boundary. The optimal locations mean that they minimize the given objective function, according to some constraints. The objective function usually is the Total wire length, while the constraints can be avoidance overlap of cells, max chip area size, The placement of the VLSI cells and the blocks is an NP-Complete combinatorial problem and various algorithms and techniques have been applied over the years to solve it. Most of them do not produce good results or are too time consuming. The main objective of the placement problem is to assign the partitions to specific cells such that an

3 objective functions (e.g. Total Wire length) is minimized, which will result is the minimization of the total area of chip. TimberWolf 3.2 is a standard cell placement and routing tool. It places the cells such that the total estimated interconnect cost is minimized. In this stage it uses the simulated annealing algorithms. After that the tool routes the placed cells and tweaks them for the area optimization. We focused on the placement part of it. TimberWolf has achieved area efficiency from 15% to 75% on numerous industrial circuits. Previous placement techniques were either 1) manual which required a lot of man hours or 2) Automatic in which the algorithms used were not flexible enough. The TimberWolf used the idea of simulated annealing, which is inspired from annealing of solids, which leads to a crystal structure. TimberWolf packages handles stander cell circuit configurations, in which the standard cells are arranges in horizontal rows and where as many as 11 macro blocks are permitted on chip. Furthermore the pads are placed around the periphery of the chip. Annealing of Solids TimberWolf uses the simulated annealing algorithms. Simulated annealing is the most well developed algorithm for the cell placement. Simulated annealing is inspired by the annealing of solids. The process of solidification consists of going from a high energy, disordered state to a low energy state. In The high energy state the movement of molecules of solid is random and fast. As the energy is lowered or the temperature is lowered by cooling the molecules for a regular crystalline structure. This corresponds to the low energy state. To achieve this, solid is annealed, heated to a temperature that permits many atomic rearrangements, then cooled slowly and carefully so as to allow them to arrange in crystal structure on cooling. This is real annealing, the process of simulated annealing tries to mimic it by analogous set of controlled cooling operations to transform a poor unordered optimization solution into a highly ordered optimized solution.

4 Simulated Annealing, analogy to physical annealing: The simulated annealing is a part of iterative improvement strategies. Which attempts to perturb an existing random or initial solution in the direction of a better, optimal, low-cost solution. This can be understood by the following example. Let us assume that there is an initial solution and we perturb it a little bit so that it can reach another solution in its neighborhood which has a lesser cost. The present solution is shown by a ball in the diagram. We apply a small random perturb to the solution (that is we change the existing solution a little bit) to get a nearby solution with less cost. The neighborhood of the current solution is from A to B. this process can continue starting from the new configuration until no further improvement are obtained at which point the process terminates. This method seems reasonable but it has a serious problem: it is easily trapped in the local minima. Solution that looks good in a small neighborhood but not necessarily the global optimum. This standard iterative improvement is a down-hill only style.each new solution moves to downwards only and thus becoming trapped in local minima. Cost Current Configuration Allowed Downward Perturbation A B Configuration C Global Minima Neighborhood

5 The simulated annealing is the same method as the above mentioned iterative improvement strategy but with one difference. It allows the perturbations to uphill in a controlled fashion. The individual perturbations are the moves or changes which will lead to a different solution slightly different (in neighborhood) of the original one. So now with simulated annealing each move can form an existing configuration into a worse configuration of higher energy by jumping uphill and out of the local minima. So now it is possible to jump out of the local minima to a more promising downhill path. However because the uphill moves are carefully controlled we don t have to worry about getting close to a final solution, only to randomly jump uphill to some far worse one. The analogy of different parameters in the real annealing to those in simulated one is as following Simulated Annealing and VLSI Placement:?? Arrangement of atoms = a new configuration of cells ( a new solution)?? Total configurations = Total solution set?? Perturbation = small random movement of cells to get new configuration (possible solution).?? Energy = Cost function?? Temperature = control parameter?? Cooling schedule = starting temperature and a rule how to decrease the temperate or how to cool The idea of temperature in simulated annealing is of a control parameter to moderate the uphill moves, in other way it will regulate the acceptance of the high energy or high cost solutions. That is if the temperature is high it will allow the uphill jump and if it is low it

6 will only not allow higher jumps and at freezing temperature it will turn greedy and only let down hill moves. A Random perturbation is proposed such as moving a particle to a new location and then evaluating the resulting change in energy? E. If? E is reduced the new configuration has lower energy and is accepted as the starting point for the next move. However, if the energy is increased, the move may still happen, the new higher energy configuration may be acceptable. In physical systems, jumps to higher energy do happen but are moderated by the current temperature T. At higher temperatures, the probability of large uphill moves in energy is large and at low temperatures the probability is small. This is modeled by the Metropolis algorithm which uses a Boltzmann Distribution, the probability of an uphill move of size delta E at temperature T is Pr [accept] = e -? E/T. In practice this probabilistic acceptance is achieved by generating a uniform random number R in [0, 1] and comparing it against the threshold Pr [accept]. Only if R < Pr is the move accepted. Thus very probably moves can be rejected and very improbable moves can be accepted at least occasionally. By successively lowering the temperature and running this algorithm, we can simulate the material coming into equilibrium at each newly reduced temperature and thus effectively simulate the physical annealing. For the placement problem a legal configuration is just an assignment of cells to locations. The cost function we choose is simply the total estimated wire length. The cooling schedule will be the simplest possible, that is it will be a geometrically decreasing temperature. TimberWolf 3.2: Based on the input data and the parameters supplied by user TimberWolf 3.2 constructs the standard cell circuit topology. These parameters in conjunction with the total width of standard cells will enable TimberWolf to compute the initial position and the target length of the rows. Macro blocks are placed next, followed by placement of pads. Pads and macro blocks retain their initial positions, and only the placement of standard cells is optimized. Following initial placement, the algorithm then performs

7 placement and routing in three distinct stages. In the first stage, cells are placed so as to minimize the estimated wire length. In the second stage feed through cells are inserted as required, wire length is minimized again and then preliminary global routing is done. In the third stage local changes are made in the placement to reduce the number of wiring tracks. The objective function which TimberWolf 3.2 attempts to minimize during the placement is the estimated interconnect cost. The purpose of the first stage is to find a placement of standard cells such that the total estimated interconnects cost is minimized. Perturb (Generate) Function: (Move Set): A neighbor function called perturb (generate) is used to produce new states by making a random selection from one of three possible perturb functions which are?? Move a single cell to a new location?? Swap two cells?? Mirror a cell about the x-axis AlgorithmsStructure(j0,T0){ T=T0; X=j0; While( Stopping criterion is not satisfied){ While ( inner loop criterion ){ J=generate(X); If(accept(c(j)),c(X),T){ X=j; } } T = update(t); } } accept( c(j), c(i), T) { delta c = c (j) c(i); y = f(delta c, T ) ; r= random (0,1); if( r < y ) { return( 1 ); } else { return ( 0 ); } }

8 The accept function is given by function f shown below f (? c, T ) = min 1, e -? E/T The acceptance function shows the probability of acceptance of bad or uphill and high cost( energy ) moves. If the temperature is high the probability function f is high and the bad uphill move is accepted, so the solution will come out of local minima. But if the temperature is low then the probability of accepting the up hill moves is very low and the TimberWolf of accepts down hill moves. TimberWolf 3.2 uses cell mirroring less frequently when compared to cell displacement and pair wise cell swapping. In particular mirroring is attempted in 10% of the cases only. (xa,y a) * Wt Window Range Limiter: Perturbations are limited to a region within a window of height Ht and width Wt. For example if a cell must be displaced the target location is found within the limiting window centered around the cell. Therefore two cells A and B centered at (xa,ya) and (xb,yb) are selected for interchange only if xa-xb <= W t and ya-yb < = H t.

9 The dimensions of the window are decreasing functions of the temperature T. If current temperature is T1 and next temperature is T 2 are decreased as follows. the window width and height W(T2 )= W(T 1 ) * {log(t 2 )/log(t 1 ) } H(T2 )= H(T 1 ) * {log(t 2 )/log(t 1 ) } Cost function: The cost function used by TimberWolf 3.2 is the sum of three components? =?1 +?2 +?3?1 is a measure of the total estimated wire length. for any net i if the horizontal and vertical spans are given by Xi and Y i then the estimated length of the net is X i +Y i. This must be multiplied by the weight Wi of the net. Further sophistication may be achieved by associating two weights to the net. The horizontal component wi H and vertical component wi H Thus,? 1?? i? nets H V? w. X? w. Y? i i i i the weight of a net is useful in indicating how critical the net is. If a net is part of a critical part, for example we want it to be as short as possible so that it introduces as little wiring delay as possible. We can increase the weight of critical nets to achieve this goal. independent horizontal and vertical weights give the users the flexibility to favor

10 connections in one direction over the other. Thus in the cell vertical spans may be given preference over horizontal tracks. This can be accomplished by lowering the weight w V. In chips where feed troughs are costly in terms of area, horizontal wiring may be preferred by lowering w H. Overlap: When a cell is displacing, or two cells are swapped, it is possible that there is an overlap between two or more cells. Let Oij indicate the area of overlap between two cells i and j. clearly, overlaps are undesirable and must be minimized, the second component of the cost function?2 is interpreted as the penalty of overlaps and is defined as follows? 2? w? 2 i? j 2?? O ij in the above equation, the w 2 is the weight for penalty. the reason for squaring the overlap is to provide much larger penalties for larger overlaps. Due to cell displacement and pair wise exchanges of cells, the length of a row might larger or smaller. Uneven Row Length in Standard Cell Design The third component of the cost function represents a penalty for the length of a row R exceeding (or falling short of) the expected length L R.? 3?? L R? L R w 3 rows

11 where W3 is the weight of unevenness. Uneven distribution of row lengths results in wastage of chip area. There is also experimental evidence indicating dependence of both the total wire length and the routability of the chip on the evenness of distribution. Annealing Schedule: The cooling schedule is represented by T? T?T i? 1?? i. Where A(t) is the cooling rate parameter which is determined experimentally. The annealing process is started at a very high initial temperature say 4*10e6. Initially the temperature is reduced rapidly?? T? = 0.8. In the medium range the temperature is reduced slowly,?? T? =0.95, most processing is done in this range. In the low temperature range the temperature is reduced rapidly again.?? T? =0.8. The algorithm is terminated when t<1. Inner Loop Criterion: At each temperature, a fixed number of moves are attempted. The optimum number of moves depends upon the size of the circuit. From experiments for a 200 cell circuit, 100 moves per cell are recommended which calls for the valuation of 2.34*10E6 configuration in about 125 temperature steps. For a 3000 cell circuit 700 moves per cell are recommended which translates to a total of 247.5*10E6 attempts. Wire Length estimates :

12 An efficient and commonly used method to estimate the wire length is the semiperimeter method. The wire length is approximated by half the perimeter of the smallest bounding rectangle enclosing all the pins. For Manhattan wiring, this method gives the exact wire length for all two terminal or three terminal nets. This method of wiring estimate is used in Timber Wolf. Conclusion : The combinatorial optimization problems like placement can very effectively solved by simulated annealing and applying effective constraints to the algorithms. The TimberWolf package is the first to take advantage of the hill-climbing probabilistic approach of the simulated annealing. With effective cost functions, move criterion and cooling schedule we can achieve high area efficiency. The TimberWolf package has given better results that industry standard placers from AMI (American Microsystems Inc) and Intel. With dynamic criterions and parallel implementations the time and area efficacy can be further increased. References : 1. VLSI Physical Design Automation by Sadiq Sait and Habib Youssef 2. TimberWolf 3.2 : A New Standard Cell Placement and Global Routing Package By Carl Sechen and Alberto Sangiovanni-Vincentelli 3. Simulated Annealing Algorithms : An Overview by R. A. Rutenbar 4. VLSI Cell Placement Techniques by K. Shahookar and P. Mazumder