EN2911X: Reconfigurable Computing Lecture 13: Design Flow: Physical Synthesis (5)
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1 EN2911X: Lecture 13: Design Flow: Physical Synthesis (5) Prof. Sherief Reda Division of Engineering, rown University Fall 09
2 Summary of the last few lectures System Specification previous lectures this lecture SW partitioning HW traditional compiler class compile compiling Verilog link synthesis executable image mapping & packing place & route download to board configuration file
3 Embedding a digital circuit to FPG fabric [Maxfield 04] Programmable logic element 1. Mapping decomposes the circuit into logic sections and flip-flops such that each section fits into a K-LUT LE. 2. Packing groups LEs into clusters so that each cluster fits into a L 3. Placement determines the position of each cluster into the Ls of the island style FPG 4. Routing determines the exact routes for the communicating LE/ Ls What are the objectives/metrics that these algorithms should pursue?
4 1. Mapping finds a covering for a given circuit using K-LUT Map to a LUT in a L [Figure form Cong FPG 01]
5 covering example [From Ling et al. DC 05] There could be many possible covering? Which one should be picked?
6 2. Packing How can we decide which LEs should go together in the same logic cluster? Possible method (VPCK): Construct each cluster sequentially Start by choosing seed LE for the cluster Then greedily selects the LE which shares the most inputs and outputs with the cluster being constructed Repeat the procedure until greedily until the cluster is full or the number of inputs exceed the limit I Can addition of a LE to a cluster reduces the number of distinct inputs?
7 3. Placement Placement assigns an exact position or L for each cluster in the input netlist Suppose you start with a random placement, how can you improve it? Possible algorithm: - Pick a pair of cells and swap their locations if this leads to reduction in WL What s wrong with the previous greedy algorithm? It can simply get stuck in a local optimal result WL results local optimal global optimal possible placements
8 Simulated annealing allows us to avoid getting trapped in a local minima Modified algorithm Generate a random move (say a swap of two cells) calculate the chance in WL (ΔL) due to the move if the move results in reduction (ΔL < 0) then accept else reject with probability 1-e -ΔL/T local optimal WL results possible placements global optimal T (temperature) controls the rejection probability Initially, T is high (thus avoiding getting trapped early in a local minima) then the temperature cools down in a scheduled manner; at the end, the rejection probability is 1 With the right slow-enough cooling scheduling, simulated annealing is guaranteed to reach the global optimal
9 How do the cooling scheduling and corresponding cost functions look like? [source: I. Markov]
10 Placement before & after simulated annealing [using VPR tool]
11 4. Routing ssign exact routes for each wire in the given circuit in the FPG fabric such that no two wires overlap General idea: Order the wires according to some criteria Sequentially route each wire using shortest path algorithms (after removing the resources consumed from preceding routed wires)
12 Maze routing s t s t Problem: Find the shortest path for a 2-pin wire from s to t grid cell capacity is full grid cell still has available tracks Speed ups are possible using * search algorithms and other I search techniques
13 Impact of Net Ordering bad net ordering may unnecessarily increase the total wirelength or even yield the chip unroutable! Example: Two nets and first then (Good order) first then (ad order) Length in placement Timing criticality
14 When a route for a net can t be found then rip up and re-route Cannot route C So rip-up and route C first. Finally route. C C C C C C [Example from Prof. D. Pan Lecture]
15 VPR. fter routing fter placement fter placement and routing You probably saw similar layouts from the Quartus II tool
16 Finally programming the FPG
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