The Design and Optimization for the TDMA Network-on-Chip

Transcription

1 第 29 卷第 2 期 计算机辅助设计与图形学学报 Vol. 29 No 年 2 月 Journal of Computer-Aided Design & Computer Graphics Feb 时分复用片上网络的设计与优化 许胜 1,2), 付斌章 1,2)*, 陈明宇 1,2) 1,2), 张立新 1) ( 中国科学院计算技术研究所计算机体系结构国家重点实验室北京 ) 2) ( 中国科学院大学北京 ) (fubinzhang@ict.ac.cn) : 针对 流水线 调度的时分复用片上网络受限于复杂的全局时钟网络以及低的网络利用效率等问题, 提出一种时分复用片上网络设计方案. 首先建立专属的调度控制网络, 有效地避免了对全局时钟网络的依赖 ; 然后提出最小空余带宽分配算法, 合理地选择调度周期和分配带宽 ; 最后利用双重交换仲裁设计, 使用网络中空闲时间片来提升性能. 实验结果表明, 与之前的工作 SurfNoC 相比, 文中方案能够在严格保证 应用域 之间无干扰的同时取得更好的网络性能. : 片上网络 ; 时分复用 ; 流水线 调度 ; 双重交换仲裁 :TP302 The Design and Optimization for the TDMA Network-on-Chip Xu Sheng 1,2), Fu Binzhang 1,2)*, Chen Mingyu 1,2), and Zhang Lixin 1,2) 1) (State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing ) 2) (University of Chinese Academy of Sciences, Beijing ) Abstract: In this paper, we propose a design of TDMA network-on-chip, which avoids the dependency on the global clock synchronization and enhances the efficiency of network resource utilization. Firstly, a dedicated control network is used to remove the requirement of global clock synchronization. Secondly, an allocation algorithm for the minimum free bandwidth is presented to make reasonable bandwidth allocation and find the optimal scheduling period. Finally, the double switch allocator is adopted to promote the network performance by leveraging idle time slots. Experimental results show that the proposed method achieves higher performance, while still preserving performance isolation, in comparison with the previous SurfNoC. Key words: network-on-chip; time division multiplexing; pipeline schedule; double switch allocator VLSI,.,, (networks on chip, NoC) [1]. NoC, [2 3] ; (quality of service, QoS) [4],. NoC, QoS,. (time division multiple access, TDMA) [5] NoC, ( ) : ; : 基金项目 : (2016YFB ); (XDA ); ( , , , ); (YBCB ). 许胜 (1984 ),,, CCF, ; 付斌章 (1982 ),,,,, CCF,, ; 陈明宇 (1972 ),,,,, CCF, ; 张立新 (1971 ),,,,,.

2 366 计算机辅助设计与图形学学报第 29 卷,., ( ), TDMA NoC.,,, [6 7]., TDMA (virtual channels, VC) (TDMA- VC),, [6 7].., TDMA-VC,, [8] ;,,,, [9]. QoS TDMA NoC, NoC,.,. 1. 3,. S D, DOR, X. T=1, S X,, T=2 D Y., 2, T=5 Y,, Y R., 6,,, 2. 1 流水线调度 Mesh Torus, (dimension order routing, DOR). DOR,,.,., 中 [6]. 1.1 维度流水线调度 [6]..,,. 1 9 mesh, 全局流水线调度 [7].,,, ;,,. 2 9 mesh, 4, 0, 1, S D, 2. 2, S D,,, (T=4),,.,,

3 第 2 期, 等 : 367. D, P, L,, 2( P L) mod D 0. 表 1 零负载延迟计算公式 TDMA HP H ( D 1) HP (( n 1) 2)( D 1) HP 2( D 1) 2 流水线调度实现机制 2,, 2, (P+L) 2(P+L).,. 1.3 全局流水线调度 3. 1) TDMA.. 2).,,. 3).,. 1 3,, H, P ( ), D ( ), n., TDMA NoC,, ;,,,,,. 2.1 流水线调度控制网络 mesh, 2 C0 C15. C0 2, C15 2. C0, C15.., 2., 2, C0 C15,, ;. 3 1). 4, (schedule table, ST) 2 Counter0 Counter1( 2 ). ST,

4 368 计算机辅助设计与图形学学报第 29 卷,.. 4 2). 5, : a.. b.. c.. 5,, (switch allocator, SA). SA. 2.2 最小空余带宽分配算法, ;,,.,,. Psarras [7],. D 0, D 1 D 2 1/2, 1/3 1/7, 16,, ~3., ;, ;,. 表 2 带宽分配方案 D 0 D 1 D 2 1 8(1/2) 6(3/8) 2(1/8) 1/24 2 8(1/2) 5(5/16) 3(3/16) 5/ (7/16) 6(3/8) 3(3/16) 1/24+5/ (1/2) 2(1/3) 1(1/6) 1/42,, :. T( N), D[N]( Di [] 1 ). N i 1. S[N], free. Step1.. if N i 1 D [] i T T then for i from 1 to N // Si [] Di [] T ; else k=t; // for i from 1 to N //, 0 1 if Di [] T 0 then Si [] Di [] T else S[i]=1; k = S[i]; sort ( DN [ ] T SN [ ]) // for i from 1 to N // if k 0 and Di [] T Si [] 0 then + +S[i] and k; else break; Step2.. for i from 1 to N if Si [] T Di [] 0then free S[] i T D[] i ; return free/t; //.

5 第 2 期, 等 : 369 T, N,. 2,, 4 : 6, B 1 =3(1/2), B 2 =2(1/3) B 3 =1(1/6)., 3, 1/ 双重交换仲裁架构设计,,. 由于 SA,,,.,,,,., SA,, 2 : 1).,. 2),. 2,. 6,, SA1, SA2 6. SA1 SA2. SA1 0,, SA2. SA2. 3 实验及结果分析 3.1 实验, Booksim [10],. 8 8 mesh, 32, 5; 4, 1 ; seperable (input-first). DOR, 1 flit. 3,. 表 3 应用域的配置信息 ,.,,.,. : Baseline.. TDMA.,. SurfNoC....

6 370 计算机辅助设计与图形学学报第 29 卷 3.2 结果分析 a 32 4., SurfNoC, Baseline TDMA.,, (head-of-line, HOL). Baseline, SurfNoC 12.8%., SurfNoC, Baseline ;,,, Baseline,.,,. 7b,, SurfNoC TDMA ;,, 32, SurfNoC 10.7, TDMA c,, ; 32, SurfNoC 25.2% PARSEC [11], Gem5 [12] traces. 2, A0 A1. A0 uniform random, A1, traces. TDMA SurfNoC, A0 0.05( ) 0.25( ), A1., A0, A1 A0. 8 TDMA.,, TDMA 29.4%, SurfNoC 7 8 PARSEC

7 第 2 期, 等 : %;, A1, SurfNoC, TDMA 19.4%, SurfNoC 3.2% SurfNoC,,.., 8, 2 8 = , 8, 16, 6.25%.,. SurfNoC,,.,,, [13]., 32, 2.0%., SurfNoC., 2, 4 4 (4, 4 ). 9,, SurfNoC.,, NoC. 9 4 结语 TDMA NoC,., ;,,.,. 参考文献 (References): [1] Dally W J, Towles B. Route packets, not wires: on-chip interconnection networks[c] //Proceeding of the 38th Annual Design Automation Conference. New York: ACM Press, 2001: [2] Lu Chao, Chen Yunji, Liu Shaoli. A novel routing algorithm for 2D Mesh network-on-chip leveraging global information[j]. Journal of Computer-Aided Design & Computer Graphics, 2014, 26(6): (in Chinese) (,,. Mesh [J]., 2014, 26(6): ) [3] Fu Binzhang, Han Yinhe, Li Huawei, et al. Building resilient NoC with reconfigurable routing algorithm[j]. Journal of Computer-Aided Design & Computer Graphics, 2011, 23(3): (in Chinese) (,,,. [J]., 2011, 23(3): ) [4] Goossens K, Azevedo A, Chandrasekar K, et al. Virtual execution platforms for mixed-time-criticality systems: The Comp- SOC architecture and design flow[j]. ACM SIGBED Review, 2013, 10(3): [5] Goossens K, Dielissen J, Radulescu A. Æthereal network on chip: concepts, architectures, and implementations[j]. IEEE Design & Test of Computers, 2005, 22(5): [6] Wassel H M G, Gao Y, Oberg J K, et al. SurfNoC: a low latency and provably non-interfering approach to secure networks-onchip[j]. ACM SIGARCH Computer Architecture News, 2013, 41(3): [7] Psarras A, Seitanidis I, Nicopoulos C, et al. Phasenoc: TDM scheduling at the virtual-channel level for efficient network traffic isolation[c] //Proceeding of the Design, Automation & Test in Europe Conference & Exhibition. San Jose: EDA Consortium, 2015: [8] Plana L A, Furber S B, Temple S, et al. A GALS infrastructure for a massively parallel multiprocessor[j]. IEEE Design & Test of Computers, 2007, 24(5): [9] Liu S T, Lu Z H, Jantsch A. Highway in TDM NoCs[C] //Proceedings of the 9th International Symposium on Networks- on-chip. New York: ACM Press, 2015: Article No.15 [10] Jiang N, Balfour J, Becker D U, et al. A detailed and flexible cycle-accurate network-on-chip simulator[c] //Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software. Los Alamitos: IEEE Computer Society Press, 2013: [11] Bienia C, Kumar S, Singh J P, et al. The PARSEC benchmark suite: characterization and architectural implications[c] //Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques. New York: ACM Press, 2008: [12] Binkert N, Beckmann B, Black G, et al. The gem5 simulator[j]. ACM SIGARCH Computer Architecture News, 2011, 39(2): 1-7 [13] Kim M M, Davis J D, Oskin M, et al. Polymorphic on-chip networks[c] //Proceeding of the 35th Annual International Symposium on Computer Architecture. Los Alamitos: IEEE Computer Society Press, 2008: