Developing Applications for HPRCs

Transcription

1 Developing Applications for HPRCs Esam El-Araby The George Washington University

2 Acknowledgement Prof.\ Tarek El-Ghazawi Mohamed Taher ARSC SRC SGI Cray 2

3 Outline Background Methodology A Case Studies Conclusions 3

4 Background Application Design Life-Cycle 0 Structured steps that take an application from concept to a working implementation Current Limitations 0 Scope and Focus are on chip-level designs, e.g. IP Designs as previously FPGAs were used as glue logic 0 Ad hoc Process Need 0 Formal and Quantitative System-Level Methodology useful for: Considering interactions among system modules Exploring the design space to select an efficient operating point 4

5 Outline Background Methodology Case Studies Conclusions 5

6 Methodology Developing Applications with a specific reconfigurable machine in mind results in hard-to-port applications Alternatively, one can break down the design process into: a machine independent step followed by a mapping step to the target architecture 6

7 Methodology Steps Provide Basic Problem Description Develop the application virtual architecture Construct a DFG for the underlying application Provide time alignment to construct a basic linear pipeline Recursively breakdown DFG to develop a virtual architecture Determine the virtual architecture superscalar degree based on: Real-Time throughput constraint Resources usage constraint Map the virtual architecture onto the target architecture Exploit maximum concurrency through I/O and computational overlapping Determine the system minimum partitionability 7

8 1) & 2) Develop the Application Virtual Architecture (Determine Application Pipeline Depth, L) Processing Elements (L s ) Pipeline Depth (L Stages) T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T 17 T T 1 T 2 T 3 T 6 T 5 T 9 T 4 T 7 T 8 T 12 T 11 T 15 Time (L) ) DFG 2.2) Equivalent Space-Time Diagram T 13 T 10 T 14 T 16 T 17 T 18 S 9 S 8 S 7 S 6 S 5 S 4 S 3 S 2 S 1 T 3 T 1 T 2 T 6 T 5 T 4 T 9 T 8 T 7 T 13 T 12 T 11 T 10 T 15 T 14 T 16 T 17 T 18 Time (L) ) Equivalent Linear Pipeline 8

9 2.4) Develop the Superscalar (Determine the Virtual Architecture Superscalar Degree, K) Assumptions: 0 Linear (Static) Pipelines Parameters: 0 Pipeline Latency (L), i.e. pipeline depth 0 Degree of superscalability (K) 0 Real-Time throughput constraint Consumed data size per clock cycle (B comp-in ) Input data size per clock cycle (B in ) Total input data size (D) Total number of tasks (N total ) Number of tasks per pipeline (N) 0 Resources usage constraint Maximum resources usage per pipeline stage (U stage )» Application requirement of the i-th resource for stage j (Z i,j )» Total available size of the i-th resource in the FPGA (Z i,fpga )» Number of resource types in the FPGA (N resources ) (e.g. CLBs, registers, shift registers, multipliers, BRAMs,. etc.) 9

10 2.4) Develop the Superscalar (cnt d) Resource Usage Boundary Kmax L! K S < 1 S = 1 S > 1 Real-Time Throughput Boundary S ( L! ) K L L! 1 " # # Operating Point 10

11 3) Virtual Architecture Target Architecture (Hypothetical Reference Architecture and System Parameters) Application parameters 0 Computations bandwidth Input bandwidth (B comp-in ), data consumption rate Output bandwidth (B comp-out ), data production rate Data production-consumption factor (β); i.e. β>1 for data-producing applications, β<1 for dataconsuming applications, and β=1 for dataprocessing applications 0 Partitionability of data and processing Input partitionability (n in ) Output partitionability (n out ) Processing partitionability (n c ) Machine Parameters 0 I/O transfers bandwidth Input bandwidth (B in ), data feed rate Output bandwidth (B out ), data output rate 0 I/O channel multiplicity Input multiplicity (K in ) Output multiplicity (K out ) 0 Channel-Overlapping factor (V) 11

12 3) Virtual Architecture Target Architecture (cnt d) (System Model of Interacting Superscalar Pipelines) Exploit maximum concurrency through I/O and computational overlapping Determine the System Minimum Partitionability 12

13 Outline Background Methodology Case Studies 0 Wavelet-Based Hyperspectral Dimension Reduction SRC 0 DWT SRC, SGI RASC, Cray XD1 0 Image Registration SRC 0 Cloud Detection SRC 0 Smith-Waterman SRC, Cray XD1 0 Cryptography (RC5, IDEA) SRC Conclusions 13

14 Applications and Machines Parameters Applications Parameters (Requirements) Machines Parameters (Characteristics) 14

15 The Application (Hyperspectral Dimension Reduction) Multi-Spectral Imagery 10 s of bands (MODIS 36 bands, SeaWiFS 8 bands, IKONOS 5 bands) Hyperspectral Imagery 100 s s of bands (AVIRIS 224 bands, AIRS 2378 bands) 0 Challenges (Curse of Dimensionality) 0 Solution On-Board Dimension Reduction 0 Needs Higher performance Lower form / wrap factors Higher flexibility Esam El-Araby, GWU Multispectral / Hyperspectral Imagery Comparison HPRCs ARSC HPRC Workshop 15

16 The Application: Wavelet Dimension Reduction (Techniques) Principal Component Analysis (PCA): 0 Most Common Method Dimension Reduction 0 Complex and Global computations: difficult for parallel processing and hardware implementations 0 Does Not Preserve Spectral Signatures Multi-Resolution Wavelet Decomposition of Each Pixel 1-D Spectral Signature (Preservation of Spectral Locality) Wavelet-Based Dimension Reduction*: 0 Simple and Local Operations 0 High-Performance Implementation 0 Preserves Spectral Signatures * S. Kaewpijit, J. Le Moigne, T. El-Ghazawi, Automatic Reduction of Hyperspectral Imagery Using Wavelet Spectral Analysis, IEEE Transactions on Geoscience and Remote Sensing, Vol. 41, No. 4, April, 2003, pp

17 The Application: Wavelet Dimension Reduction (1 - Application Description) 17

18 2) Develop the Application Virtual Architecture (DFGs and Time-Alignment) X DWT L 1 -L 5 IDWT Y 1 -Y 5 CORR HIST Space (Number of Processing Elements) 4 Histogram 3 Correlator 2 IDWT 1 DWT Output Data Flow Time 2.1) Highest-Level DFG 2.2) Equivalent Space-Time Diagram 18

19 2) Develop the Application Virtual Architecture (Determine Application Pipeline Depth, L) 19

20 2) Develop the Application Virtual Architecture (Construct a Basic Linear Pipeline) 20

21 2.4) Develop the Superscalar (cnt d) (Determine the Virtual Architecture Superscalar Degree, K) Operating Point 21

22 3) Virtual Architecture Target Architecture (Determine the System Minimum Partitionability) Performance Design Space 22

23 Experimental Setup and Measurements Scenarios Measurements Scenario 23

24 Execution Profiles 24

25 Speedup (SRC-6E P3 vs. Intel Xeon P4-1.8 GHz) Salinas' Speedup SRC-P3 (No Overlapping) SRC-P3 (Overlapping) Level of Decomposition 25

26 Speedup (SRC-6E P4 vs. Intel Xeon P4-1.8 GHz) Salinas' Speedup SRC-P4 (No Overlapping) SRC-P4 (Overlapping) Level of Decomposition 26

27 Outline Background Methodology Case Studies 0 Wavelet-Based Hyperspectral Dimension Reduction SRC 0 DWT SRC, SGI RASC, Cray XD1 0 Image Registration SRC 0 Cloud Detection SRC 0 Smith-Waterman SRC, Cray XD1 0 Cryptography (RC5, IDEA) SRC Conclusions 27

28 Multi-Resolution DWT Decomposition (Mallat Algorithm) The input image is first convolved along the rows by the two filters L and H and decimated along the columns by two resulting in two "column-decimated" images L and H Each of the two images, L and H, is then convolved along the columns by the two filters L and H and decimated along the rows by two This decomposition results into four images, LL, LH, HL and HH The LL image is taken as the new input to perform the next level of decomposition Image Size = 512 X 512 pixels 28

29 Multi-Resolution DWT Decomposition (cnt d) 29

30 Image Registration SRC-6 Two Techniques 0 Exhaustive search 0 Iterative refinement Similarity Measures 0 correlation 0 Normalized cross-correlation Expensive One of the best similarity measures 0 Statistical correlation 0 Match filters 0 Phase-correlation 0 Sum of absolute differences 0 Root mean square 0 Masked correlation Two engines 0 79% usage of the chip resources (slices) High Accuracy 0 Floating-point arithmetic Extrapolated Higher Performance 0 Larger data sizes 0 Many optimization techniques such as data streaming 30

31 Automatic Cloud Cover Assessment (ACCA) (Theory and Algorithms) Theory is based on the observation that clouds are: 0 Highly reflective (in the visible, near- and mid- IR bands) 0 Cold (in the thermal bands) Algorithms 0 Landsat 4 & 5 ACCA Threshold based - 3 filters Trouble with cold, highly reflective landscapes (e.g. tundra, deserts) Imperfect snow/cloud discriminator Insensitive to warm clouds Performance suffers at low sun elevation angles 0 MODIS (Moderate Resolution Imaging Spectroradiometer) Threshold based - 13 filters Parameters differ depending on the time of day and the pixel ecosystem Supporting ecosystem maps and land/sea masks are required 0 Landsat 7 ETM+ (Enhanced Thematic Mapper) ACCA Threshold based - 8 filters A compromise between Landsat 4&5 and MODIS Two-pass approach» Pass one Fixed thresholds» Pass two Adaptive thresholds based on statistical analysis of pass one results 31

32 Automatic Cloud Cover Assessment (cnt d) Total Execution Time m sec Xeon 2.8GHz Floating Point 1X Fixed Point 1X Floating Point 2X Floating Point 2X Comp./8X Data Fixed Point 8X Speed Up Xeon 2.8GHz Floating Point 1X Fixed Point 1X Floating Point 2X Floating Point 2X Comp./8X Data Fixed Point 8X 32

33 Bioinformatics Sequence Alignment (The Smith-Waterman Algorithm) Genomic comparison and alignment algorithm 0 Similar to BLAST, but 10x slower 0 Provably optimum- the gold standard for alignment algorithms 0 Based on Dynamic Programming * Rate = (FPGA freq.) X (cycles/cell) X (# SWPEs) Two-step process 0 Create scoring matrix and find maximum score forward pass 0 Work back to determine alignment traceback Opteron Implementation (SSEARCH34) * Million Cell Updates Per Second (CUPS) * CUG 05, New Mexico, May

34 Conclusions A two-step structured and efficient methodology for developing portable application designs has been demonstrated The first step is to develop an ideal architecture for the problem in the absence of hardware resource and structural constraints 0 The virtual architecture is used to derive the application requirement parameters The second step is to map this virtual (portable) architecture onto the target reconfigurable machine 0 The machine characteristics are also measured using an artificial workloads that optimize its performance After all it can be a science! 34