An Implementation Comparison of an IDEA Encryption Cryptosystem on Two General-Purpose Reconfigurable Computers

Transcription

1 An Implementation Comparison of an IDEA Encryption Cryptosystem on Two General-Purpose Reconfigurable Computers Allen Michalski 1, Kris Gaj 1, Tarek El-Ghazawi 2 1 ECE Department, George Mason University 2 ECE Department, The George Washington University

2 What is a Reconfigurable Computer? Microprocessor system Reconfigurable processor system µp... µp FPGA... FPGA µp memory... µp memory FPGA memory... FPGA memory IO Interface Interface IO

3 Characteristic Features composed of traditional microprocessors and FPGAs programming does not require knowledge of hardware design permit run-time reconfiguration of FPGAs SRC-6E Examples: Starbridge HC-36

4 SRC and Star Bridge Systems

5 SRC Hardware Architecture 528 MBs P3 P3 (1GHz) (1GHz) 8000 MBs 528 MBs 8000 MBs L2 L2 PCI up Board 800 MBs MIOC 800 MBs Computer Memory (1.5 GB) DDR Interface SNAP 800 MBs FPGA 1 XC2V6000 Control FPGA XC2V MBs (6x64 bits) On-Board Memory (24 MB) 4800 MBs (6x 64 bits) 2400 MBs (192 bits) (108 bits) 4800 MBs (6x 64 bits) (108 bits) ½MAP Board FPGA 2 XC2V6000 Chain Ports 2400 MBs

6 SRC Compilation Process Application sources Macro sources.c or.f files.vhd or.v files HDL sources.v files Logic synthesis µp Compiler MAP Compiler Netlists.ngo files Object files.o files.o files Place & Route Linker Application executable.bin files Configuration bitstreams

7 SRC Programming Model Program in C or Fortran Main program Function_1(a, d, e) Function_2(d, e, f) Function_1 Macro_1(a, b, c) Macro_2(b, d) Macro_2(c, e) Function_2 Macro_3(s, t) Macro_1(n, b) Macro_4(t, k) FPGA contents after the Function_1 call FPGA b Macro_2 d a Macro_1 c Macro_2 e

8 Star Bridge Hardware Architecture Xeon (1GHz) L2 Computer Memory (4 GB) MIOC Xeon (1GHz) L2 PCI µp Board 64 PCIX Bus Bus Controler XC2V XPOINT XC2V Clock 94 Bus Router XC2V User PE(x1x5) XC2V6000 User PE(x2x6) XC2V6000 User PE(x3x7) XC2V6000 User PE(x4x8) XC2V6000 Single Quad FPGA Board Connector J1-J10 (560 PIN IO)

9 Star Bridge Processing Element (PE) 16x MT46V64M4 DDR RAM 3 64M x 64 bit 0.5 GB 64 data address 16x MT46V64M4 DDR RAM 4 64M x 64 bit 0.5 GB User PE XC2V x MT46V64M4 DDR RAM 1 64M x 64 bit 0.5 GB address data 64 16x MT46V64M4 DDR RAM 2 64M x 64 bit 0.5 GB

10 Sheets Library Object

11 Star Bridge Compilation Process User input Graphical User Interface VIVA Netlists.ngo files Xilinx Place & Route.bin files Application executable Configuration bitstreams

12 SRC vs. Star Bridge Design Entry SRC Software Hardware HDL Data Flow HLL Star Bridge Software Hardware porting EDIF COM objects Increased productivity Increased capability to describe parallel execution

13 High-Throughput Secret-Key Encryption with IDEA

14 IDEA International Data Encryption Algorithm, published in 1990 Conventional encryption algorithm suggested to replace DES Largest use in PGP Block cipher 128 bit key 64 bit data block 8 ½ rounds

15 IDEA Three Basic Operations X K Y = X K Y = X + K mod 2 16 X K X K Y = X K mod ( ) where 0 represents 2 16

16 Fully Pipelined Architecture of IDEA rounds 14 pipeline stagesround 116 pipeline stages New input & new output every clock cycle

17 High-Throughput Encryption.... M i+2 M i+1 M i K 0 IDEA C i+2 C i+1 C i

18 High-Throughput Secret-Key Encryption in SRC

19 Data Flow During Encryption µp P Board µp P Board Xeon µp Xeon µp Xeon µp Xeon µp L2 L2 MAP Board L2 L2 MIOC Control Chip (6x) Control Chip (6x) MIOC PCI Slot Private Memory SNA P On-Board Memory (24 MB) On-Board Memory (24 MB) SN A P Private Memory PCI Slot (6x) (6x) User Chip User Chip User Chip User Chip

20 Execution Time (ms) IDEA Encryption 5 MB 10 MB 15 MB 20 MB Amount Data Processed MAP Data Transfer Out MAP FPGA Processing MAP Data Transfer In MAP FPGA Config

21 Problems Execution time dominated by - Configuration of the MAP FPGA and - Data transfer between the System Common Memory and On-Board-Memory Configuration time hiding techniques Preloading the configuration before execution Flip-flopping FPGAs during reconfiguration

22 Comparison of SRC MAP vs. Pentium 4 Data Processed 5MB 10MB 15MB 20MB SRC (sec) Pentium 4 (sec) SRC Speed-up Pentium 4 implementation based on the Crypto library

23 IDEA in VIVA

24

25 Star Bridge Results Hardware interface and software support for efficient data transfer still under development Unable to measure end-to-end time without file io, data transfer in time, or data transfer out time MAP FPGA Processing Time the same as on the SRC machine

26 Results Comparison

27 IDEA Compilation Time SRC Synthesis 2 min Mapping 4 min Placing and Routing 1 hr 34 min Star Bridge Viva compilation time ~36 hrs Mapping 14 min Placing and Routing 1 hr 25 min

28 IDEA Use of FPGA Resources Xilinx XC2V % 50% 40% 30% 20% 10% 0% SRC VHDL Only SRC VHDL-C VIVA CLB Slices Slice FFs LUTs

29 IDEA Timing FPGA Processing Time the same in both systems The same number of clock cycles The same maximum clock frequency 100 MHz The End-to-End time much smaller in SRC, but the exact comparison impossible because of the early development stage of the Star Bridge hardware and software

30 Conclusions Both platforms are unique expansions of existing paradigms FPGA data transfer is a significant bottleneck for IO intensive applications, such as encryption SRC hardware and software more advanced Star Bridge system still in early development state Two order-of-magnitude speedup versus softwareonly solution for the high-speed IDEA encryption on SRC