GAN-OPC: Mask Optimization with Lithography-guided Generative Adversarial Nets

Transcription

1 GAN-OPC: Mask Optiization with Lithography-guided Generative Adversarial Nets Haoyu Yang Shuhe Li Yuzhe Ma ABSTRACT Bei Yu Mask optiization has been a critical proble in the VLSI design flow due to the isatch between the lithography syste and the continuously shrinking feature sizes. Optical proxiity correction (OPC) is one of the prevailing resolution enhanceent techniques (RETs) that can significantly iprove ask printability. However, in advanced technology nodes, the ask optiization process consues ore and ore coputational resources. In this paper, we develop a generative adversarial network (GAN) odel to achieve better ask optiization perforance. We first develop an OPC-oriented GAN flow that can learn target-ask apping fro the iproved architecture and objectives, which leads to satisfactory ask optiization results. To facilitate the training process and ensure better convergence, we also propose a pre-training procedure that jointly trains the neural network with inverse lithography technique (ILT). At convergence, the generative network is able to create quasi-optial asks for given target circuit patterns and fewer noral OPC steps are required to generate high quality asks. Experiental results show that our flow can facilitate the ask optiization process as well as ensure a better printability. 1 INTRODUCTION With the VLSI technology node continuously shrinking down, the ask optiization process becoes a great challenge for designers [1, 2]. Conventional ask optiization process is illustrated in Figure 1, where OPC ais at copensating lithography proxiity effects through correcting ask pattern shapes and inserting assist features. OPC ethodologies include odel-based techniques [3 5] and inverse lithography-based technique (ILT) [6 8]. In odel-based OPC flows, pattern edges are fractured into segents which are then shifted/corrected according to atheatical odels. A high printability ask can then be obtained with sub-resolution assist features (SRAF) [9]. Awad et al. [3] propose a pattern fidelity aware ask optiization algorith that optiizes core polygons by siultaneously shifting adjacent segentations. Su et al. [5] significantly accelerate the OPC flow by extracting representative process corners while aintaining a good wafer iage quality. However, odel-based OPC flows are highly restricted by their solution space and hence lacking in reliability for coplicated designs. On the other hand, ILTs iniize the error between the wafer iage and the target with lithography constraints. Because ILTs conduct pixel-based optiization on layout asks, they Perission to ake digital or hard copies of all or part of this work for personal or classroo use is granted without fee provided that copies are not ade or distributed for profit or coercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for coponents of this work owned by others than ACM ust be honored. Abstracting with credit is peritted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific perission and/or a fee. Request perissions fro perissions@ac.org. DAC 18, June 24 29, 2018, San Francisco, CA, USA 2018 Association for Coputing Machinery. ACM ISBN /18/06... $ Evangeline F. Y. Young fyyoung@cse.cuhk.edu.hk Target Mask Wafer Iage OPC Litho- Etch Figure 1: Conventional OPC flow and lithography process, where OPC is very tie consuing. are expected to offer better lithography contour quality. Recently, Ma et al. [8] adopt ILT to siultaneously perfor ask optiization and layout decoposition that brings a better solution of ultiple patterning ask design. Although the odel-based ethod and the ILT-based ethod behave well on a variety of designs, they take the wafer iage as a ask update criterion in each iteration of the OPC process. In other works, ultiple rounds of lithography siulation are indispensable in the optiization flow which is drastically tie consuing. The explosion of achine learning techniques have draatically changed the way to solve design for anufacturability probles. Recently, both shallow and deep learning odels have been successfully utilized to estiate ask printability accurately and efficiently (e.g. [10 13]). There are also several attepts on ask optiization probles that contain ore coplex regression or classification procedures. Matsunawa et al. [14] conduct segent based pattern correction with hierarchical Bayes odel. Gu et al. [15] introduce discrete cosine transfor (DCT) features and linear regression to predict fragent oveent. [16, 17] incorporate artificial neural networks to estiate ask patterns. However, existing achine learning odels can only perfor pixel-wise or segent-wise ask calibration that is not coputationally efficient. Generative adversarial networks (GAN) has shown powerful generality when learning the distribution of a given dataset [18]. The basic optiization flow of GAN contains two networks interacting with each other. The first one is called generator that takes rando vectors as input and generates saples which are as uch closer to the true dataset distribution as possible. The second one is called discriinator that tries to distinguish the true dataset fro the generated saples. At convergence, ideally, the generator is expected to generate saples that have the sae distribution as true dataset. Inspired by the generative architecture and the adversarial training strategy, in this work we propose a lithography-guided generative fraework that can synthesis quasi-optial ask with single round forwarding calculation. The quasi-optial ask can be further refined by few steps of noral OPC engine. It should be noted conventional GAN cannot be directly applied here, due to the following two reasons. (1) Traditional GANs are trained to iic a dataset distribution which is not enough for the target-ask apping procedure. (2) Copensation patterns or segent oveents in the ask are derived based upon a large area of local patterns (e.g n 2 ) that brings uch training pressure on the generator. In accordance with these probles, we develop custoized GAN training strategies for the purpose of ask optiization. Besides, since

2 layout topology types are liited within specific area, we autoatically synthesis local topology patterns based on size and spacing rules. The benefits of the artificial patterns are twofold: (1) we avoid to train the neural network with large iages and facilitate the training procedure significantly; (2) autoatically designed patterns are distributed uniforly and to soe extent alleviate the over-fitting proble. Observing that ost ILTs update the ask through steepest descent that resebles the training procedure in neural networks, we connect an ILT structure with the generative networks and pre-train the generator through backpropagating the lithography error to neuron weights. With the above pre-training phase, the generative odel converges faster than training fro rando initialized neuron weights. The ain contributions of this paper are listed as follows: We synthesis training topologies to enhance the coputational efficiency and alleviate the over-fitting proble. We propose an ILT-guided pre-training flow to initialize the generator which can effectively facilitate the training procedure. We design new objectives of the discriinator to ake sure the odel is trained toward a target-ask apping instead of a distribution. Experiental results show that our fraework can significantly facilitate the ask optiization procedure as well as generating ask that has better printability under noinal condition. The rest of the paper is organized as follows. Section 2 lists basic concepts and proble forulation. Section 3 discusses the details of the fraework and training strategies. Section 4 presents experiental results, followed by conclusion in section Section 5. 2 PRELIMINARIES In this section, we will discuss soe preliinaries of ask optiization and the generative adversarial nets. Throughout this paper, we use Z t to represent the target layout, M for the ask, I for the aerial iage, Z for the wafer iage, G for the generator output, D for the discriinator output and p x for soe distribution. We also denote operations and as convolution and eleent-wise product, respectively. In order to avoid confusion, all the nors are calculated with respect to flattened vectors. Hopkins theory of the partially coherence iaging syste has been widely applied to atheatically analyze the ask behavior of lithography [19]. Because the Hopkins diffraction odel is coplex and not coputational-friendly, [20] adopts the singular value decoposition (SVD) to approxiate the original odel with a weighted suation of coherent systes. I = w k M h k 2, (1) N 2 k=1 where h k and w k are the k th kernel and its weight. As suggested in [7], we pick the N h th order approxiation to the syste. Equation (1) becoes, N h I = w k M h k 2. (2) k=1 We pick N h = 24 in our experients. The lithography intensity corresponds to the exposure level on the photo resist, which controls the final wafer iage with a photo resit odel (Equation (3)). { 1, if I(x,y) Ith, Z(x,y) = (3) 0, if I(x,y) < I th. Mask quality is evaluated through the fidelity of its wafer iage with respect to the target iage. Edge placeent error (EPE), bridge Bad EPE Good EPE Bridge Neck Figure 2: Different types of defects. Sae lithography iages result in different EPE violation counts due to different choices of easureent points. Soe defects are not detectable through erely checking edge placeent errors. and neck are three ain types of defect detectors that are adopted in a layout printability estiation flow. As shown in Figure 2, EPE easures horizontal or vertical distances fro given points (i.e. OPC control points) on target edges to lithography contours. Neck detector checks the error of critical diensions of lithography contours copared to target patterns, while bridge detector ais to find unexpected short of wires. Note that unlike EPE violations, bridge and neck defects can appear in any directions. Because EPE violations could happen with good critical diension and neck or bridge occurs with sall EPE, none of these defect types individually can be an ideal representation of ask printability. Considering the objective of ask optiization is to ake sure the reaining patterns after lithography process are as close as target patterns, we pick the squared L 2 error as the etric of lithography quality since a saller L 2 indicates a better wafer iage quality. Definition 1 (Squared L 2 Error). Let Z t and Z as target iage and wafer iage respectively, the squared L 2 error of Z is given by Z t Z 2 2. Following above terinologies, we define the ask optiization proble as follows. Proble 1 (Mask Optiization). Given a target iage Z t, the objective of the proble is generating the corresponding ask M such that reaining patterns Z after lithography process is as close as Z t or, in other word, iniizing the squared L 2 error of lithography iages. 3 GAN-OPC FRAMEWORK A classical GAN architecture coprises a generator and a discriinator. The generator accepts rando vectors z p z as the input and generates saples G(z; W д ) that follows soe distribution p д, where G is a convolutional neural networks paraeterized by W д. The discriinator acts as a classifier that distinguishes G(z; W д ) and the instance drawn fro a data distribution p d. The output D(x; W d ) represents the probabilities of x drawn fro p d and p д. It should be noted that the original settings are not well suitable for the ask optiization proble. In this section, we will introduce the details of our fraework including OPC-oriented GAN architecture and advanced training strategies. 3.1 Design Fro the previous discussion we can notice that the generator learns a distribution of a given dataset, which is originally designed as a apping function G : p z p д, where p z is a distribution that input vectors are drawn and p д denotes the distribution of the training set. The objective of the generator is to generate saples that deceive the discriinator as uch as possible, as in Equation (4): ax E z pz [log(d(g(z)))], (4) which axiizes the log-likelihood of the discriinator giving predictions that generated saples are real. Correspondingly, the generator

3 Target Target & Mask Encoder Discriinator 0.2 coprises a deconvolutional architecture that casts 1D vectors back to 2D iages through stacked deconvolution operations, as shown in Figure 3. Our fraework, however, is expected to perfor ask optiization on given target circuit patterns and obviously violates the deconvolutional architecture. To resolve this proble, we design a generator based on auto-encoder [21] which consists of an encoder and a decoder subnets. As depicted in Figure 4, the encoder is a stacked convolutional architecture that perfors hierarchical layout feature abstractions and the decoder operates in an opposite way that predicts the pixel-based ask correction with respect to the target based on key features obtained fro the encoder. Discriinator Design The discriinator is usually an ordinary convolutional neural networks that perfor classification to distinguish the generated saples fro the given data saples as shown in Equation (5): ax Ex pd [log(d(x))] + Ez pz [log(1 D(G(z)))]. (5) In this work, the discriinator predicts whether an input instance is the generated ask M or the reference ask M. However, the discriinator in Equation (5) is necessary but not sufficient to ensure generator to obtain a high quality ask (Figure 3). Consider a set of target patterns Z = {Zt,i, i = 1, 2,..., N } and a corresponding reference ask set M = {Mi, i = 1, 2,..., N }. Without loss of generality, we use Zt,1 in the following analysis. Suppose the above GAN structure has enough capacity to be well trained, the generator outputs an ask G(Zt,1 ) that optiizes the objective function as in Equation (4). Observe that log(d(g(zt,1 ))) reaches its axiu value as long as G(Zt,1 ) = Mi, i = 1, 2,..., N. Decoder Real Figure 3: Conventional GAN architecture. 3.2 Discriinator Fake (6) Therefore, an one-one apping between the target and the reference ask cannot be guaranteed with current objectives. To address above concerns, we propose a new classification schee that predicts positive or negative labels on target-ask pairs that inputs of the discriinator will be either (Zt, G(Zt )) or (Zt, M ), as illustrated in Figure 4. Clai that G(Zt ) M at convergence with new discriinator. We still assue enough odel capacity and training tie for convergence. The discriinator now perfors prediction on targetask pairs instead of asks. Because only pairs {Zt,i, Mi } are labeled as data, the generator can deceive the discriinator if and only if G(Zt,i ) Mi, i = 1, 2,..., N, where N is the total nuber of training instances. Mask 0.8 Bad Good Mask Mask Figure 4: The proposed GAN-OPC architecture. 3.3 GAN-OPC Training Based on the OPC-oriented GAN architecture in our fraework, we tweak the objectives of G and D accordingly, ax EZt Z [log(d(zt, G(Zt )))], axezt Z [log(d(zt, M ))] + EZt Z [1 log(d(zt, G(Zt )))]. (7) (8) In addition to facilitate the training procedure, we iniize the differences between generated asks and reference asks when updating the generator as in Equation (9). in EZt Z M G(Zt ) n, (9) where n denotes the ln nor. Cobining (7), (8) and (9), the objective of our GAN odel becoes in ax EZt Z [1 log(d(zt, G(Zt ))) + M G(Zt ) nn ] G D + EZt Z [log(d(zt, M ))]. (10) Previous analysis shows that the generator and the discriinator have different objectives, therefore the two sub-networks are trained alternatively, as shown in Figure 5(a) and algorith 1. In each training iteration, we saple a ini-batch of target iages (line 2) and their ground truth asks (line 3); Gradients of both the generator and the discriinator are initialized to zero (line 4); A feed forward calculation is perfored on each sapled instances (lines 6); We calculate the loss of the generator and the discriinator on each instance in the inibatch (lines 7 8); We obtain the accuulated gradient of losses with respect to neuron paraeters (lines 9 10); Finally the generator and the discriinator are updated by descending their ini-batch gradients (lines 12 13). Note that in Algorith 1 we convert the in-ax proble in Equation (10) into two iniization probles such that gradient ascending operations are no longer required to update neuron weights. Algorith 1 differs fro traditional GAN optiization flow on the following aspects. (1) The generator plays as a apping function fro target to ask instead of erely a distribution, therefore the gradient of L 2 loss is back-propagated along with the inforation fro the discriinator. (2) The discriinator functions as an alternative of ILT engine that deterines only the quality of generated asks without any calibration operations. Besides, our cobined input ensures that the discriinator will ake positive prediction if and only if the generated

4 Algorith 1 GAN-OPC Training 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: 11: 12: Feed-forward for nuber of training iterations do Saple target clips Z {Zt,1, Zt,2,..., Zt, }; Wд 0, Wd 0; for each Zt Z do M G(Zt ; Wд ); M Groundtruth ask of Zt ; lд log(d(zt, M)) + α M M 22 ; ld log(d(zt, M)) log(d(zt, M )); lд ld Wд Wд + ; Wd Wd + ; Wд Wд Wд Wд Wд ; Wd Wd Wd ; (b) Figure 5: (a) GAN-OPC training and (b) ILT-guided pre-training. Although with OPC-oriented techniques, GAN is able to obtain a fairly good perforance and training behavior, it is still a great challenge to train the coplicated GAN odel with satisfactory convergence. Observing that ILT and neural network training stage share siilar gradient descent techniques, we develop an ILT-guided pre-training ethod to initialize the generator, after which the alternative ini-batch gradient descent is discussed as a training strategy of GAN optiization. The ain objective in ILT is iniizing the lithography error through gradient descent. (11) where Zt is the target and Z is the wafer iage of a given ask. Because ask and wafer iages are regarded as continuously valued atrices in the ILT-based optiization flow, we apply translated sigoid functions to ake the pixel values close to either 0 or 1. 1, 1 + exp[ α (I It h )] 1 Mb =, 1 + exp( β M) Z= layer while neural weights are updated as follows, Wд = Wд Wд, (15) where Wд is accuulated gradient of a ini-batch of instances and is the ini-batch instance count. Because Equation (15) is naturally copatible with ILT, if we create a link between the generator and ILT engine, the wafer iage error can be back-propagated directly to the generator as presented in Figure 5. The generator pre-training phase is detailed in Algorith 2. In each pre-training iteration, we saple a ini-batch of target layouts (line 2) and initialize the gradients of the generator Wд to zero (line 3); The ini-batch is fed into the generator to obtain generated asks (lines 5). Each generated ask is loaded into the lithography engine to obtain a wafer iage (line 6); The quality of wafer iage is estiated by Equation (11) (lines 7); We calculate the gradient of lithography error E with respect to the neural networks paraeter Wд through the E M chain rule, i.e., (line 8) ; Finally, Wд is updated following the M Wд gradient descent procedure (line 10). Algorith 2 ILT-guided Pre-training (12) 1: 2: (13) 3: 4: where It h is the binarization threshold, Mb is the incopletely binarized ask, while α and β control the steepness of relaxed iages. Cobine Equations (1) (3), Equations (11) (13) and the analysis in [6], we can derive the gradient representation as follows, E =2α β Mb (1 Mb ) M (((Z Zt ) Z (1 Z) (Mb H )) H+ ((Z Zt ) Z (1 Z) (Mb H)) H ), Real Fake LithoSiulator ILT-guided Pre-training E = Zt Z 22, Discriinator (a) ask is uch close to the ground truth, which also helps train the generator better. 3.4 Back-propagetion 5: 6: 7: 8: 9: 10: (14) where H is the conjugate atrix of the original lithography kernel H. In traditional ILT flow, the ask can be optiized through iteratively descending the gradient until E is below a threshold. The objective of ask optiization proble indicates the generator is the ost critical coponent in GAN. Observing that both ILT and neural network optiization share siilar gradient descent procedure, we propose a jointed training algorith that takes advantages of ILT engine, as depicted in Figure 5(b). We initialize the generator with lithography-guided pre-training to ake it converge well in the GAN optiization flow thereafter. The key step of neural network training is back-propagating the training error fro the output layer to the input 11: for nuber of pre-training iterations do Saple target clips Z {Zt,1, Zt,2,..., Zt, }; Wд 0; for each Zt Z do M G(Zt ; Wд ); Z LithoSi(M) Equations (2) (3) E Z Zt 22 ; E M Wд Wд + ; Equation (14) M Wд Wд Wд Wд ; Equation (15) Copared to the training towards ground truth (i.e., directly backpropagate the ask error to neuron weights), ILT-guided pre-training provides step-by-step guidance when searching for a solution with high quality, which reduces the possibility of the generator being stuck at local iniu region in an early training stage. Because ILT contains coplicated convolutions and atrix ultiplications that are coputational expensive, we approxiate the pre-training stage through back-propagating errors of interediate asks, which guides the generator towards optiality. We only adopt the ILT engine in the pre-training stages and replace it with the discriinator in the ain training stage where the generator is optiized in an adversarial style.

5 Table 1: The design rules used. Ite Min Size (n) M1 Critical Diension 80 Pitch 140 Tip to tip distance 60 L2 Loss GAN-OPC PGAN-OPC ILT Engine ,000 2,000 3,000 4,000 5,000 6,000 7,000 Training Step Figure 7: Training curves of GAN-OPC and PGAN-OPC. Figure 6: GAN-OPC flow: generator inference and ILT refineent. 4 EXPERIMENTAL RESULTS The generative adversarial network for ask optiization is ipleented based on Tensorflow [22] library and tested on single Nvidia Titan X. The lithography engine is based on the lithosi_v4 package fro ICCAD 2013 CAD Contest [23], which also provides ten industrial M1 designs on 32n design node. As a type of deep neural networks, GAN can be hardly well trained with only ten instances. To verify our fraework, we synthesize a training layout library with 4000 instances based on the design specifications fro existing 32n M1 layout topologies. We adjust the wire sizes to ake sure the shapes in synthesized layouts are siilar to those in the given benchark. To generate experiental cells, all the shapes are randoly placed together based on siple design rules, as detailed in Table 1. In addition, ost generative odels have shown obvious weakness in iage details, which akes it extreely hard to optiize iages with size Therefore, we perfor 8 8 average pooling on layout iages before feeding the into the neural networks. In the generation stage we adopt siple linear interpolation to convert the layout iages back to their original resolution. The proposed GAN-OPC flow is illustrated in Figure 6, where we first feed target patterns into the generator and obtain the quasi-optial asks, followed by refineent through an ILT engine. To verify the effectiveness of ILT-guided pre-training algorith, we record training behaviors of two GANs which are denoted by GAN-OPC and PGAN- OPC. Here GAN-OPC and PGAN-OPC denote GAN-OPC flow without generator pre-training and GAN-OPC flow with ILT-guided pretraining, respectively. The training procedure is depicted in Figure 7, where x-axis indicates training steps and y-axis is L 2 loss between generator outputs and ground truth asks, as in Equation (9). The training tie for both GAN and PGAN are around 10 hours on our platfor. Although L 2 loss of GAN-OPC drops slightly faster before 3000 iterations, the training curve shows that PGAN-OPC is a ore stable training procedure and converges to a lower loss. Besides, it takes uch ore efforts for GAN-OPC to search a direction to descending the gradient fast, while the training loss of PGAN-OPC drops soothly and converges at a lower L 2 loss than GAN-OPC, which indicates ILTguided pre-training indeed facilitates ask-optiization-oriented GAN training flow. We will also show that PGAN-OPC exhibits better ask optiization results in the following section. In the second experient, we optiize the ten layout asks in ICCAD 2013 contest benchark [23] and copare the results with previous work. Figure 8 depicts ask optiization results in coparison with an ILT engine [7], and the quantitative results are listed in Table 2. Here the wafer iages are calculated fro the siulation tool (lithosi_v4) in the contest [23]. Note that all the GAN-OPC and PGAN-OPC results are refined by an ILT engine which generates final asks to obtain wafer iages. Colun L 2 is the squared L 2 error between the wafer iage and the target iage under noinal condition. Colun PVB denotes the contour area variations under ± 2% dose error. It is notable that GAN-OPC significantly reduces squared L 2 error of wafer iages under the noinal condition by 9% and with the ILT-guided pre-training, squared L 2 error is slightly iproved and PVB is further reduced by 1%. Because we only focus on the optiization flow under the noinal condition and no PVB factors are considered, our ethod only achieves coparable PVB areas aong ten test cases. Additionally, feed-forward coputation of GAN only takes 0.2s for each iage which is ignorable, therefore runtie of our flow is alost deterined by ILT refineents. Coluns RT (s) lists the total ask optiization tie of [7], GAN-OPC and PGAN-OPC. For ost benchark cases, GAN-OPC and PGAN-OPC show a earlier stop at a saller L 2 error and, on average, reduce the optiization runtie by ore than 50%. For ost test cases, [7] exhibits a saller PV band area possibly because the printed iages are ore likely to have large wafer iage CD and shorter wire length, which akes asks suffer less proxiity effects while inducing bridge or line-end pull back defects, as shown in Figure 9. 5 CONCLUSION In this paper, we have proposed a GAN based ask optiization flow that takes target circuit patterns as input and generates quasi-optial asks for further ILT refineent. We analyze the specialty of ask optiization proble and design OPC-oriented training objectives of GAN. Inspired by the observation that ILT procedure resebles gradient descent in back-propagation, we also develop an ILT-guided pre-training algorith that initializes the generator with interediate ILT results, which significantly facilitates the training procedure. Experiental results show that our fraework not only accelerates ILT but also has the potential to generate better asks through offering better starting points in ILT flow. ACKNOWLEDGMENTS This work is supported in part by The Research Grants Council of Hong Kong SAR (Project No. CUHK ). REFERENCES [1] D. Z. Pan, B. Yu, and J.-R. Gao, Design for anufacturing with eerging nanolithography, IEEE TCAD, vol. 32, no. 10, pp , [2] B. Yu, X. Xu, S. Roy, Y. Lin, J. Ou, and D. Z. Pan, Design for anufacturability and reliability in extree-scaling VLSI, Science China Inforation Sciences, pp. 1 23, [3] A. Awad, A. Takahashi, S. Tanaka, and C. Kodaa, A fast process variation and pattern fidelity aware ask optiization algorith, in Proc. ICCAD, 2014, pp [4] J. Kuang, W.-K. Chow, and E. F. Y. Young, A robust approach for process variation aware ask optiization, in Proc. DATE, 2015, pp [5] Y.-H. Su, Y.-C. Huang, L.-C. Tsai, Y.-W. Chang, and S. Banerjee, Fast lithographic ask optiization considering process variation, IEEE TCAD, vol. 35, no. 8, pp , [6] A. Poonawala and P. Milanfar, Mask design for optical icrolithography an inverse iaging proble, IEEE Transactions on Iage Processing, vol. 16, no. 3, pp , [7] J.-R. Gao, X. Xu, B. Yu, and D. Z. Pan, MOSAIC: Mask optiizing solution with process window aware inverse correction, in Proc. DAC, 2014, pp. 52:1 52:6.

6 (a) (b) (c) (d) (e) Figure 8: Result visualization of PGAN-OPC and ILT. Coluns correspond to ten test cases fro ICCAD 2013 CAD contest. Rows fro top to botto are: (a) asks of [7]; (b) asks of PGAN-OPC; (c) wafer iages by asks of [7]; (d) wafer iages by asks of PGAN-OPC; (e) target patterns. Table 2: Coparison with state-of-the-art ILT solver. Bencharks ID Area (n2 ) Average Ratio (a) L2 ILT [7] PVB (n2 ) RT (s) L2 GAN-OPC PVB (n2 ) RT (s) L2 PGAN-OPC PVB (n2 ) RT (s) (b) Figure 9: Soe wafer iage details of (a) [7] and (b) PGAN-OPC. [8] Y. Ma, J.-R. Gao, J. Kuang, J. Miao, and B. Yu, A unified fraework for siultaneous layout decoposition and ask optiization, in Proc. ICCAD, 2017, pp [9] R. Viswanathan, J. T. Azpiroz, and P. Selva, Process optiization through odel based SRAF printing prediction, in SPIE Advanced Lithography, vol. 8326, [10] T. Matsunawa, J.-R. Gao, B. Yu, and D. Z. Pan, A new lithography hotspot detection fraework based on AdaBoost classifier and siplified feature extraction, in Proc. SPIE, vol. 9427, [11] H. Zhang, B. Yu, and E. F. Y. Young, Enabling online learning in lithography hotspot detection with inforation-theoretic feature optiization, in Proc. ICCAD, 2016, pp. 47:1 47:8. [12] H. Yang, L. Luo, J. Su, C. Lin, and B. Yu, Ibalance aware lithography hotspot detection: a deep learning approach, JM3, vol. 16, no. 3, p , [13] H. Yang, J. Su, Y. Zou, B. Yu, and E. F. Y. Young, Layout hotspot detection with feature tensor generation and deep biased learning, in Proc. DAC, 2017, pp. 62:1 62:6. [14] T. Matsunawa, B. Yu, and D. Z. Pan, Optical proxiity correction with hierarchical bayes odel, JM3, vol. 15, no. 2, p , [15] A. Gu and A. Zakhor, Optical proxiity correction with linear regression, IEEE TSM, vol. 21, no. 2, pp , [16] R. Luo, Optical proxiity correction using a ultilayer perceptron neural network, Journal of Optics, vol. 15, no. 7, p , [17] S. Choi, S. Shi, and Y. Shin, Machine learning (ML)-guided OPC using basis functions of polar fourier transfor, in Proc. SPIE, vol. 9780, [18] I. Goodfellow, J. Pouget-Abadie, M. Mirza, B. Xu, D. Warde-Farley, S. Ozair, A. Courville, and Y. Bengio, Generative adversarial nets, in Proc. NIPS, 2014, pp [19] H. Hopkins, The concept of partial coherence in optics, in Proceedings of the Royal Society of London A: Matheatical, Physical and Engineering Sciences, vol. 208, no The Royal Society, 1951, pp [20] N. B. Cobb, Fast optical and process proxiity correction algoriths for integrated circuit anufacturing, Ph.D. dissertation, University of California at Berkeley, [21] J. Masci, U. Meier, D. Cireşan, and J. Schidhuber, Stacked convolutional autoencoders for hierarchical feature extraction, Artificial Neural Networks and Machine Learning ICANN 2011, pp , [22] M. Abadi, P. Barha, J. Chen, Z. Chen, A. Davis, J. Dean et al., TensorFlow: A syste for large-scale achine learning, in Proc. OSDI, 2016, pp [23] S. Banerjee, Z. Li, and S. R. Nassif, ICCAD-2013 CAD contest in ask optiization and benchark suite, in Proc. ICCAD, 2013, pp