A Low-cost Memory Architecture with NAND XIP for Mobile Embedded Systems

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1 A Low-cost Meory Architecture with XIP for Mobile Ebedded Systes Chanik Park, Jaeyu Seo, Sunghwan Bae, Hyojun Ki, Shinhan Ki and Busoo Ki Software Center, SAMSUNG Electronics, Co., Ltd. Seoul , KOREA {ci.park, pelican, sunghwan.bae, zartoven, shinhank, ABSTRACT flash eory has becoe an indispensable coponent in obile ebedded systes because of its versatile features such as non-volatility, solid-state reliability, low cost and high density. Even though flash eory is gaining popularity as data storage, it can be also exploited as code eory for XIP (execute-in-place). In this paper, we present a new eory architecture which incorporates flash eory into an existing eory hierarchy for code execution. The usefulness of the proposed approach is deonstrated with real ebedded workloads on a real prototyping board. Categories and Subject Descriptors B.3.2 [Meory Structures]: Design Styles Cache eories; D.4.2 [Operating Systes]: Storage Manageent Secondary storage; B.6.1 [Logic Design]: Design Styles Meory control and access. General Ters Algoriths, Measureent, Perforance, Design Keywords Meory architecture, XIP, Priority-based caching 1. INTRODUCTION A eory architecture design is a ain concern to ebedded syste engineers since it doinates the cost, power and perforance of obile ebedded systes. The typical eory architecture of obile ebedded systes consists of ROM for initial bootstrapping and code execution, RAM for working eory, and flash eory for peranent data storage. In particular, eerging eory technology, the flash eory, is becoing an indispensable coponent in obile ebedded systes due to its versatile features: non-volatility, solid-state reliability, low power consuption, etc. Perission to ake digital or hard copies of all or part of this work for personal or classroo use is granted without fee provided that copies are not ade or distributed for profit or coercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific perission and/or a fee. CODES+ISSS 3, October 1-3, 23, Newport Beach, California, USA Copyright 23 ACM /3/1 $5.. The ost popular flash eory types are NOR and. NOR flash is particularly well suited for code storage and execute-inplace (XIP) 1 applications, which require high-speed rando access. While flash provides high density and low-cost data storage, it is not applicable to XIP applications due to the sequential access architecture and long access latency Table 1 shows different characteristics of various eory devices. Mobile SDRAM has advantages in perforance but requires high power consuption over other eories. There is a tradeoff between low power SRAM and fast SRAM in ters of power consuption, perforance and cost. In non-volatile eories, NOR flash provides fast rando access speed and low power consuption, but the cost of NOR flash is high copared to flash. Even though flash shows long rando read latency, it has advantages in power consuption, storage capacity, and erase/write perforance in contrast to NOR flash. Table 1. Characteristics of various eory devices. The values in the table were calculated based on SAMSUNG 23 eory data sheets [1-2]. Current (A) Meory $/Gb idle active Mobile SDRAM Low power SRAM Fast SRAM NOR Rando Access (16bit) read write erase 9ns 55ns 1ns 2ns 1.1us 9ns N.A 55ns N.A 1ns N.A 21.5us 1.2 sec 2.5us 2 s Even though flash eory is widely used for data storage in obile ebedded systes, flash eory researches for code storage are hardly found in industry or acadeia. In this paper, we present a new eory architecture for flash eory to provide XIP functionality. With XIP functionality in flash, the cost of the eory syste can be reduced since the flash can be used not only as data storage but also as code storage for execution. As a result, we can obtain cost-efficient eory systes with reasonable perforance and power consuption. The basic idea of our approach is to exploit the locality of code access pattern and ipleent a cache controller for repeatedly accessed codes. The prefetching cache is used to hide eory latency resulting fro eory access. In this paper we concentrate on code execution even though data eory is also an iportant aspect of eory architecture. There are two ajor 1 XIP is the execution of an application directly fro the flash eory instead of having to download the code into the systes RAM before executing it. 138

2 contributions in this paper. First, we deonstrate that the XIP is feasible in real-life systes through a real hardware and coercial OS environent. Second, we apply highly optiized caching techniques geared toward the specific features of Flash. The rest of this paper is organized as follows. In the next section, we describe the trend of eory architecture in obile ebedded systes. Section 3 reviews related work in acadeia and industry. In Sections 4 and 5, we present our new eory architecture based on XIP. In Section 6, we deonstrate the proposed architecture with real workloads on a hardware prototyping board and evaluate cost, perforance and power consuption over existing eory architectures. Finally, our conclusions and future work are drawn in Section Motivational Systes: Mobile Systes Voice-centric 2G MCU Data-centric 2.5G MCU 3G & SartPhone MCU NOR SRAM OS NOR SRAM App 1 (data) (code) App 2 Data (a) (b) (c) OS App 1 App 2 DRAM Figure 1. The eory architectures for obile systes Figure 1 shows the trend in eory architecture of obile systes. The first approach is to use NOR for code storage and SRAM for working eory as shown in Figure 1(a). It is appropriate for low-end phones, which require ediu perforance and cost. However, as obile systes evolve into data centric and ultiedia-oriented applications, storage with high perforance and huge capacity has becoe necessary. The second architecture (Figure 1(b)) sees to eet the requireents in ters of storage capacity through flash eory, however its perforance is not enough to accoodate 3G applications which consist of real-tie ultiedia applications. In addition, the increased nuber of coponents increases syste cost. The third architecture (Figure 1(c)) eliinates NOR flash eory and uses only flash eory by using a shadowing 2 technique. Copying all code into RAM offers the best perforance possible, but contributes to the slow boot process. A large aount of DRAM is necessary to hold both the OS and the applications. The higher power consuption fro power hungry DRAM eory is another proble for battery-operated systes. Thus, it is iportant to investigate an efficient eory syste in ters of cost, perforance and power consuption. 3. RELATED WORK In the past, researchers have exploited NOR flash eory as caches for agnetic disks due to its low power consuption and high-speed characteristics. envy focused on developing a persistent storage architecture without agnetic disks [7]. Fred et al showed that NOR flash eory can reduce energy consuption by an order of agnitude, copared to agnetic disk, while providing good read perforance and acceptable write perforance [9]. B. Marsh et al exained the ipact of using NOR flash eory as a second-level file syste buffer cache to reduce power consuption and file access latency on a obile coputer [8]. Li-Pin et al investigated the perforance issue of flash eory storage subsystes with a striping architecture, which uses I/O parallelis [1]. In industry [5], XIP is ipleented using sall size of buffer and I/O interface conversion, but the XIP area is liited to boot code. The OS and application codes should be copied to syste eory at booting tie. In suary, even though several researches have been ade to obtain the axiu perforance and low power consuption fro data storage, few efforts to support XIP in flash are found in acadeia or industry. 4. XIP ARCHITECTURE In this section, we describe XIP architecture. First, we look into the structure of flash eory and illustrate the basic ipleentation of XIP based on caching echanis. 4.1 BACKGROUND A flash eory consists of a fixed nuber of blocks, where each block has 32 pages and each page consists of 512 bytes ain data and 16 bytes spare data as shown in Figure 2. Read/write operation is perfored on page basis. In order to read a page, coand and address are inputted to flash eory through I/O pins. After a fixed delay tie, selected page is loaded into data and spare registers. Spare data can be used to store auxiliary inforation such as bad block identification and error correction code (ECC) for associated ain data. flash eories are subject to a condition called bad block, in which a block cannot be copletely erased or cannot be written due to partial or 2-bit errors. Bad blocks ay exist in flash eory when shipped or ay occur during operation. The syste design ust be able to ask out the invalid blocks via address apping. For exaple, as shown in Figure 3, if block 2 and 5 are initially bad, the bad block nubers and the replaceent block nubers are recorded in a bad block ap table. The bad block ap table is anaged by hardware or software. 1 Block =32 pages I/O bus 512 bytes 16 bytes Main data Data register Spare data Spare register Figure 2. Structure of flash eory 2 During syste booting tie, entire code iage is copied fro peranent storage into systes RAM for execution. 139

3 In order to ipleent the XIP, we should consider the following points. Average eory access tie Worst case handling Bad block anageent The perforance of eory syste is easured by average access tie [3]. In order to ipleent XIP functionality, the average access tie of flash eory should be coparable to that of other eories such as NOR, SRAM and SDRAM. Though average eory access tie is a good etric for perforance evaluation, worst-case handling, or cache iss handling is another proble in practical view since ost obile systes such as cellular phones include tie-critical interrupt handling for call processing. For instance, if the tie-critical interrupt occurs during cache iss handling, the syste ay not satisfy the given deadline and to ake it worse, it ay lose data or connection. Another consideration in XIP is to anage bad blocks because bad blocks cause discontinuous eory space, which is intolerable for code execution. 4.2 BASIC IMPLEMENTATION DATA [:7] ADDR [:12] CE#,OE#,WE# BUSY# Syste interface Cache (SRAM) Boot Loader Prefetch Control logic Flash interface Figure 3. XIP controller The proposed architecture consists of a sall aount of SRAM for cache, interface conversion logic, the control logic and flash eory as shown in Figure 3. Interface conversion is necessary to connect the I/O interface of flash eory to eory bus. For cache echanis, direct ap cache with victi cache is adopted based on Jouppi s work in [4] with optiization for flash. In [4], the victi cache is accessed on a ain cache iss; if the address hits the victi cache, the data returned to the CPU and at the sae tie it is prooted to the ain cache; the replaced block in the ain cache is oved to the victi cache, therefore perforing a swap. If the victi cache iss also occurs, flash eory access is perfored; the incoing data fills the ain cache, and the replaced block will be oved to the victi cache. In next section, we odify the above swap algorith using syste eory and page address translation table (PAT). The prefetching cache is used to hide eory latency resulting fro eory access. Several hardware prefetching techniques can be found in literature [13]. In our case, prefetching inforation is analyzed through profiling process and the prefetching inforation is stored in spare data at code iage building tie. 5. INTELLIGENT CACHING: PRIORITY- BASED CACHING Though the basic ipleentation is suitable for application code which shows its spatial and teporal localities, it ay be less effective in systes code which has a coplex functionality, a large size, and interrupt-driven control transfers aong its procedures [14]. Torrellas et al. presented that the operating syste has the characteristics which large sections of its code are rarely accessed and suffers considerable interference within popular execution paths [14]. For exaple, periodic tier interrupt, rarely-executed special-case code and plenty of loopless code disrupt the localities. On the other hand, real-tie applications should be retained as long as possible to satisfy the tiing constraints 3. In this paper, we distinguish the different cache behavior between syste and application codes, and adapt it to the page-based architecture. We apply profile-guided static analysis of code access pattern. Main cache Victi A Page address translation table Control C A B C H L H B SRAM/SDRAM Data bus Address bus Figure 4. Priority-based cache architecture We can divide code pages into three categories depending on their access cost: high priority, id priority and low priority pages. Even though the priority can be deterined by various objectives, we set the priority to pages based on the nuber of references to pages and their criticality. For exaple, if a specific page is referenced ore frequently or has tie critical codes, it is classified as a high-priority page and should be cached or retained in cache to reduce the later access cost in case that the page is in flash eory. OS-related code, syste libraries and realtie applications have high-priority pages. On the other hand, id-priority page is defined to be noral application code which is handled by noral caching policy. Finally, low-priority page corresponds to sequential code such as initialization code, which is rarely executed. PAT is introduced to reap pages in bad blocks to pages in good blocks and to reap requested pages to swapped pages in syste eory. We illustrate the caching echanis in detail in Figure 4. First, when page A with highpriority is requested, it is cached fro flash to ain cache. Next, when page B is requested fro the CPU, it should be oved to ain cache or syste eory. Here assuing that page B is in conflict with page A, page B is oved to syste eory (SRAM/SDRAM) since page B is low priority page ( L in spare area of flash eory eans low-priority). At the sae tie, PAT is updated so that later access to page B is referred to syste eory. Again, when page C is requested and in conflict with page A, page C replaces page A and page A is discarded fro ain cache since C s priority is high. The evicted page A is 3 In this paper, real-tie applications indicate ultiedia applications with soft real-tie constraints. 14

4 oved to victi cache. In suary, on flash s page deand, the controller discards or swaps existing cache page according to the priority inforation stored in spare area data. The detail algorith is explained in Figure 5. Another usage of spare area data is to store prefetching inforation based on profiling inforation gathered during code execution. This static prefetching technique iproves eory latency hiding without iss penalty fro iss-prediction at run-tie. Cache Cache siulator cache paraeters Pattern analysis Meory Trace eory addresses Priority Caching (address) { page = convert(address); if (isinpat(page)) ain eory hit; else if(isinmaincache(page)) Cache hit; else if(isinvicticache(page)) Victi hit; else { // iss, fetch a page fro flash eory } } page_priority = [page].priority; if (cache[page%cache_size].priority ==HIGH) [page] ain eory; else if (cache[page%cache_size].priority == MID) { cache[page%cache_size] victi; [page] cache[page%cache_size]; } else [page] cache[page%cache_size]; Figure 5. Priority-based cache algorith 6. EXPERIMENTAL SETUP This section presents our experiental environent. Our environent consists of a prototyping board, our in-house cache siulator with pattern analysis and a real workload, or PocketPC[6]. The prototyping board has ARM9-based icrocontroller, SRAM, SDRAM, NOR flash and eories as shown in Figure 6. It is used not only to ipleent a real cache configuration on FPGA but also to gather eory address trace fro running applications for cache siulator. The specification of ain processor and flash eory is shown in Table 2. The cache siulator explores various paraeters such as iss rate, replaceent policy, associativity and cache size based on eory traces fro the prototyping board. The real ebedded workload, PocketPC supports XIP-enabled iage based on the existing ROMFS file systes in which each application can be directly executed without being loaded into RAM. Table 2. The specification of the prototyping board Paraeter Configuration CPU clock L1 Icache 2 MHz 64 way, 32byte line, 8KB Bus width 16 bit = 1 word read initial latency 1 us/512byte serial read tie 5 ns/word SRAM read tie 1 ns/word SDRAM read tie 12 ns/4word NOR read tie 21 ns/4word SRAM FPGA SDRAM ARM9-based Processor Figure 6. Prototyping board for XIP PocketPC 6.1 PERFORMANCE MODELING In general, the eory syste perforance is evaluated by the average access tie: Average eory access tie = hit tie + iss rate * iss penalty. (1) Hit tie is the tie to fill the L1 cache (32byte line) and the iss penalty is the tie to fill the L2 cache fro flash eory. The total energy consued by the syste is the su of energies consued by syste coponents such as processor, bus, eory and the DC-DC converter. In this paper, we concentrate on the energy consuption of the processor and eory syste: E syste = ECPU + Eeory. (2) The energy consuption of CPU is divided into two parts: E CPU = PCPU _ active TCPU _ active + PCPU _ idle TCPU _ idle. (3) T CPU_active is assued to be constant regardless of eory syste since the nuber and execution tie of instructions are fixed. Thus, we are concerned about T CPU_idle which is proportional to off-chip eory access tie. In eory case, the nuber of accesses to the eory is directly proportional to energy consuption. The unit access energy consuption can be estiated fro the active power specified in the data sheet [1-2]: E eory = Eaccess N access. (4) The cost of eory syste is coputed fro paraeters shown on Table 1: N Cost eory _ syste = density unit cost + Cost controller. (5) The Cost controller is coputed based on the synthesis result in Xilinx FPGA: totally 27, gates including 4KB and using offchip SRAM for TAG and cache eory. Finally, booting ties are easured using real-tie easureent tools. 141

5 6.2 EXPERIMENTAL RESULTS In Figure 7, we copare the iss ratio over various configuration paraeters such as associativity, replaceent policy and cache size. We collected address traces fro PocketPC while we were executing various applications such as Media Player and MP3 player since they are popular ebedded ultiedia applications which involve real-tie requireents. Note that the cache size is the ost iportant factor to affect iss ratio as shown in Figure 7. Miss Ratio( Direct ap FIFO LRU rando FIFO LRU rando FIFO LRU 2-w ay 4-w ay 8-w ay Replace ent/associativity Figure 7. Associativity with different replaceent policies and cache sizes versus iss ratio Miss Ratio ( Average Meory Access Ti (CPU cycles) rando Cache Line Size (Bytes) (a) Cache Line Size (Bytes) Energy (ns*w) Cache Line Size (B y te s ) (c) Figure 8. Cache line size versus (a) iss ratio, (b) access tie per 32-byte and (c) energy consuption To analyze the optial cache line size in XIP cache, siulation has been done with the eory trace which is gathered fro the prototyping board. The line size of 256-byte shows better nubers in average eory access tie and energy consuption over all other cache sizes as shown in Figure 8. Therefore, the line size of XIP controller is deterined to be 256-byte hereafter. Average Meory Access Ti e (cycle) Energy (ns* W ) XIP (basic) (a) XIP (priority) SDRAM shadowing ArchitecturalChoices XIP(basic) (b) XIP (priority) SDRAM shadow ing ArchitecturalChoices NOR XIP NOR XIP Figure 9. Overall perforance coparison of different eory architectures: (a) average eory access tie and (b) energy consuption. (b) 142

6 Architectural Choices NOR XIP SDRAM Shadowing XIP (basic) XIP (priority) Coponents NOR(64MB)+SDRAM(32MB) (64MB)+SDRAM(64MB) XIP(64MB)+SRAM(256KB) Controller+SDRAM(32MB) XIP(64MB)+SRAM(64KB) Controller+SDRAM(32MB) Booting Tie (sec) Cost ($) Figure 1. Overall booting tie and cost coparison of different eory architectures. Figure 9 and 1 show overall perforance coparison aong different eory architectures based on our prototyping results. NOR XIP architecture (NOR+SDRAM) shows fast boot tie and low power consuption at high cost. Even though SDRAM shadowing architecture ( + SDRAM) achieves high perforance, it suffers fro a relatively long booting tie and inefficient eory utilization. Finally, our approach XIP shows reasonable booting tie, perforance and power consuption with outstanding cost efficiency. Two ipleentations of XIP (basic and priority) are also copared. The XIP (basic) is coposed of 256KB cache and 4KB victi cache. On the other hand, the XIP (priority) has 64KB cache, 4KB victi and 2KB PAT. The XIP (priority) has advantage of cache size reduction with the assistance of syste eory and priority based caching. 6.3 Worst Case Handling Even though XIP offers an efficient eory syste, it ay suffer fro worst-case handling, naely cache iss handling. A straightforward solution is to hold the CPU until the requested eory page arrives. This can be ipleented using wait/ready signals handshaking ethod. However, the iss penalty, 35us 4 is not trivial tie especially in case that a fast processor is used. Besides CPU utilization proble, if the tiecritical interrupt request occurs to the syste, the interrupt ay be lost because the processor is waiting for eory s response. In order to solve this proble, a syste-wide approach is needed. First, OS should handle the cache iss as a page fault as in virtual eory anageent. The CPU also should supply abort function to restart the requested instruction after cache iss handling. In analytical approach view, task tiing analysis and schedulability test will be helpful in the doain of real-tie[12]. 7. CONCLUSIONS We presented the new low cost eory architecture with XIP functionality which enables flash eory to be used as code storage as well as data storage. In order to hide a long read access latency, we applied the priority-based caching echanis geared for specific features. As a result, we can accoplish cost and power efficient eory systes with reasonable perforance and booting tie. As future work, copiler s assistance will be helpful to iprove XIP in ebedded eory architectures. Code packing and positioning will be achieved in near future. 4 It is calculated as su of initial delay (1us) + page read (512 x 5ns) REFERENCES [1] Sasung Electronics Co., Flash Meory & SartMedia Data Book, 22. [2] [3] J.L. Hennessy and D.A. Patterson, Coputer Architecture: A Quantitative Approach, 2 nd edition, Morgan Kaufan Publishers, [4] N. Jouppi, Iproving Direct-Mapped Cache Perforance by the Addition of a Sall Fully-Associative Cache and Prefetch Buffers, ISCA-17:ACM/IEEE International Syposiu on Coputer Architecture, pp , May 199. [5] Mobile_DOC_G3_DS_Rev1..pdf [6] Microsoft Co., Pocket PC 22, [7] M. Wu, Willy Zwaenepoel, envy: A Non-Volatile, Main Meory Storage Syste, Proc. Sixth Int l Conf. On Architectural Support for Prograing Languages and Operating Sys. (ASPLOS VI), San Jose, CA, Oct. 1994, pp [8] B. Marsh, F. Douglis, and P. Krishnan, Flash eory file caching for obile coputers, Proc. 27 th Hawaii Conf. On Sys. Sciences, Wailea, HI, Jan. 1993, pp [9] F. Douglis et al., Storage Alternatives for Mobile Coputers, Proc. First USENIX Syp. On Operating Sys. Design and Ipleentation, Monterey, CA, pp 25-37, Nov [1] Li-Pin Chang, Tei-Wei Kuo, "An Adaptive Striping Architecture for Flash Meory Storage Systes of Ebedded Systes," The 8th IEEE Real-Tie and Ebedded Technology and Applications Syposiu (RTAS 22) Septeber, 22. San Jose, California. [11] J. R. Lorch and A. J. Sith, Software Strategies for Portable Coputer Energy Manageent, IEEE Personal Counications, June, [12] C.-G. Lee, K.-P. Lee, J. Hahn, Y.-M. Seo, S.L. Min, R. Ha, S. Hong, C.Y. Park, M. Lee, and C.S. Ki, Bounding Cache-related Preeption Delay for Real-tie Systes, IEEE Transaction on Software Engineering, vol 27, no 9, pp85-826, 21. [13] C. Young, E. Shekita, An Intelligent I-Cache Prefetch Mechanis, in Proceedings of the International Conferences on Coputer Design, pp , Oct [14] Josep Torrellas, Chun Xia, and Russell Daigle, Optiizing Instruction Cache Perforance for Operating Syste Intensive Workload, Proc. HPCA-1: 1st Intl. Syposiu on High-Perforance Coputer Architecture, p.36, January [15] Zhang Yi, Steve Haga and Rajeev Barua, Execution History Guided Instruction Prefetching, Proceedings of the Sixteenth ACM Int l Conference on Supercoputing (ICS), New York City, NY, June,