NEW STRATEGIES FOR HIGH PERFORMANCE VLSI PHYSICAL DESIGN HUA XIANG

Transcription

1 NEW STRATEGIES FOR HIGH PERFORMANCE VLSI PHYSICAL DESIGN BY HUA XIANG B.S., Peking University, 1997 M.S., Peking University, 2000 M.S., University of Texas at Austin, 2002 DISSERTATION Submitted in artial fulfillment of the requirements for the degree of Doctor of Philosohy in Comuter Science in the Graduate College of the University of Illinois at Urbana-Chamaign, 2004 Urbana, Illinois

2 c 2004 by Hua Xiang. All rights reserved

3 NEW STRATEGIES FOR HIGH PERFORMANCE VLSI PHYSICAL DESIGN Hua Xiang, Ph.D. Deartment of Comuter Science University of Illinois at Urbana-Chamaign, 2004 Martin D. F. Wong, PhD. Adviser Physical design lays an imortant role in connecting front-end design and back-end design in chi develoment. In this thesis, we solve several imortant roblems in hysical design of VLSI circuits. Chater 2 addresses a floorlan roblem that considers floorlanning and bus lanning simultaneously. We roose an efficient evaluation algorithm to transform a sequence air to a floorlan with buses inserted. Then simulated annealing is used to search for an otimal or near otimal solution. Chater 3 addresses a wire lanning roblem with the bounded over-the-block constraint. Two exact olynomial-time algorithms are resented, and both algorithms guarantee to find an otimal routing solution for a two-in net as long as one exists. Chaters 4 and 5 are based on a min-cost max-flow algorithm. In chater 4, we resent the first olynomial-time algorithm for simultaneous in assignment and routing for all two-in nets between one source block and all other blocks. In chater 5, we roose a olynomial-time algorithm for integrated in assignment and buffer insertion. Chaters 6 and 7 address ECO roblems. Chater 6 resents two algorithms to resolve overlas between ower rails and signal wires which are introduced by ower rail redesign. In chater 7, we roose an algorithm to eliminate caacitive crosstalk violations. iii

4 To Father and Mother iv

5 ACKNOWLEDGMENTS I would like to thank my adviser, Professor Martin D. F. Wong, for his constant guidance and invaluable suort throughout my graduate study. I am greatly benefited from his dee insight in technical roblems and valuable advice on my research. I am also grateful to the other members of my committee Professors Janak Patel, Lenny Pitt, and Jose Torrellas for their interest in my work. Also I would like to acknowledge my colleagues for their cooeration and many thoughtful technical discussions. I am grateful to all the wonderful friends I made during my graduate study. Their friendshi made my graduate study much more roductive and enjoyable. Finally, I would like to exress my secial thanks to my arents for their love, encouragement, and understanding throughout my graduate study. v

6 TABLE OF CONTENTS LIST OF FIGURES x LIST OF TABLES xv CHAPTER 1 INTRODUCTION CHAPTER 2 BUS-DRIVEN FLOORPLANNING Introduction Preliminary ProblemFormulation Bus OrderingviaSequencePair A necessary condition for one bus Bus ordering between twobuses Multile bus ordering EvaluationAlgorithm Feasible Bus Checking Orientation Bus Ordering Modified LCS Comutation BDFAlgorithm Perturbation (Move) Cost Function Soft BlockAdjustment ExerimentalResults Conclusion vi

7 CHAPTER 3 WIRE PLANNING WITH BOUNDED OVER-THE-BLOCK WIRE CONSTRAINTS Introduction ProblemFormulation WPAlgorithm WP-Path algorithm WP-Slit algorithm Comarison ExerimentalResults Conclusion CHAPTER 4 SIMULTANEOUS PIN ASSIGNMENT AND ROUTING Introduction Problem Definition TheAlgorithm Alications ECO Imrovementon anygivensolution Multile-in nets ExerimentalResults Conclusion CHAPTER 5 INTEGRATED PIN ASSIGNMENT AND BUFFER PLANNING Introduction PinAssignmentand Buffer PlanningforOneSourceBlock (PBO) TheAlgorithm PinAssignmentand Buffer Planning(PB) ImrovementwithNodeClustering ExerimentalResults vii

8 5.7 Conclusion CHAPTER 6 ECO ALGORITHMS FOR REMOVING OVERLAPS BETWEEN POWER RAILS AND SIGNAL WIRES Introduction PSO (Powerrail -Signal wireoverla)problem FP-Range (Fixed-Pin-decided Range) ConsistencyGrah PSO-H Algorithm PSO-G Algorithm ExerimentalResults Conclusion CHAPTER 7 AN ECO ALGORITHM FOR ELIMINATING CROSSTALK VIOLATIONS Introduction CrosstalkViolationElimination Preliminaries FP-Range Crosstalk model CVE Algorithm FCVE algorithm SCVE Otimization Nodeclustering Edge omitting ExerimentalResults Conclusion viii

9 CHAPTER 8 CONCLUSION Summary FutureResearch REFERENCES APPENDIX VITA ix

10 LIST OF FIGURES FIGURE PAGE 1.1 Thedesignflow ofa chi Two floorlans have the same chi size. (a) Two buses u (A, C) andv (B, E, H)areassigned. (b)neitherofthebuses can beassigned A feasible horizontal bus u =< H,t,{A, B, C} >. y max = y c +h c, y min = y b, and y max y min t A necessary condition for one bus. (a) The sequence air must be (... A... D... B... C...,... A... D... B... C...) to fit in a horizontal bus. (b) The sequence air must be (... B... C... A...,... A... C... B... ) to fit in a vertical bus Cases ofrelativeositionsoftwohorizontalbuses Two kinds of cycles in bus ordering constraint grahs. (a) Two buses are crossing. (b) The bus ordering constraint grah corresonding to (a). (c) Three buses are crossing. (d) The bus ordering constraint grah corresonding to (c) Indeendent set roblem and node-deleting roblem. (a) An instance of indeendent set roblem (ISP). (b) G d is a horizontal bus ordering constraint grah Node Deleting Algorithm. (a) An instance of bus ordering constraint grah G. (b) Nodes whose in-degree or out-degree is zero are removed from G. (c) Node c is deleted from G in order to break cycles. (d) The residual acyclic grah of G after deleting c and i x

11 2.8 Insert two horizontal buses to the floorlan reresented by (A DEBCF G, EDAFBCG). (a) One horizontal bus {A, B, C} is assigned. (b) In order to insert another bus {B,E,G}, blocksa and D have to move u and this makes the bus {A, B, C} changed,too (a) Two buses overla due to basic alignment adjustment. (b) Assignment of two buses without overla (Case A) Two buses share blocks A and B. Bus Overla may haen. (Case B) The blocks of two buses aear interlaced along x-axis. Bus Overla may haen. (Case C) Two buses have no overlas along x-axis. Bus Overla is imossible Soft block adjustment. (a) A BDF solution. Block E is on an LCS ath. (b) The new BDF solution after changing the shae of block E The result acking of ami49-2 after soft block adjustment. There are 49 blocks and 12 buses An otimal acking of grid7. There are 49 blocks and 14 buses The routing illustrated by thin lines is not valid; while the routing shown by widelinesisafeasiblesolution (a) A routing-block B i is divided into 3 3 subblocks, and the interconnect bound is 3. (b) A grah denotes all valid OB-wires within B i (a) The two nodes r j i and rk i are within the same routing-block B i. (b) Each node is slit into an in-node and an out-node The solid lines indicate a routing solution between blocks B 1 and B The corresonding ath grah G. The wide lines illustrate a shortest ath from u 1 1 to u (a) r 1 i, r2 i, r3 i,andr4 i are subblocks of a routing-block B i. (b) Each subblock is reresented by a node array The corresonding slit grah for Figure 3.4. The wide lines illustrate a shortest ath from v1 1[1] to v1 6 [1] xi

12 3.8 The comarison of WP-Path and WP-Slit on the relationshi between running timeand thenumberofnets (a) The two-ste aroach fails to route all nets. (b) The otimal solution of inassignmentandroutingby ouraroach (a) The net-by-net aroach fails to route all nets. (b) The otimal solution of inassignmentandroutingby ouraroach A routinggridgrah fortwolayers (a) A PAR roblem in detailed routing. (b) The corresonding network grah (a) A solution in a flow network. A flow f 1 goes from to q; and another flow f 2 goes from q to. (b)anothersolutionwithlesscost Node slitting for caacitated nodes. The caacity of the new edge is U(r) and its cost is (a) A flow f in the network in Figure 4.4 (b), f =3. (b) The corresonding solution of in assignment and routing for the 3 nets in the roblem of Figure 4.4 (a) (a) The initial in assignment and routing solution. (b) The solution obtained by alying PAR-by-Flow on Block A satisfying the new requirement Illustration of imrovement on a given solution. (a) Illustration of net connections among Block A, B, C and D. (b) Initial net-by-net solution based on the min-cost ath aroach. 5 nets (2 between B and C; 3 between C and D) are not routed. The total cost is 51. (c) The solution after alying PARby-Flow on Block A. Cost is reduced by 15. (d) The solution after alying PAR-by-Flow on Block B. Two more nets between B and C are routed. (e) The solution after alying PAR-by-Flow on Block C. All nets are routed (3 more nets) with less cost (from 51 to 50). (f) The solution after alying PAR-by-Flow on Block D. Nothingis changed xii

13 4.10 Illustration of imrovement for a in assignment and routing of two/multilein nets. (a) A one-layer in-assignment and routing solution. (b) When Block A is selected to be the source block, all nets connecting to A are removed to reroute. The routing e between B and C should not be changed. (c) The corresonding flow network grah. (d) A flow f ( f =4) in the network An imroved solution of in assignment and routing of two/multile-in nets Two-layer in assignment and routing for X18. (a) Net-by-net solution. (b) Thesolutionobtainedby alyingourmethodon(a) (a) Three nets use 3 buffers and the total wire length is 19. (b) An otimal solution with 1 buffer and wire length (a) A PBO roblem with 3 macro blocks and 3 buffer blocks. (b) The corresonding flow network grah Node slitting for caacitated nodes. The new edge has caacity U(v) and cost C(v) (a) A flow f in the network in Figure 5.2 (b), f =3. (b) The corresonding solution of in assignment and buffer lanning to the PBO roblem of Figure 5.2 (a) (a) A PB roblem with 3 macro blocks and 3 buffer blocks. (b) The corresonding flow network when b 1 isthesourceblock The corresonding flow network when b 2 is thesourceblock The corresonding flow network of the PB roblem in Figure 5.5(b) using the node clustering method (a) A flow f, f =3flows through a suernode. (b) The corresonding network and a flow solution. (c) Deriving connections for original in nodes (a) Some horizontal signal wire segments on M 5 overla with P 1 and P 2.(b) A feasiblepso solution. (c) A solutionwithviolations Wire searation requirement illustration xiii

14 6.3 (a) A PSO roblem. (b) Overlas: vertical segments a and b on M 4 ;and horizontal segments c and d on M FP-Range illustration. The tiny squares are fixed ins Threecases ofvertical overlas Illustration of the FP-Range calculation when the width is taken into consideration A routingsolutionofsignalwireson theto layer (a) Full connections of adjacent segments. (b) Consistency grah Illustration of Onodes/Rnodes (a) A routing solution with crosstalk violations. (b) A routing solution with overlaviolations Segments A and C have caacitive crosstalk; while the crosstalk between segments B and C iszero (a) B, C, andd are three children of A. The osition of A is fixed. (b) B is first selected and ut to its highest available osition. (c) A solution according to ouraroach (a) A CVEP roblem. There are 4 signal wire segments A 1, A 2, A 3,andA 4, and 1 ower rail P. (b)theconsistencygrah isaath (a) A CVEP roblem. (b) FSP grah G of the CVEP roblem. (c) SP grah Ḡ ofthecveproblem. (d)a feasiblesolutiontothecveproblem (a) A i is a wire segment and it has 12 available ositions. (b) Every three nodes are clusteredas a suernode (a) FSP grah of a CVEP roblem. is a feasible osition of A i 1. (b) SP grah ofthecvep roblem (Case 1) u is the closest feasible osition to y i. Only one edge is needed. (Case 2) y i is the only feasible osition in (B u, 2y i u). Two edges are added. (Case 3) There are two feasible ositions in (2y i u, B l ). Three edges are added xiv

15 LIST OF TABLES TABLE PAGE 2.1 Test set Test sets2 and Algorithmcomarison Test resultsofwp-path andwp-slit algorithms Average results of 10 times for detailed routing test files. All nets are routed after refinement byreimprove-by-par Average results of 10 times for global routing test files. All nets are routed after refinement by ReIMProve-by-PAR Average results of PB-Flow for 5 times. All nets are found using PB-Flow algorithm Average results of PSO-H and PSO-G for 5 times Test files ofcve roblem Test resultsofcve roblem OtimizationfortestfileN xv

16 CHAPTER 1 INTRODUCTION As the very large scale integration (VLSI) technology marches toward ultradee submicron, designs are becoming increasingly comlex with millions of layout objects on a monolithic chi. As a result, the chi design cycle time becomes longer. However, due to the raid develoment of current technology and tight marketing schedule, the chi design time has to be short enough to satisfy time-to-market considerations. Therefore, sohisticated comuter-aided design (CAD) tools and methodologies are badly needed, and they are widely used to facilitate chi develoment. In general, the to-down design flow of a device can be abstracted as the following stes as illustrated in Figure 1.1 [1]. A design starts from secifications that describe the behavior of the target chi. Next, architectural design defines larger circuit modules such as arithmetic units, memory units, etc. Then the defined architecture is maed to the logic structure in the logic design stage. Finally, hysical design transforms the logic structure from the revious stage to geometric shaes that are used in the fabrication of the chi. Therefore, hysical design lays an imortant role such that it connects front-end and back-end design. Moreover, the quality of hysical design tools directly determines the erformance and cost of the final roduct. 1

17 Secificaion Architectural Design Logical Design Physical Design Fabrication Chi Figure 1.1 The design flow of a chi. In this thesis, we study several imortant roblems in hysical design. In Chater 2, we roose bus-driven floorlanning. In Chater 3, we study the roblem of wire lanning with bounded over-the-block wires. In Chater 4, we address the simultaneous in-assignment and routing roblem. In Chater 5, we resent an integrated aroach for in-assignment and buffer insertion. In Chaters 6 and 7, we roose algorithms to solve some ECO (engineering change order) roblems. The results resented in these chaters can be briefly summarized as follows. In Chater 2, we roose an integrated aroach for floorlanning and bus lanning, i.e., bus-driven floorlanning (BDF). We are given a set of circuit blocks and bus secifications (i.e., the net list of blocks for the buses). A feasible BDF solution is a lacement of all circuit blocks such that each bus can be realized as a rectangular stri (horizontal or vertical) going through all the blocks connected by the bus. The objective is to determine a feasible BDF solution that minimizes the floorlan area and the total bus area. Our a- 2

18 roach is based uon the sequence-air floorlan reresentation. After a careful analysis of the relationshi between bus ordering and block ordering in the floorlan reresented by a sequence air, we derive feasibility conditions on sequence airs that give feasible BDF solutions. We tested on three sets of test files and obtained excellent results. In Chater 3, we address the roblem of wire lanning (WP) with bounded over-theblock wires. The constraints on over-the-block wires hel the longest over-the-block wires within a block to satisfy signal integrity without buffer inserted. We resent two exact olynomial-time algorithms to solve the WP roblem. Both algorithms guarantee to find an otimal routing solution for a two-in net as long as one exists. One requires less memory, while the other may take less running time when rocessing a large number of nets. According to different alication requirements, users can choose an aroriate algorithm. In Chater 4, we resent an algorithm for simultaneous in-assignment and routing. In revious works, the algorithms for these roblems can be classified into two categories: (1) a two-ste aroach where in assignment is followed by routing, and (2) a net-by-net aroach where in assignment and routing for a single net are erformed simultaneously. But none of the existing algorithms is exact in the sense that they may fail to route all nets even though a feasible solution exists. This remains to be true even if only twoin nets with fixed ins between two blocks are concerned. In this chater, we consider the roblem of two-in net connections from one macro block to all other blocks, and we resent the first olynomial-time exact algorithm for simultaneous in assignment and 3

19 routing for all two-in nets between one block (source block) and all other blocks. In addition to finding a feasible solution whenever one exists, it guarantees to find a inassignment/routing solution with minimum cost α W + β V,whereW is the total wire length and V is the total number of vias. Our algorithm has various alications: (1) It is suitable in ECO situations where an existing solution is modified incrementally. (2) Given any in assignment and routing solution obtained by any existing method, our algorithm can be used to increase the number of routed nets and reduce the routing cost. Furthermore, it rovides an efficient algorithm for the in assignment and routing roblem of all blocks. The method is alicable to both global and detailed routing with arbitrary routing obstacles on multile layers. In Chater 5, we resent a olynomial-time exact algorithm for integrated in assignment and buffer lanning for all two-in nets from one macro block (source block) to all other blocks. Moreover, we can guarantee to minimize the total cost α W + β R for any ositive α and β where W is the total wire length and R is the number of buffers. By alying this algorithm iteratively ( i.e., each time ick one block as the source block), it rovides a olynomial-time algorithm for in assignment and buffer lanning for nets among multile macro blocks. Exerimental results demonstrate that this aroach is efficient and effective. In Chater 6, we address the PSO (ower rail - signal wire overla) roblem which removes overlas between ower rails and signal wires on the to layer of a multile layer routing region under certain constraints. PSO roblems are frequently caused by changes 4

20 from ower delivery system or ackage design. Efficient and graceful solutions to PSO are needed due to design constraints and tight schedules during the late ECO stages. In this chater, we first roose two algorithms to remove the overlas between ower rails and signal wires. Both algorithms guarantee to find a feasible solution as long as one exists. One is faster, while the other makes effort to minimize the total deviation as well as the maximum deviation. For a set of industrial test circuits, we were able to remove all overlas between ower rails and signal wires with minimal wire deviation. In Chater 7, we address the CVE (crosstalk violation elimination) roblem. Due to the changes in a multile layer routing design, the total caacitive crosstalk on some signal wire segments may be larger than their allowable bounds after ost-layout timing/noise analysis. The target is to find a new routing solution without crosstalk violations under certain constraints which hel to kee the new design close to the original one. We roose a two-stage algorithm to solve the CVE roblem, and resent otimization strategies to seed u the execution. One ossible alication of CVE algorithm is that it can be used to eliminate crosstalk violations in the outut of PSO roblem in Chater 6. Finally, in Chater 8, we summarize our research and roose some directions for future research work. 5

21 CHAPTER 2 BUS-DRIVEN FLOORPLANNING 2.1 Introduction As the dee submicron technology advances, chis become more congested even though more metal layers are used for routing. Usually a chi includes several buses. As design increases in comlexity, bus routing becomes a heavy task, esecially for networking chis or data rocessors. Since buses have different widths and go through several module blocks, the ositions of macro blocks greatly affect bus lanning. To ease bus routing and avoid unnecessary iterations in hysical design, we need to consider bus lanning in early floorlanning stage. In this chater, we address the roblem of bus-driven floorlanning (BDF). We use to two layers for bus lanning, and buses go either horizontally or vertically on one layer in floorlanning stage. The simle bus structure is good and efficient at lanning stage, and would facilitate bus routing in later stages. Furthermore, more comlicated bus structure can always be decomosed into several horizontal/vertical bus segments. Informally, the roblem can be described as follows. Given a set of rectangular macro blocks and the bus secifications (i.e., the net list of blocks for the buses), find a lacement 6

22 u A B D v E G H A G D u E B C C F I H F I (a) (b) Figure 2.1 Two floorlans have the same chi size. (a) Two buses u (A, C) andv (B, E, H) are assigned. (b) Neither of the buses can be assigned. of all circuit blocks such that each bus can be realized as a rectangular stri (horizontal or vertical) going through all the blocks connected by the bus. At the same time, the chi area as well as the total bus area is minimized. Figure 2.1 gives an examle. Figure 2.1(a) and (b) are two floorlans with the same chi size. Two buses u (A, C) and v (B, E, H) are laced in the floorlan of Figure 2.1(a). However, neither of the buses can be assigned based on the floorlan in Figure 2.1(b) since blocks B, E and H are not aligned, and the vertical overla between blocks A and C is less than the width of bus u. In revious works, researchers have discussed some articular kinds of floorlan constraints related to alignment. However, these kinds of alignment constraints are not suitable for bus-driven floorlanning. Young et al. [2] handle a kind of alignment in which modules involved in an alignment are required to be aligned by left (right/bottom/uer) side. But this is not necessary in BDF roblems. For examle, the bottom sides of blocks B, E and H are not aligned, but bus v still fits in the floorlan in Figure 2.1(a). Tang and 7

23 Wong [3] roosed another alignment constraint in which several blocks are aligned in a row, abutting with each other. But blocks involved in one bus do not need to be laced adjacent to each other. In Figure 2.1(a), A and C are not adjacent while bus u is assigned. Liu et al. [4] discussed redefined coordinate alignment constraint in which some blocks are to be laced along a redefined coordinate within a small region. In BDF, there are no constraints on coordinates. Rafiq et al. [5, 6] roosed bus-based integrated floorlanning. However, the bus defined in their works is comosed of bundles of wires connecting only two blocks. Also bus assignment is accomlished by global routing. Most floorlan algorithms use simulated annealing to search for an otimal solution. The imlementation of the simulated annealing scheme deends on a floorlan reresentation where a neighbor solution is generated and examined by erturbing the reresentation (called move ). In this chater, we use the sequence air reresentation and analyze the relationshi between bus ordering and sequence air reresentation. Then a fast evaluation algorithm is roosed to transform a sequence air reresentation to a floorlan with buses inserted. The algorithm first derives a bus ordering based on some necessary conditions. Then a modified longest common subsequence algorithm is alied to decide block ositions as well as bus assignments. Moreover, we also develo an efficient algorithm to handle soft modules to further imrove solution quality. Exerimental results on three sets of test files (MCNC benchmarks, industry test files,and bus grid test files) demonstrate the effectiveness and efficiency of our aroach. The rest of the chater is organized as follows. Section 2.2 rovides background infor- 8

24 mation on the sequence air reresentation. The formal definition of the BDF roblem is given in Section 2.3. In Section 2.4, we analyze the relationshi between bus ordering and sequence air reresentation. Then a fast evaluation algorithm is roosed to transform a sequence air to a BDF solution in Section 2.5. In Section 2.6, a simulated annealing BDF algorithm is resented. Finally, we address how to handle soft blocks to imrove solution quality in Section 2.7. Exerimental results are given in Section 2.8, and Section 2.9 concludes the aer. 2.2 Preliminary A sequence air is a air of sequences of n elements reresenting a list of n blocks. In general, a sequence air imoses the relationshi between any two blocks a and b as follows: (i) If a is ahead of b in both sequences, a is to the left of b in the floorlan. (ii) If a is ahead of b in the first sequence while behind b in the second sequence, a is above b in the floorlan. The original aer which roosed sequence air [7] resented an algorithm to transform a sequence air to a floorlan in Θ(n 2 ) time. Recently, Tang et al. sed u the evaluation algorithm to O(n log n) in [9], and later further to O(n log log n) in [8]. The coordinates of blocks and the width and height of a floorlan can be obtained by comuting longest common subsequence (LCS) in terms of the two sequences [9, 8]. Given a sequence air (X, Y ), the width of a floorlan equals the length of the longest 9

25 common subsequence of X and Y where weights are blocks widths. Furthermore, given a block b,let(x, Y )=(X 1 bx 2,Y 1 by 2 )andlcs(x, Y ) be the length of the longest common subsequence of (X, Y ). Then the x-coordinate of block b equals to LCS(X 1,Y 1 ) with blocks widths as weights. Similarly, the height of a floorlan is determined by dealing with the longest common subsequence of (X, Y R )wherey R is the reverse of Y and weights are blocks heights. Furthermore, all the comutations of blocks x/y coordinates can be integrated into a single longest common subsequence comutation for a sequence air. 2.3 Problem Formulation Suose the routing region has multile layers and buses can be assigned on the to two layers. So the orientation of buses is either horizontal or vertical. The roblem of busdriven floorlanning (BDF) can be defined as follows. Problem 2.1 Bus-Driven Floorlanning (BDF) Given n rectangular macro blocks B = {b i i =1,..., n} and m buses U = {u i i =1,..., m}, each bus u i has a width t i and goes through a set of blocks B i where B i B and B i = k i. Decide the ositions of macro blocks and buses such that there is no overla between any two blocks or between any two horizontal (vertical) buses, and bus u i goes through all of its k i blocks. At the same time, the chi area as well as the total bus area is minimized. In BDF roblems, buses should go through all of their related blocks. So the ositions of blocks greatly affect bus assignments. For convenience, let <g,t,{b 1,..., b k } > reresent 10

26 y y b +h b y a +h a y c +h c y b y a y c A B u C y max y min >t x Figure 2.2 A feasible horizontal bus u =< H,t,{A, B, C} >. y max = y c +h c, y min = y b, and y max y min t. abusu where g {H, V } is the orientation, t is the bus width, and b i (i =1,..., k) are the blocks the bus goes through. For short, a bus is just reresented as {b 1,..., b k }.Alsolet (x i,y i ) be the lower-left corner of block b i. And the width and height of block b i are w i and h i resectively. In the following, we give the necessary conditions of a feasible horizontal and vertical bus resectively. Lemma 2.1 Feasible Horizontal Bus (H-Bus) If a horizontal bus u =< H,t,{b 1,..., b k } > is feasible, then y max y min t where y max =min{y i + h i i =1, 2,..., k} and y min = max{y i i =1, 2,..., k}. Lemma 2.2 Feasible Vertical Bus (V-Bus) If a vertical bus u =< V,t,{b 1,..., b k } > is feasible, then x max x min t where x max =min{x i + w i i =1, 2,..., k} and x min = max{x i i =1, 2,..., k}. Figure 2.2 illustrates an H-bus u =< H,t,{A, B, C} >. In order to fit in bus u, the vertical overla of the three blocks has to be larger than the bus width t. 11

27 2.4 Bus Ordering via Sequence Pair A sequence air always entails a acking if no constraints are given. However, when constraints are introduced, there may not exist a corresonding acking for some sequence airs. In this section, we discuss the relationshi between bus ordering and sequence air reresentation. First, a necessary condition is derived when only one bus is considered. Then we discuss the relative ositions of any two horizontal (vertical) buses imosed by a sequence air. Based on the analysis of the ordering of two buses, we set u a bus ordering constraint grah and roose an algorithm to remove infeasible buses A necessary condition for one bus Since blocks cannot overla in a BDF solution, blocks have at most one-dimension overla; i.e., if the rojections on x-axis of two blocks have overla, their rojections on y-axis cannot overla. On the other hand, if the rojections on y-axis of two blocks have overla, their rojections on x-axis cannot overla. However, in order to fit in a bus {b 1,..., b k },the rojections on x-axis (y-axis) of b i and b j (i, j =1,..., k; i j) must have overla. In other words, the osition relationshi of any two related blocks has to be left-right (below-above). Thus we have the following necessary condition. Theorem 2.1 (Block Ordering) Given a sequence air (X, Y ) and a bus u = {b 1,..., b k }, if u is feasible, then the ordering of the k blocks should be either the same or reverse in the 12

28 y y A D B C x A B C x (a) (b) Figure 2.3 A necessary condition for one bus. (a) The sequence air must be (... A... D... B... C...,... A... D... B... C...) to fit in a horizontal bus. (b) The sequence air must be (... B... C... A...,... A... C... B... ) to fit in a vertical bus. two sequences X and Y. Furthermore, if the k blocks aear in the same order in both X and Y, the orientation of the bus is horizontal; otherwise the bus is vertical. For convenience, this necessary condition is also called block ordering. Figure 2.3 gives two examles. The sequence air for Figure 2.3(a) is (... A... D... B... C...,... A... D... B... C...), and a horizontal bus {A, B, C, D} can be assigned. Figure 2.3(b) shows another examle. The sequence air is (... B... C... A...,... A... C... B... ) and the bus is a vertical one {A, B, C}. Note that Theorem 2.1 deals with only one bus. When multile buses are considered, it is likely that some buses cannot be assigned for the floorlan although each bus satisfies the necessary condition Bus ordering between two buses The relative ositions of blocks is determined by a sequence air. Since buses go through blocks, the ordering of buses is also influenced by the sequence air. Given a sequence air (X, Y ) and two horizontal buses u = {a 1,a 2,..., a k } and v = 13

29 {b 1,b 2,..., b l }, denote the block set S u = {a 1,a 2,..., a k }, S v = {b 1,b 2,..., b l },ands = S u S v. Suose S = L (L k + l since the two buses may go through the same blocks) and (X, Y ) satisfies block ordering for the two buses. Also we assume these L blocks aear in the sequence air as (... c 1... c c L...,... d 1... d d L...) where c i S and d i S (i =1,..., L), and the subsequence air (X,Y )=(c 1 c 2... c L,d 1 d 2... d L ). For convenience, let [c i ]=i(i =1,..., L) which denotes the osition of c i in X,and q[d i ]=ireresents the osition of d i in Y. From this subsequence air (X,Y ),wecan derive the relative ositions of the two buses. Case 1. If a S u, [a] q[a], and a S u, [a] >q[a], then bus u is below bus v. Suose [a i ] >q[a i ],then(x, Y ) must be (... b j... a i...,... a i... b j...). b j is above a i.sinceugoes through a i while v goes through b j,busu is below v. Figure 2.4 (Case 1) shows an examle. The subsequence air is ( DAEBFC, ADBECF). [A] =2and q[a] =1; [B] =4and q[b] =3; [C] =6and q[c] =5. So bus u = {A, B, C} is below bus v = {D, E, F}. Case 2. If a S u, [a] q[a], and a S u, [a] <q[a], then bus u is above bus v. Figure 2.4 (Case 2) shows an examle. Block B is shared by both buses. Bus u = {A, B, C} is above bus v = {D, B, E}. Case 3. If a S u, [a] >q[a], and a S u, [a ] <q[a ], then the two buses u and 14

30 v cannot be assigned at the same time. Suose [a i ] >q[a i ] and [a j ] <q[a j ],then(x, Y ) must be (... b I... a i... a j... b J...,... a i... b I... b J... a j...). Blockb I is above a i while b J is below a j. The ositions of blocks are illustrated in Figure 2.4 (Case 3). In the examle, the two buses are u = {A, B} and v = {C, D}. Then the subsequence air is (X,Y ) is (A CDB, CABD). For block A, [A] =1and q[a] =2while [B] =4and q[b] =3. In this case, the two buses cannot be assigned at the same time. Case 4. If a S u, [a] =q[a], then the two buses have no firm ordering. Either bus can be above the other. Figure 2.4 (Case 4) illustrates an examle. In this examle, bus u = {A, B, C} can be below bus v = {D, E}. On the other hand, u is also ossible above v. Therefore, the two buses have no bus ordering constraints. For any two vertical buses, we can get the similar results from (X, Y R ) Multile bus ordering In a BDF solution, it is imossible that the ordering of several buses forms a cycle. For examle, bus u is above bus v, busv is above bus w, andbusw is above bus u. Thiskind of relationshi cannot exist in a feasible solution. In the above section, we have discussed bus ordering imosed by the given sequence air. To exress the relative ositions among buses, we construct bus ordering constraint 15

31 y D v E F A B C u x SubSequence Pair (D A E B F C, A D B E C F) q D A E B F C A D B E C F Case 1 y A D u B v C E x SubSequence Pair (A D B C E, D A B E C) q A D B C E D A B E C Case 2 y y A C v Case 3 D u A C D B B q C A B D x SubSequence Pair (A C D B, C A B D) A D v E C A D B E C uv B Case 4 x SubSequence Pair (A D B E C, A D B E C) q A D B E C Figure 2.4 Cases of relative ositions of two horizontal buses. 16

32 grahs for horizontal buses and vertical buses, resectively. The construction rules for a horizontal bus ordering constraint grah are listed as follows. The grah for vertical buses can be derived similarly. Each bus is reresented by a node. If one bus u is above another bus v (Case 1 or 2), add one edge (u, v). If one block related to bus u is above a block related to bus v, while another block related to u is below a block related to v (Case 3), add two edges (u, v) and (v, u). If two buses have no bus ordering constraint (Case 4), no edge is added. The horizontal bus ordering constraint grah serves in two ways: (i) Given a BDF solution, the block acking must corresond to a sequence air. Then the horizontal bus relationshi imosed by the sequence air can be reresented by an acyclic constraint grah. (ii) If a constraint grah contains a cycle, then at least one bus cannot be assigned. According to the construction rules, there are two kinds of cycles. (a) A cycle includes only two nodes. Then the relative osition of the two corresonding buses must comly with Case 3, and at least one bus cannot be assigned. Figure 2.5(a) shows an examle. Two buses u = {A, B} and v = {C, D} are crossing, and the subgrah is given in Figure 2.5(b). 17

33 y A C D v u u v B x (a) (b) y A 1 v B 2 u w C 2 u v B 1 C 1 A 2 x w (c) (d) Figure 2.5 Two kinds of cycles in bus ordering constraint grahs. (a) Two buses are crossing. (b) The bus ordering constraint grah corresonding to (a). (c) Three buses are crossing. (d) The bus ordering constraint grah corresonding to (c). (b) A cycle includes at least three nodes. Figure 2.5 (c) illustrates an examle. There are three buses u = {A 1,A 2 }, v = {B 1,B 2 } and w = {C 1,C 2 }. The sequence air is (... A 1... B 1... B 2... C 1... C 2... A 2...,... B 1... A 1... C 1... B 2... A 2... C 2...). From this sequence air, we can conclude that bus u should be above v, v should be above w, andw should be above u. However,thisis imossible in a BDF solution. Therefore, at least one bus has to be discarded. If a bus-ordering constraint grah contains cycles, there must be some buses that cannot be assigned. Since our target is to assign as many buses as ossible, the roblem becomes how to remove minimum number of buses so that the grah is acyclic. However this rob- 18

34 lem is an NP-Comlete roblem. For convenience, if some nodes are removed from the grah G =(V,E), then edges connecting to/from these nodes are also removed, and the result grah is called a residual grah. Also all nodes are indexed, and node u<vmeans that the index of u is less than that of v. Problem 2.2 Node-Deleting Problem (NDP) Given a sequence air and a set of buses, a horizontal (vertical) bus-ordering constraint grah can be constructed. Remove nodes from the constraint grah so that the residual grah is acyclic. At the same time, the number of deleted nodes is minimized. Theorem 2.2 Node-Deleting Problem (NDP) is NP-Comlete. Proof NDP is the otimization roblem of removing minimum number of nodes from a constraint grah so that the residual grah is acyclic. As a decision roblem, we ask simly whether there exists a node set of size k such that the residual grah is acyclic by removing these nodes from a constraint grah. To show that NDP NP, for a given constraint grah Ḡ =( V,Ē), weusetheset V V as a certificate of Ḡ. Checking whether the residual grah of removing V from Ḡ is acyclic or not can be accomlished in olynomial time. Next we rove that NDP is NP-hard by roving that indeendent set roblem (ISP), which is NP-comlete, is olynomial-time reducible to NDP; i.e., ISP NDP. 19

35 u e 1 e 2 v w v z u e 1 e 2 w z (a) (b) Figure 2.6 Indeendent set roblem and node-deleting roblem. (a) An instance of indeendent set roblem (ISP). (b) G d is a horizontal bus ordering constraint grah. Let G =(V,E) be an instance of ISP. Suose V = N and E = M. We form a directed grah G d =(V,E d ) where E d = {(i, j) (i, j) E} {(j, i) (i, j) E}; i.e., each edge in G is reresented by a air of edges with different directions in G d. Obviously, the construction of G d from G takes O(M) running time. Figure 2.6 shows an examle. Figure 2.6(a) is an instance of indeendent set roblem G. Figure 2.6(b) is G d. Note that G is an undirected grah. Given a node subset V, we can get a residual grah Ḡd of G d by removing nodes in {V V }. We show that V is an indeendent set of G if and only if the residual grah Ḡd is acyclic. If V is an indeendent set of G, then there are no edges in Ḡd. Obviously, Ḡd is acyclic. On the other hand, for any residual grah Ḡd of G d, if it contains no cycles, then there are no edges in Ḡd since edges always aear in airs. Therefore, the nodes in Ḡd also form an indeendent set of G. Finally we show that G d is a bus ordering constraint grah. For any edge e i =(u, v) E (u <v), let block sequence x i =(a u i bv i cv i du i ), and block sequence y i =(b v i au i du i c v i ),whereau i, bv i, cv i and du i are macro blocks. Suose there are 20

36 L indeendent nodes w i (i =1,..., L) ing which are not incident on any edge. Let block sequence x M+i =(a w M+i dw M+i ) and block sequence y M+i =(a w M+i dw M+i ) where aw M+i and d w M+i are blocks. We form a sequence air (X, Y ) = (x 1...x M x M+1...x M+L, y 1...y M y M+1...y M+L ). Blocks in X and Y form the macro block set B. So totally there are 4M +2L blocks. Since there are N nodes in G, the number of buses is also N. For each bus, the blocks that goes through are {z i z i B,i =1,..., (M + L),z = a, b, c, d}. Since the ordering of blocks of each bus is always the same in both sequences, all buses are horizontal buses. For each air of buses u and v ( u<v), we get the subsequence air (X,Y )= (x 1 x 2...x M,y 1 y 2...y M ),wherex i is a subsequence of x i,andy i is a subsequence of y i. Blocks aearing in X or Y are related to either bus u or v. Furthermore, (x i,y i)(i = 1...M) can be only one of the two cases. (i) (x i,y i)=(x i,y i ) (ii) x i = y i If J, (x J,y J )=(x J,y J ),thenj is unique since there is only one edge between two nodes u and v in G. At the same time, the subsequence air (X,Y ) involves bus crossing (Case 3 ) for bus u and v. Therefore, the bus constraint grah contains two edges (u, v) and (v, u). On the other hand, if i {1,..., (M +L)}, x i = y i, the two buses have no bus ordering constraint, and there is no edge between the two nodes u and v in the constraint grah. Also if x i = y i (x i /y i can be emty), then there is no edge between u and v in G either. Thus 21

37 a b e b d c g f i h c g f i h (a) b a (b) b e g f i h d g f h (c) (d) Figure 2.7 Node Deleting Algorithm. (a) An instance of bus ordering constraint grah G. (b) Nodes whose in-degree or out-degree is zero are removed from G. (c) Node c is deleted from G in order to break cycles. (d) The residual acyclic grah of G after deleting c and i. we can conclude that G d is the horizontal bus ordering constraint grah for the constructed sequence air. Since NDP is NP-Comlete, we derive a heuristic method to remove nodes from a grah so that the residual grah is acyclic. The method is based on the following lemma. Lemma 2.3 Given a directed grah, if the in-degree and out-degree for each node are both nonzero, then a cycle must exist in the grah. For any given directed grah G =(Ṽ,Ẽ), if the in-degree and out-degree of each node are nonzero, a cycle can be found in the following way. Randomly select a node ṽ 1 as the first node of a ath. Then let the second node ṽ 2 be a node incident on an out-going edge 22

38 of ṽ 1. Since the out-degree of ṽ 1 is nonzero, an out-going edge always exists. Reeat this rocess until a node aears twice along the ath. Since Ṽ is finite, the loo must finish within Ṽ +1stes. And if a node aears twice on a ath, it means a cycle is formed. An algorithm is used to remove nodes to break cycles in a bus-ordering constraint grah. Algorithm 1 Node Deleting (V, E) 1: for i =1to V do 2: Calculate in-degree and out-degree of nodes in V 3: Find min in-degree min in and min out-degree min out 4: if (min in =0)or(min out =0)then 5: Remove the corresonding node v from V 6: Remove edges connecting to/from v from E 7: else 8: Find the node v with max degree 9: Insert v into Remove Set 10: Remove v from V and related edges from E 11: end if 12: end for 13: return Remove Set For each iteration, the size of V is reduced by one. If we can find a node whose indegree or out-degree is 0, then this node is treated as a good node. Otherwise, we select the node v with max degree (in-degree + out-degree) and insert it to the Remove Set, i.e., v should be discarded in order to break cycles. This algorithm guarantees that if the grah is acyclic, Remove Set is emty. The running time is O( V 2 ). Figure 2.7 illustrates an examle. Figure 2.7(a) shows an instance of bus ordering constraint grah G, which includes nine buses. We first remove nodes whose in-degree 23

39 or out-degree is zero. Buses a, d, ande are removed from G as Figure 2.7(b). In Figure 2.7(b), the in-degree and out-degree of all nodes are nonzero; therefore, a cycle must exist. Since c has the maximum degree, c is deleted, making b and g free. The result is illustrated as Figure 2.7(c). Finally i is deleted to break the cycle between i and h. Therefore, there are two nodes c and i in Remove Set. Figure 2.7(d) shows the residual acyclic grah after deleting c and i. Furthermore, based on Figure 2.7(d), it is easy to find a bus ordering consistent with the below-above relationshi imosed by the sequence air. For instance, the bus ordering (from bottom to to) could be g, d, f, h, a, b, e. 2.5 Evaluation Algorithm The evaluation algorithm Algorithm 2 transforms a sequence air reresentation to a BDF solution. However, for some sequence airs, it is imossible to fit in all of the buses. For examle, if a sequence air violates block ordering for a bus, then some buses cannot be assigned. Therefore, the target of the evaluation algorithm is to find a floorlan that assigns as many buses as ossible. The algorithm is summarized as follows. Suose there are n blocks and m buses. Algorithm 2 Evaluation BDF (Seq, Bus) 1: Feasible Bus Checking Orientation 2: Bus Ordering 3: Modified LCS Comutation In the following, we exlain the above three rocedures one by one. 24

40 2.5.1 Feasible Bus Checking Orientation According to Theorem 2.1, if the blocks of a bus violate block ordering in the given sequence air, the bus cannot be assigned. Therefore, the first ste is to identify these buses and remove them from the bus set. For each bus, one scan of the sequence air is enough to make the judgment. At the same time, if blocks related to a bus aear in the same order in both sequences, the bus is a horizontal bus, otherwise, the bus is a vertical one. This ste takes O(mn) time Bus Ordering Due to the bus ordering imosed by the given sequence air, some buses cannot be assigned at the same time as discussed in Section 2.4. We aly the Node Deleting algorithm to further remove some buses. Meanwhile, since the constraint grah is acyclic, we sort the horizontal buses from bottom to to (from left to right for vertical buses) according to the below-above (left-right) relationshi. This bus order will be used in the next ste. This ste takes O(m 2 n) time Modified LCS Comutation The algorithm is based on the engine of comuting longest common subsequence (LCS) resented in [8]. LCS comutation calculates x coordinates and y coordinates searately. And it always acks blocks from bottom to to (from left to right). In this section, we only discuss the calculation of y coordinates of blocks with the assignment of horizontal buses. 25