Interconnect Delay Minimization through Interlayer Via Placement in 3-D ICs

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1 Interonnet Delay Minimization through Interlayer Via Plaement in -D ICs Vasilis F. Pavlidis, Eby G. Friedman Department of Eletrial and Computer Engineering University of Rohester Rohester, New York 467, UA [pavlidis, ee.rohester.edu ABTRACT The dependene of the propagation delay of the interlayer -D interonnets on the vertial through via loation and length is investigated. For a variable vertial through via loation, with fixed vertial length, the optimum vertial through via loation that minimizes the propagation delay of an interonnet line onneting two iruits on different planes is determined. The optimum vertial through via loation and length or, equivalently, the number of physial planes traversed by the vertial through via, are determined for varying the plaement of the onneted iruits. Design expressions for the optimal via loations and lengths have been developed to support plaement and routing algorithms for -D ICs. Categories and ubjet Desriptors B.7. [Design Aids] General Terms: Performane, Design. Keywords: -D ICs, Elmore delay, RC Interonnets. for interonnet-entri iruits that offers signifiant redutions in interonnetion length. This advantage is ahieved by using the third dimension, as shown in Figure. In Figure, multiple physial planes are staked to reate a -D system. A variety of bonding tehniques to aomplish this task have been desribed in the literature [-]. Most of these tehniques invoe bonding fores with elevated temperatures and the bonding materials inlude adhesive polymers or euteti metal pads [4]. Eah physial plane of the stak is similar to a onventional -D iruit, in that a plane inludes a devie layer and multiple metal layers are used to onnet individual iruits on the same physial plane (the intralayer interonnets). Eah of the bonded planes an utilize ompletely different proesses or design disiplines. For instane, non-silion analog, digital, and RF iruits suh as GaAs and ige an be staked within a single -D multilayer system. uh tehnology diversity extends the apabilities of -D systems over a onventional CMO platform, greatly failitating the ystems-on-chip design onept. Communiation among iruits on different physial planes (the interlayer interonnets) is implemented by vertial through vias, whih are alled vias here for brevity.. INTRODUCTION Tehnology saling has enabled an inrease in integration density and a onsiderable derease in the intrinsi gate delay, through smaller and faster devies. Higher integration densities require both a greater number of interonnets and longer interonnets. Therefore, as the devie delay is redued, the performane of the integrated iruits is now dominated by the interonnet delay. In addition, other interonnet related issues, suh as power onsumption and signal integrity, have beome more pronouned with tehnology saling. To manage these issues, a variety of tehniques have been developed, suh as tapered buffers, repeater insertion, wire sizing, and shielding, to name a few. Nonetheless, these tehniques inrease silion area and power onsumption. As a result, innovative design proesses are sought to satisfy the ever inreasing demand for greater performane. Three-dimensional integration is an effetive design paradigm This researh was supported in part by the emiondutor Researh Corporation under Contrat No. 00-TJ-068 and 004-TJ-07, the National iene Foundation under Contrat No. CCR , the Fullbright Program under Grant No , a grant from the New York tate Offie of iene, Tehnology & Aademi Researh to the Center for Advaned Tehnology in Eletroni Imaging ystems, and by grants from Xerox Corporation, IBM Corporation, Intel Corporation, uent Tehnologies Corporation, and Eastman Kodak Company. Permission to make digital or hard opies of all or part of this work for personal or lassroom use is granted without fee provided that opies are not made or distributed for profit or ommerial advantage and that opies bear this notie and the full itation on the first page. To opy otherwise, or republish, to post on servers or to redistribute to lists, requires prior speifi permission and/or a fee. GVI 05, April 7 9, 005, Chiago, Illinois, UA. Copyright ACM /05/ $5.00. Interonnets Adhesive polymer Interonnets Adhesive polymer Devies ubstrate ubstrate Vertial interplane interonnets (vias) Bulk CMO rd plane nd plane st plane Figure. hemati of a three-dimensional iruit []. These short interlayer vias replae the long interonnets along the edges of the die, yielding a onsiderable redution in wirelength. This behavior is verified by a number of wirelength distribution models desribed in the literature whih predit signifiant savings in the number of long interonnets. The fundamental assumption of these models is that Rent s rule [5] an be applied to threedimensional partitions. More speifially, Joyner [6] extended a stohasti model for -D iruits introdued by Davis [7] to threedimensions. Rahman [8] also used the Davis model as the basis for his -D interonnet distribution model. Although wirelength redution is an attrative feature of -D ICs, volumetri design poses a number of hallenges. Plaement and routing algorithms are examples of suh a hallenge, sine another degree of freedom is added to the design proess [9]. Certain 0

2 transformations an be applied to onvert a -D routing problem to a -D routing task [0]. In addition, novel CAD tools are required for three-dimensional iruits. Reently, suh CAD tools have been published [] that validate the interonnet predition model desribed in [8]. In all of these algorithms, however, the partiular nature of the interlayer interonnets is not onsidered. Additionally, delay expressions used in the aforementioned interonnet predition models for -D iruits are similar to traditional CMO models, negleting the impat of the vias and the non-uniform impedane harateristis of these lines. Zhang et al. [] onsider the effet of the vertial vias on the interlayer interonnets in their delay expression by modeling the line with different impedanes; however, they apply two restritive assumptions. First, that the via is always plaed in the mide of the line, independent of the line length and, seond, eah horizontal segment of the interonnet has the same impedane harateristis. As shown in this paper, the former assumption leads to severe performane inauray, while the latter assumption does not aurately depit the physial nature of the interlayer interonnets. The optimum via loation that yields the minimum propagation delay of the line is determined in this work. The effet of the via length, or equivalently, the number of physial planes that the via spans, on the propagation delay of the line is also investigated. The inlusion of variable via loations into routing algorithms and a variable number of physial planes in plaement algorithms will onsiderably enhane the effiieny of the -D design proess. The rest of the paper is organized as follows. In the following setion, the problems are formulated, and various traits of the interlayer -D interonnets are outlined. For a fixed via length, the optimum via loation to minimize the propagation delay of these interonnets is desribed in etion. Additionally, onditions for the minimum propagation delay, where the via length and loation are varied, are desribed. Expressions for the via length and loation that yield the minimum delay are also provided. In etion 4, simulation results are presented, verifying the theoretial results presented in etion. Finally, in etion 5, some onlusions are offered.. PROBEM FORMUATION The problems explored in this paper an be better explained with the aid of Figure, where a ross setion of a three-dimensional manhattan grid is illustrated. The irles and the bold solid, dashed, and dotted lines represent possible plaement loations and routing paths, respetively. ine the overall performane is typially based on the delay of the long interonnets, it is assumed that these interonnets are routed first, thus multiple routing paths are possible. In Figure a, two iruits are plaed on two different devie layers. The total and interlayer distanes are fixed. The via loation (the length of the horizontal segments of the line), however, is allowed to hange, as shown by the dashed and dotted routing paths. In Figure b, not only does the length of the horizontal segments hange, but also the via is allowed to span a variable number of planes. In the first ase, the optimum via loation that minimizes the propagation delay is determined, while in the seond ase, both the optimum via loation and number of planes that the via traverses are determined. Beause the total geometri length for all of the possible routing paths is the same, in most plaement and routing algorithms a typial riterion to determine the most appropriate via loation and/or number of planes is to selet the routing path and/or plaement loation that yields the minimum routing blokage. This harateristi ours beause in -D iruits, interonnets are usually onsidered to oupy a single metal layer and to be of uniform impedane throughout the length, and the via loation and impedane are assumed to not affet the delay of the line. This assumption is no longer valid, however, for interlayer interonnets in three-dimensional iruits, as shown in Figure. To model interlayer interonnets as an assemblage of non-uniform segments is justified by the physial nature of -D ICs. For example, the iruit an be plaed on more than one die and therefore proess variations not only exist within a single die (intradie) but also die-todie (interdie) variations should be onsidered. Consequently, interonnet impedanes in different physial planes an differ from eah other by a non-negligible amount. In addition, -D ICs may ombine dies from totally disparate tehnologies, resulting in different interonnet parameters for eah physial plane. Furthermore, eah segment of the interlayer interonnet an be laid out on different metal layers, whih exhibit different impedane harateristis. Also, the oupling apaitane between eah segment will vary, as the interonnet struture that surrounds eah segment is typially different. Consider the ase where a -D iruit onsists of only two physial planes and the bonding proess is similar to that illustrated in Figure. The metal layers of the bottom physial plane will exhibit a greater line-to-ground apaitane beause the layers are sandwihed between two substrates, while for those interonnets within the upper plane, the same apaitane omponent is smaller due to the absene of a nearby seond substrate. Figure. Interlayer interonnet (a) with multiple routing paths, (b) with multiple plaement loations and routing paths. Figure. Interlayer interonnet and orresponding model, omposed of a set of non-uniformly distributed RC segments. The Elmore delay model has been adopted to analyze the propagation delay of these interonnets. If auray is an issue, a fitted Elmore delay model an be used []. However, unlike a single plane, more than one set of fitting oeffiients is required in a -D system. In the following setion, the optimum via loation problem is further explored.

3 . OPTIMUM VIA OCATION In this setion, two variants of the optimum via loation problem, whih enhane the task of routing and plaement for interlayer interonnets in -D iruits, are onsidered. In the first subsetion, the optimum via loation of an interonnet, for a fixed via length, is provided. The ase where the via length onstraint is removed is investigated in the seond subsetion.. Fixed number of physial planes An interlayer interonnet that onnets two iruits loated on two different physial planes is depited in Figure. As mentioned previously, due to the non-uniformity of the interonnets, eah segment is modeled as a distributed RC line with different impedane harateristis (see Figure ). Indutane is not onsidered in this work. The driver is modeled as a step input voltage and a linear resistane R, and the interonnet is terminated with a apaitive load C. The total resistane and apaitane of segment i are R i r i l i and C i i l i, where r i and i denote the resistane and apaitane, respetively, per unit length and l i is the length of the segment. The length of the horizontal segments is l and l and the via length is l. ine the via may span more than one physial plane, l an be expressed as l ( n ) l v, () where n is the number of physial planes making up the onneted iruits and l v is the length of the via that interonnets two metal layers loated in two adjaent physial planes. This value is determined by the fabriation proess and an range from 5 µm to 70 µm [], [4]. The total length of the line an be expressed as The Elmore delay for the system is l +. () + l l RC RC Tel + CR + + C + C ( R + R + R ) + C ( R + R ( R + R ) RC + + R + R ). ubstituting the total resistane and apaitane with the per unit length parameters, and using () and (), the Elmore delay desribed in () an be written as a funtion of the length of the first segment l, where ) ( ) ( r r r ) () T el ( l A l + A l + A, (4) A +, (5) Rs ( ) + ( n ) ( r r + r r ) ( r r ) + C ( r r ), A A R (( n ) l ( ) + ) + (( n ) l ) v v + r (6) r r + + r ( n ) ( r r ) + C (( n ) ( r r ) + R + r ) +. (7) Equation (4) desribes a parabola, but the existene of a minimum is not guaranteed. The seond derivative of (4) with respet to l is d Tel A. (8) Depending upon the sign of A, the propagation delay of the line will exhibit either a minimum or a maximum as l varies or, alternatively, as the loation of the via along the line hanges. The following notations are introdued to failitate the analysis, r a, r b, r m, and r From (9), the seond derivative is d Tel ( a + ) r b v. (9). (0) ine r is always positive, the sign of (0) and, onsequently, the timing behavior of the line only depends upon the sign of the term in the parentheses. For the propagation delay to be minimum, the following inequalities should be satisfied, a >, or b > d Tel b (,], a (,] > 0 () b ( 0, ], a (,], and a > b a ( 0, ], b (,], and b > a. If the inequalities in () are not satisfied, the delay of the line exhibits a maximum. The existene of either a minimum or maximum delay with the via loation depending on the values of a and b an be roughly explained as follows. Negleting the via, the line omprises two segments with different impedane harateristis. Alternatively, a non-uniform line an be seen as a uniform tapered line that only onsists of two segments. etting r r 0 /w, r r 0 /w, 0 w, and 0 w, a and b desribe the tapering fator of the line. It has been shown that an optimum tapering fator exists in terms of the delay, where the width of the line dereases towards the reeiver [5]. If a is greater than one, the tapering dereases. The value of l for whih the delay exhibits an extremum, either minimum or maximum, is ( r r + r r ) ( n ) A r r + r l A Rs ( ) ( ) ( ) + r r + C r r r r + r +. () ine no restritions have been applied on the value of l, the extreme point an our for values other than within the physial l 0 l where l 0 -l -l min. l min is the minimum domain of l, i.e., [ ], 0 distane between a via and a ell, determined by the design rules of the fabriation proess. The following emma is used to determine the optimum via loation for various values of a, b, and l. The proof is omitted due to spae limitations. emma : If f(x) Ax d f(x) +Bx+C and < 0 then dx (a) for x max [0,x 0 ] x0 x0 (i) if x max >, f(0) < f(x 0 ), (ii) if x max <, f(0) > f(x 0 ), (b) for x max < 0, f(0) > f(x 0 ), () for x max > x 0, f(0) < f(x 0 ). Depending upon the sign of (0) and the value of l in (), the optimum via loation is determined for eah possible ase: d T A) el > 0. If l [ 0, l0 ], the propagation delay is minimized when l is the value desribed in (). Consequently, the via should be plaed at a distane l from the driver. The Elmore delay for a 5 mm line is illustrated in Figure 4 versus the via loation l. Two

4 observations an be made. First, that the delay exhibits a minimum and that the minima position shifts to the right as a inreases. If l < 0, the via should be plaed losest to the driver, while if l > l 0, the via should be plaed losest to the reeiver. d T B) el < 0. In this ase, the delay of the line reahes a maximum for the value of l desribed in (). If l [ 0 l ], 0, aording to emma, for l < l 0 /, the via should be plaed losest to the reeiver, while for l > l 0 /, the via should be plaed losest to the driver. In Figure 5, the Elmore delay of a 5 mm line is shown as a funtion of the via loation l. Note that the delay reahes a maximum and that the maximum shifts to the right as b inreases. If l < 0, the via should be plaed losest to the reeiver, while if l > l 0, the via should be plaed losest to the driver. T el [nse] Minima a. a.7 a. a.7 a 4. a l [mm] Figure 4. Propagation delay of a 5 mm line versus via loation l for various values of a. The interonnet parameters are r 76 W/mm, r 5 W/mm, ff/mm, 79 ff/mm, b.674, l v 0 µm, and n. The driver resistane and load apaitane are R 40 W and C 80 ff, respetively. d Tel C) 0. If the seond derivative equals zero, (4) beomes T el ( l) Al + A, () whih is a linear funtion of l. The first derivative of (4) is equal to A. For A < 0, (4) is stritly dereasing, and the delay is a minimum by plaing the via losest to the reeiver. For A > 0, (4) is stritly inreasing, and the delay is a minimum by plaing the via losest to the driver. Note that the fundamental minimum distane of a via from a ell is tehnology dependent. In the speial ase where a b, from (6) and (7), A << A and the delay is independent of l. However, as n inreases, A also inreases and the hoie of n affets the rate of hange in the delay, as disussed in the following setion. As illustrated in Figure 4, the optimum via loation shifts to the right (left) when a inreases (dereases). The same applies to Figure 5 in terms of b. To explain this behavior, onsider the definitions of a and b in (9), where a (b) desribes the resistane (apaitane) ratio of the horizontal segments. Referring to Figure 4, both a and b are greater than one, whih means that segment is less (more) resistive (apaitive) than segment. Assuming for the moment that a, the delay of the line dereases as the length of the more apaitive segment l (i.e., C ) dereases. However, l does not vanish beause C inreases as l dereases, approahing C. Consequently, as l is dereased beyond a ertain distane, desribed in (), the delay starts to inrease. As a inreases, the optimum point ours at values of l > l 0 /, although segment is more apaitive than segment (b > ). This behavior ours beause the delay depends not only on the apaitane, but also on the urrent, whih is ontrolled by the resistane of eah segment. In the ase where b >> and a <<, where segment is both more apaitive and resistive than segment, l beomes small to redue the overall delay and, in this ase, () yields negative values for l. imilar arguments apply to the dependene of the optimum via loation on b shown in Figure 5. In the following subsetion, the optimum via loation and number of planes in terms of the propagation delay are determined for a variable number of planes n. T el [nse] b 0.5 b 0.55 b 0.6 b 0.65 b 0.7 b 0.75 b 0.8 b 0.85 Maxima l [mm] Figure 5. Propagation delay of a 5 mm line versus via loation l for various values of b. The interonnet parameters are r 9 W/mm, r 4 W/mm, 96 ff/mm, 86 ff/mm, a 0.47, l v 0 µm, and n. The driver resistane and load apaitane are R 40 W and C 80 ff, respetively.. Variable number of physial planes If the number of physial planes is varied, multiple plaement loations an exist, and (4) beomes ( l l ) r ( F l + F l l + F l + F l + F l ) T el +, (4) where, 4 5 F6 ( ) ( a + ) F, F ( v m + ), (5) b mv a F m + a R C 4 r, (6), F ( b ) + + ( a) R C F5 ( v ) + ( m a) r +, (7) C R C F6 + + a + a. (8) r Equation (4) is a quadrati funtion with respet to l and l, and desribes a paraboloid. As a polynomial funtion is both ontinuous and differentiable, global extrema exist whih an our either on the boundary, or the interior of the domain of l and l. The solutions of the gradient T el ( l,l ), whih are alled ritial points, desribe possible interior extrema. The interior point at whih the delay an exhibit an extremum is

5 ( ab va + m mb + v v + vmb ) Rs l r (( v + m) + mv( b + a) + ab mb va v m ) (9) r ( C + )( va m)( m), r (( v + m) + mv( b + a) + ab mb va v m ) ( R + r ( C + ) )( m mb + ab av + v ) l. (0) r (( v + m) + mv( b + a) + ab mb va v m ) From multivariable alulus, the interior ritial point is a minimum for (4) when (9) and (0) satisfy the following onditions, ( l, l ) Tel H r F > 0, () l H r ( l, l ) T ( l, l ) T ( l, l ) Tel l ( 4F F F ) > 0. el l el l l () ine (4) is a quadrati funtion, both () and () are independent of the ritial points of (4) and the values depend only on the ratios desribed in (9). Depending upon these values, the following ases are distinguished: A) H > 0, H > 0. The delay is a minimum in terms of both the via loation and length. The optimum via loation is given by (9), while the optimum number of planes n opt is obtained after the disreteness onstraints for variable l, desribed in (0), are applied aording to (), l l +, if l < + n opt () l l +, if l > +, where, in (), [x] denotes the integer part of number x. In Figure 6, the Elmore delay of a 5 mm line is plotted versus the via loation l and the via length l. The global minimum is depited in Figure 6 by the dot. Figure 6. Propagation delay of a 5 mm line versus via loation l and via length l. The interonnet parameters are r 5 W/mm, 88 ff/mm, a., b.85, m., and v.5. The driver resistane and load apaitane are R 476 W and C 88 ff, respetively. B) H < 0, H > 0. The delay is a maximum for the values of l and l desribed in (9) and (0), respetively. In this ase, the optimal point both for the via loation and length is on the boundary of the domain of l and l, whih defines a retangle. earhing in the subset of boundary points that onsists of the verties of the retangle, namely T el (l min, l v ), T el (l min, (n max -)l v ), T el (-l v -l min, l v ), and T el (-(n max -)l v -l min, (n max -)l v ) suffies for the minimum delay to be determined. n max is the maximum number of staked planes permitted by the target tehnology. The point that yields the smallest delay provides the optimal values for l and l. C) H < 0. If () is negative, (9) and (0) do not represent an extremum but rather a sade point. The optimal point is again loated on the boundary. Note that in this ase, depending on the signs of F and F, a different subset of boundary points should be examined to determine the optimal values of l and l. In addition, seleting the number of planes an be based on other riteria as disussed in the following setion, where simulation results are presented. 4. REUT AND DICUION In this setion, experimental results are presented and a disussion of the proposed approah is offered, partiularly for those ases where the minimum ours at the boundary. The analysis has been applied to interonnets with lengths ranging from mm to 0 mm, for different interonnets parameters. The ratios in (9) range from 0. to 0, and over all pratial ases of interest. The maximum variation in delay with the length of the segment l (or equivalently the via loation) for different line lengths and interonnet parameters is listed in Table. This variation expresses the differene between the delay of the line when the via is plaed at the optimum point and the delay of the line when the via loation oinides with a point lose to either the reeiver or the driver. It is assumed that the physial design rules impose a minimum 0 µm distane between a via and a ell. The number of planes is equal to two and the via length is assumed to be l l v 0 µm [4]. As listed in Table, the optimum via loation shifts to the right as a inreases, in agreement with the theoretial results depited in Figure 4. In Table, the optimum via loation and number of planes for different line lengths are listed. In this ase, the minimum via length l v 50 µm. As mentioned in etion, a minimum does not exist if () is negative and the values of l and l, from (9) and (0), respetively, orrespond to a sade point. In addition, (0) may result in an infeasible solution, sine the maximum number of planes that an be staked n max is tehnology limited. In these ases, the optima our at the boundary of the domain of l and l. Thus, either n or n n max should be seleted depending upon whih value produes the smaller delay. The hoie of the number of planes n an also be based on a different riterion than the propagation delay. For example, if the impedane parameters of the via are muh greater than those of the horizontal segments (m, v >> ), n an be inreased suh that the delay of the line does not vary signifiantly as the via loation hanges. Alternatively, if the impedane parameters of the line segments are of similar value, the number of planes n an be seleted suh that the delay with respet to l is a minimum when the via is plaed at the enter of the line. In this ase, the variation of the line delay with via loation is smallest, as shown in Figure 4, for a.7. Thus, if an inrease in the overall delay is aeptable, the number of layers n an be hosen suh that the skew between interonnets (e.g., lok skew) varies slowly with via loation. 4

6 5. CONCUION The interlayer via loation and length to minimize the signal delay in -D systems is desribed in this paper. The Elmore delay model is adopted to investigate the propagation delay of interlayer -D interonnets. The non-uniform impedane harateristis of the line are also onsidered. The propagation delay of the interonnet is shown to depend both on the via loation and the number of planes that the via vertially traverses. Expressions for the optimum via loation and number of planes are provided. imulation results verifying these expressions are also presented. The proposed design expressions an be used to enhane plaement and routing algorithms targeting -D ICs. 6. REFERENCE [] R. J. Gutmann et al., Three-dimensional (D) ICs: A Tehnology Platform for Integrated ystems and Opportunities for New Polymeri Adhesives, Proeedings of the Conferene on Polymers and Adhesives in Miroeletronis and Photonis, pp. 7-80, Otober 00. []. Xue, C. iu, and. Tiwari, Multi-layers With Buried trutures (MB): An Approah to Three-dimensional Integration, Proeedings of the IEEE International Conferene on ilion On Insulator, pp. 7-8, Otober 00. [] M. Koyanagi et al., Future ystem-on-silion I Chips, IEEE Miro, Vol. 8, No. 4, pp 7-, July/August 998. [4] A. Fan, A. Rahman, and R. Reif, Copper Wafer Bonding, Eletrohemial and olid-tate etters, Vol. 0, No., pp , Otober 999. [5] B. andman and R. Russo, On a Pin vs. Blok Relationship for Partitions of ogi Graphs, IEEE Transations on Computers, Vol. 0, No., pp , Deember 97. [6] J. W. Joyner et al., Impat of Three-dimensional Arhitetures on Interonnets in Gigasale Integration, IEEE Transations on Very arge ale Integration (VI) ystems, Vol. 9, No. 6, pp. 9-97, Deember 000. [7] J. Davis and J. Mein, A tohasti Wire-length Distribution for Gigasale - Part I: Derivation and Validation, IEEE Transations on Eletron Devies, Vol. 45, No., pp , Marh 999. [8] A. Rahman and R. Reif, ystem-level Performane Evaluation of Three-dimensional Integrated Ciruits, IEEE Transations on Very arge ale Integration (VI) ystems, Vol. 8, No. 6, pp , Deember 000. [9] A. Cohoon et al., Physial ayout for Three-Dimensional FPGAs, Proeedings of the ACM/IGDA Physial Design Workshop, pp. 4-49, April 996. [0] C. C. Tong and C.-. Wu, Routing in a Three-dimensional Chip, IEEE Transations on Computers, Vol. 44, No., pp. 06-7, January 995. []. Das et al., Calibration of Rent s Rule for Three-Dimensional Integrated Ciruits, IEEE Transations on Very arge ale Integration (VI) ystems, Vol., No. 4, April 004. [] R. Zhang et al., tohasti Modeling, Power Trends, and Performane Charaterization of -D Ciruits, IEEE Transations on Eletron Devies, Vol. 48, No. 4, April 00. [] A.I. Abou-eido, B. Nowak, and C. Chu, Fitted Elmore Delay: A imple and Aurate Interonnet Delay Model, IEEE Transations on Very arge ale Integration (VI) ystems, Vol., No. 7, pp , July 004. [4] P. Ramn et al., InterChip Via Tehnology for Vertial ystem Integration, Proeedings of the IEEE International Interonnet Tehnology Conferene, pp. 60-6, June 00. [5] C.-P. Chen et al., Optimal izing Formula Under the Elmore Delay Model, Proeedings of the International ACM/IEEE Design Automation Conferene, pp , June 996. Table. Maximum delay variation and optimum via loation for different interonnet lengths and impedane parameters r 86 Ω/mm, r 5 Ω/mm, 79 ff/mm, 96 ff/mm, b., C 80 ff, and l v 0 µm mm, R 40 Ω mm, R 40 Ω a Del. Variation (%) l opt [mm] mm, R 940 Ω 4 mm, R 940 Ω a Del. Variation (%) l opt [mm] mm, R 560 Ω 6 mm, R 560 Ω a Del. Variation (%) l opt [mm] mm, R 0 Ω 8 mm, R 0 Ω a Del. Variation (%) l opt [mm] mm, R 0 Ω 0 mm, R 0 Ω a Del. Variation (%) l opt [mm] Table. Optimum via loation l and number of physial planes n for different interonnet lengths and impedane parameters Inter. ength l opt [mm] n opt a b m v R [Ω] C [ff] r [Ω/mm] [ff/mm] mm mm mm mm mm