Improved Circuit-to-CNF Transformation for SAT-based ATPG

Transcription

1 Improved Ciruit-to-CNF Transformation for SAT-based ATPG Daniel Tille 1 René Krenz-Bååth 2 Juergen Shloeffel 2 Rolf Drehsler 1 1 Institute of Computer Siene, University of Bremen, Bremen, Germany {tille,drehsle}@informatik.uni-bremen.de 2 NXP Semiondutors Germany GmbH, Hamburg, Germany {rene.krenz-baath,juergen.shloeffel}@nxp.om Abstrat SAT-based ATPG has proven to be a benefiial omplement to traditional ATPG tehniques. The generation of a CNF-representation is a vital issue in SAT-based test pattern generation. Firstly, the generation of the problem instanes for SAT-based ATPG requires a signifiant portion of the overall runtime. Seondly, the performane of the SAT solver strongly depends on the properties of the resulting CNF-representation. The ontribution of this paper is a new approah to generate CNF-representations for SAT-based ATPG. The objetive of the proposed tehnique is to speed up the generation proess and to optimize the resulting CNF-representation with respet to the SAT omputation. The experimental results, obtained on large industrial designs, show that the aomplished optimizations result in a signifiant redution of the overall runtime of the SAT-based test pattern generation proess. Finally we disuss how this ontribution enables some promising future work. I. INTRODUCTION The ontinuous growth of today s iruit designs requires a onstant improvement of state-of-the-art omputer-aided design (CAD) and omputer-aided test (CAT) tools. During reent years SAT-based ATPG algorithms beame a promising alternative to traditional ATPG tehniques suh as FAN [1] and PODEM [2]. In partiular for hard-to-solve problem instanes SAT-based methods proved to be highly advantageous [3], [4], [5], [6]. However, SAT-based ATPG algorithms suffer from a number of disadvantages. Most modern SAT-solvers [7], [8], [9], [10] require the modeling of the problem in Conjuntive Normal Form (CNF). Hene the ATPG problem needs to be onverted into one or several CNF-representations. Furthermore SAT-based ATPG tehniques tend to deliver overdetermined test pattern whih is disadvantageous with respet to pattern ompation and runtime. The ontribution of this paper is a new approah to effiiently generate CNF-representations for SAT-based ATPG. The proposed tehnique employs Redued Ordered Binary Deision Diagrams (ROBDDs) [11] in order to generate optimized CNF-instanes during test pattern generation. The This work was done during a researh visit at the NXP development enter in Hamburg, Germany. new approah onstruts ROBDD-representations of Fanout- Free Regions (FFRs) in the iruit graph, where every FFR is treated as an individual sub-iruit. To derive CNFrepresentations diretly from these ROBDDs provides several advantages over traditional approahes. Funtional redundanies ontained in the FFR will not be refleted by the resulting CNF. Furthermore the number of CNF-variables is redued drastially. Finally the number of CNF-lauses in the problem instanes is onsiderably dereased. The experimental results show that the proposed approah is a promising alternative to traditional iruit-to-cnf transformation tehniques. The paper is strutured as follows. Previous work is disussed in Setion II. The proposed approah is the objetive of Setion III. Experimental results are presented in Setion IV. Setion V onludes the paper and disusses future work. A. SAT-based ATPG II. PREVIOUS WORK Test pattern generation with respet to some Stuk-At Fault (SAF) is the searh for an input assignment, whih onduts different values at some primary output between the faulty iruit and the orret iruit. SAT-based ATPG was initially proposed by Larrabee in [3]. Signifiant improvements were ahieved by Stephan et al. in [12] and by Silva and Sakallah in [13]. In SAT-based ATPG the problem of finding a suffiient input assignment is transformed into a Boolean satisfiability problem suh that if a test for a partiular SAF exists, then the orresponding problem instane is satisfiable and the resulting test pattern an be diretly derived from the satisfying assignment. If the fault is undetetable the SAT solver onludes unsatisfiability. In the following the iruit-to-cnf transformation for an SAF is reviewed. Figure 1 illustrates a ombinational iruit. The fault loation denotes a onnetion where an SAF is assumed. The area denoted as output one, ontains all gates belonging to some path P from to some primary output in the reflexive fanout of, fanout ({}). Let us denote the set of primary outputs reahable from by O. Next the reflexive

2 fault loation a reflexive fanin output one b Fig. 1. Illustration of influened iruit areas. (a + b + ) (a + b + ) (a + ) fanin, fanin (O ), of all primary outputs in O is omputed, see Figure 1. As introdued in [4], two Boolean variables G(v) and G f (v) are assigned to every gate v in the reflexive fanout of, v fanout ({}), to represent the fault free iruit and the faulty iruit, respetively. Both iruits are generated by building the harateristi funtion for every gate. Clearly all gates belonging to the reflexive fanin of some primary output in the set O and are not ontained in fanout ({}) only need to be modeled one, sine the SAF at does not influene their behaviour. To express a differene of the values at G(v) and G f (v), additionally a Boolean variable G d (v) is assigned to every gate v fanout ({}). If G d (v) is true, then the values G(v) and G f (v) differ. A test pattern to detet the SAF at is found if it is possible to ompute an assignment suh that there exists a path P from to some primary output, where the variable G d (v) for eah gate v P is true. This path is alled D-hain. B. ROBDDs The proposed tehnique employs ROBDDs as a anonial representation of Boolean funtions [11]. Canoniity allows signifiant performane improvements for operations suh as equivalene heking or satisfiability heking. Additionally ROBDDs are a highly effetive representation for large ombinational sets, whih is ruial for model heking tasks [14]. Given an ROBDD representing some Boolean funtion a CNF of this funtion an be generated as follows: Let P be a path from the root node to the zero-terminal node. A lause an be derived by the disjuntion of the omplement of eah variable ourring in P. In Figure 2 an example for this ROBDD-to-CNF onversion is given. An ROBDD onsisting of three variables is depited in Figure 2(a). The solid lines represent the high-edges and the dashed lines represent the low-edges. The CNF desribing the same Boolean funtion as the ROBDD is given in Figure 2(b). To generate the CNF all paths from the root node (labeled with a) to the zero-terminal node (labeled with 0) have to be traversed. Sine there exist three suh paths in the ROBDD the CNF onsists of three lauses. The first lause is derived by applying the approah explained above to the path onsisting of all high-edges. The seond lause (along a high b low low ) and the third lause (along a low low ) are built the same way. Fig (a) 0 (b) Example for the ROBDD-to-CNF onversion: (a) ROBDD, (b) CNF. As mentioned above the number of lauses in the CNF is equal to the number of zero-paths in the ROBDD. Unfortunately in the worst ase the number of zero-paths is exponential with respet to the number of nodes (e.g., the EXOR funtion). A sophistiated approah whih introdues auxiliary variables in order to redue the number of paths in the ROBDD is proposed in [15]. The minimization of the number of paths in an ROBDD using different sifting strategies is desribed in [16]. III. IMPROVED CIRCUIT-TO-CNF TRANSFORMATION The traditional approah to derive a CNF-representation from a iruit graph is desribed in Setion II. The CNFrepresentation of every single gate is generated without onsideration of the adjaent iruit struture. It is obvious that this onept, although simple, does not generate a ompat CNF-representation of the problem instane. The goal of the proposed tehnique is to inrease the effiieny of the CNF-generation proess itself and to improve the properties of the generated problem instane with respet to the sueeding reasoning proess. This is aomplished by first generating an ROBDD-based representation of speifi parts of the iruit graph, and later on deriving the orresponding CNFs from these ROBDDs. The iruit is deomposed along Fanout-Free Regions (FFRs) in the iruit graph, where eah FFR is treated as an individual sub-iruit. The D-hains (f. Subsetion II-A) are build along FFRs, i.e. variables G d are only assigned to FFR-output gates. A. Observations The proposed approah is based on the following observations: 1) Kuehlmann and Krohm showed in [17] that industrial iruits ontain a large amount of funtional redundanies. A CNF derived from the orresponding ROBDD

3 a b d e f g h FFRh i j FFRk k (d + b + ) (d + b) (d + ) (e + b + ) (e + b) (e + ) (h + f + g) (h + f) (h + g) (f + d) (f + d ) (g + e) (g + e ) Fig. 3. Illustrative example. (a) will not reflet these redundanies. This yields a redution in the number of lauses and the amount of CNFvariables in the resulting problem instane. 2) The presented tehnique works similar to the onept of supergates, where a set of gates in a iruit graph is merged to a larger gate [18]. Thus the number of CNFvariables required to generate the CNF of this set of gates is signifiantly smaller than the amount of CNFvariables produed by the traditional approah. 3) We observed that numerous FFRs or their subfuntions are funtionally equivalent. Treating FFRs as independent sub-iruits leads to an inreased sharing of ROBDD-strutures for the representation of several funtionally equivalent iruit-strutures. Note that we refer to the funtional equivalene of gates with respet to the inputs of individual FFRs. B. Illustrative Example The following example larifies the observations disussed in Subsetion III-A. The iruit graph depited in Figure 3 ontains two FFRs, named FFR h and FFR k orresponding to the names of their output gates. The set of gates belonging to the individual FFRs is indiated by dotted lines. Considering FFR h it is easy to see that gates d, e, and h implement the same Boolean funtion, b, with respet to the FFR-inputs b and. Transforming these gates in the traditional way would require 7 CNF-variables and 13 lauses. The proposed tehniques would instead generate only 3 CNFvariables and 3 lauses. These improvements are expliitly obtained through redundany removal as desribed in the first observation in Subsetion III-A. Figure 4 presents two alternative CNF-representations of the Boolean funtion implemented by FFR h in Figure 3. Part (a) of Figure 4 shows the CNF-representation obtained using the traditional approah, where a CNF is generated for every single gate in the iruit graph. This tehnique introdues a CNFvariable for every single gate ontained in the FFR and ignores possible redutions with respet to adjaent gates. Figure 4(b) ontains the result of the ROBDD-to-CNF transformation, where the CNF-representation is derived from the BDD-based representation of FFR h as desribed in Subsetion II-B. Generating the CNF-representation of the Boolean funtion implemented by FFR k in the traditional way would require 6 CNF-variables. As desribed in the seond observation, it is possible to redue the number of required CNF-variables to 4 (h + b + ) (h + b) (h + ) (b) Fig. 4. CNFs of the example: (a) Traditionally derived CNF, (b) ROBDDderived CNF. by treating the FFR as a single but more omplex gate. As mentioned above every FFR is treated as an individual Boolean funtion. Variables used in the orresponding ROBDD-representations are re-used for every individual FFR. Let us assume that the ROBDD-variables x 1, x 2, and x 3 are assigned to the FFR-inputs a, h, and, respetively, of FFR k. Furthermore we assume the order of the ROBDD-variables to be x 1, x 2, x 3. Then the generated ROBDD-struture an be partially re-used to also represent the funtion implemented by FFR h, assuming that the FFR-inputs b and are assigned to x 1 and x 2, respetively. In pratie this feature ontributes to a dramati redution of the number of generated ROBDDnodes and hene a signifiant improvement with respet to the memory onsumption. C. Implementation Details In the following we disuss issues regarding the implementation of the proposed tehnique. The onstrution of the ROBDD-based representations is aomplished during a preproessing step. This means the iruit-to-robdd onversion is performed only one. As BDD pakage we hoose to apply the well-known CUDD pakage [19] version CNF-representations of individual FFRs are generated multiple times during a omplete ATPG run. In the urrent implementation the initially omputed ROBDDs will be repeatedly used during the entire ATPG run. The derivation of the CNF from the orresponding ROBDDrepresentation is disussed in Setion II. The number of literals ontained in the generated CNF-lauses is signifiantly redued by using the prime impliants in the ROBDDs. The mapping of ROBDD-variables onto the orresponding CNF-variables is aomplished during every individual CNFgeneration. During first experiments it was observed that the number of prime impliants and hene the number of lauses derived from an ROBDD often exeed the number of lauses generated by the traditional approah. We observed that this

4 situation appears frequently for ROBDD-representations of FFRs with more than 16 inputs. Therefore it was deided to add two limitations in order to prevent suh an inrease of the CNF size. Firstly a iruit-to-robdd transformation is only performed for FFRs with 16 or less inputs. Seondly the number of lauses generated by the traditional approah is estimated. FFRs whose ROBDD-representation exeeds this limit are not onsidered during the sueeding ROBDD-to- CNF transformation. The estimation is based on the following two assumptions: the FFR does only ontain two-input gates, and the CNF-representation of every individual gate in the FFR would require three lauses, e.g., AND, NAND, OR, NOR. Based on these assumptions the following ost funtion an be formulated: n lauses = 3(n inputs 1), where n lauses denotes the estimated number of lauses, and n inputs represents the number of FFR-inputs. For example the estimated amount of resulting lauses for a 4-input FFR and for an 11-input FFR would be 9 lauses and 30 lauses, respetively. Furthermore, the urrent implementation does only onstrut ROBDD-representations of FFRs whih do not require an enoding for four-valued logi. IV. EXPERIMENTAL RESULTS This setion ontains an experimental evaluation of the proposed tehnique. We will demonstrate that the new approah redues the number of variables and the number of lauses in the problem instane signifiantly. The obtained runtime improvements onfirm that the proposed optimizations result in a onsiderable speed-up of the atual pattern generation. The new tehnique was integrated into a prototype version of the NXP Semiondutors ATPG tool AMSAL and applied to a set of benhmarks onsisting of four large industrial designs. The used SAT-solver is MiniSat version 1.14 [10]. The experiments were performed on a PC equipped with a 2.4 GHz AMD Opteron 880 CPU and 64 GByte main memory running RedHat Enterprise 4. Table I provides a first set of experimental results. Columns one to four ontain information about the iruits, suh as benhmark name, number of inputs, number of outputs, and number of targets, respetively. The set of targets ontains all remaining faults after fault ollapsing. The name of the benhmark reflets the approximate number of gates ontained in the iruit. For example benhmark p141k ontains roughly 141,000 gates. Building all ROBDDs for the tested designs as proposed in Setion III requires less than two seonds of CPU time and the additional memory onsumption does not exeed 50 MByte. Further details about the number of FFRs transformed into ROBDDs and the CNF-size savings are given in Table II. TABLE I BENCHMARK STATISTICS AND RESULTS OBTAINED BY THE PRESENTED ALGORITHM IN COMPARISON TO THE TRADITIONAL APPROACH USING A SET OF INDUSTRIAL BENCHMARKS. runtime runtime Benhmarks Inputs Output Targets without ROBDDs with ROBDDs p141k 11,290 10, ,946 5:23h 3:44h p267k 17,332 16, ,773 16:27m 10:53m p330k 18,010 17, ,756 1:48h 1:38h p418k 30,430 29, ,022 3:42h 3:33h TABLE II FURTHER RESULTS OBTAINED BY THE PRESENTED ALGORITHM IN COMPARISON TO THE TRADITIONAL APPROACH. % % % Benhmarks treated saved saved FFRs lauses CNF-vars p141k p267k p330k p418k Although only a subset of FFRs in the iruit graph has been onsidered, see seond olumn in Table II, runtime redutions of 30.65% and 33.84% for the designs p141k and p267k, respetively, have been obtained. However, the overall runtimes, listed in the most right olumn of Table I, do not reflet the ahieved improvements with respet to the atual runtime required to find a suffiient input assignment. In order to provide this information a set of diagrams is depited whih ontains individual SAT-runtimes for every omputed target. Figure 5 omprises four diagrams, whih diretly ompare the runtimes required by the SAT-solver with and without the proposed preproessing tehnique. Eah entry represents the omputation times onsumed for a single target. The runtime is onsiderably redued for a large number of targets. The seond set of diagrams, given in Figure 6, illustrates the ahieved improvements with respet to the number of lauses to model the Boolean funtion implemented by an individual FFR. Note that these results only reflet the lause redution of FFRs treated by the proposed tehnique. The number of lauses is onsiderably redued in nearly all ases. In partiular for larger FFRs the number of lauses ould be redued signifiantly. One reason for that is the higher likelihood of redundanies ontained in these FFRs. The redution of the number of lauses and the number of CNF-variables due to redundany removal is disussed in Setion III. Columns three and four in Table II report the perental redution of the number of lauses and the number of CNF-variables with respet to all FFRs treated by the proposed tehnique. V. CONCLUSIONS AND FUTURE WORK The ontribution of this paper is a new approah to effiiently translate a iruit-based ATPG problem into a orresponding CNF-representation. In ontrast to traditional approahes, whih onstrut the CNF-representation of every single gate without onsidering the adjaent iruit struture, the new tehnique generates the CNF-representation of a set

5 Fig. 6. FFRs. Fig. 5. Runtime omparison for individual targets. Number of lauses ontained in the CNF-representation of individual of gates. The proposed tehnique employs ROBDDs in order to redue the resulting problem instane with respet to the number of lauses and the amount of CNF-variables. The experimental results onfirm that the overall runtime of the ATPG omputation an be signifiantly redued using the new tehnique. Our future work involves the appliation of the proposed onept to other fault models, e.g. the gate delay fault model and the path delay fault model. Additionally the tehnique an be extended to handle multiple-valued logi whih is ontained in many industrial iruits. ACKNOWLEDGEMENTS Parts of this researh work were supported by the German Federal Ministry of Eduation and Researh (BMBF) in the Projet MAYA under the ontrat number 01M3172B. REFERENCES [1] H. Fujiwara and T. Shimono, On the aeleration of test generation algorithms, IEEE Trans. on Comp., vol. 32, pp , [2] P. Goel, An impliit enumeration algorithm to generate tests for ombinational logi, IEEE Trans. on Comp., vol. 30, pp , [3] T. Larrabee, Test pattern generation using Boolean satisfiability, IEEE Trans. on CAD, vol. 11, pp. 4 15, [4] P. Stephan, R.K. Brayton, and A.L. Sangiovanni-Vinentelli, Combinational test generation using satisfiability, IEEE Trans. on CAD, vol. 15, pp , [5] J. Shi, G. Fey, R. Drehsler, A. Glowatz, F. Hapke, and J. Shlöffel, PASSAT: Effient SAT-based test pattern generation for industrial iruits, in IEEE Annual Symposium on VLSI, 2005, pp [6] D. Tille, S. Eggersglüß, G. Fey, R. Drehsler, A. Glowatz, F. Hapke, and J. Shlöffel, Studies on integrating SAT-based ATPG in an industrial environment, in GI/ITG Workshop Testmethoden und Zuverlässigkeit von Shaltungen und Systemen, [7] J.P. Marques-Silva and K.A. Sakallah, GRASP a new searh algorithm for satisfiability, in Int l Conf. on CAD, 1996, pp [8] M.W. Moskewiz, C.F. Madigan, Y. Zhao, L. Zhang, and S. Malik, Chaff: Engineering an effiient SAT solver, in Design Automation Conf., 2001, pp [9] E. Goldberg and Y. Novikov, BerkMin: a fast and robust SAT-solver, in Design, Automation and Test in Europe, 2002, pp [10] N. Eén and N. Sörensson, An extensible SAT solver, in SAT 2003, 2004, vol of LNCS, pp [11] R.E. Bryant, Graph-based algorithms for Boolean funtion manipulation, IEEE Trans. on Comp., vol. 35, no. 8, pp , [12] P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vinentelli, Combinational test generation using satisfiability, Teh. Rep. UCB/ERL M92/112, Dept. of EECS, Univ. of California, Berkeley, Otober [13] J.P. Marques-Silva and K.A. Sakallah, Robust searh algorithms for test pattern generation, Teh. Rep. RT/02/97, Dept. of Informatis, Tehnial University of Lisbon, Lisbon, Protugal, January [14] K.L. MMillan, Symboli Model Cheking, Kluwer Aademi Publisher, [15] G. Cabodi, S. Noo, and S. Quer, SAT-based bounded model heking by means of BDD-based approximate traversals, in Design, Automation and Test in Europe, 2003, pp [16] G. Fey and R. Drehsler, Minimizing the number of paths in BDDs: Theory and algorithm, in IEEE Trans. on CAD, 2006, pp [17] A. Kuehlmann and F. Krohm, Equivalene heking using uts and heaps, in Design Automation Conf., 1997, pp [18] S.C. Seth, L. Pan, and V.D. Agrawal, Predit - probabilisti estimation of digital iruit testability, in Int l Symp. on Fault-Tolerant Comp., 1985, pp [19] F. Somenzi, CUDD: CU Deision Diagram Pakage Release 2.3.1, University of Colorado at Boulder, 2001.