Alleviating DFT cost using testability driven HLS

Transcription

1 Alleviating DFT ost using testability driven HLS M.L.Flottes, R.Pires, B.Rouzeyre Laboratoire d Informatique, de Robotique et de Miroéletronique de Montpellier, U.M. CNRS rue Ada, Montpellier Cedex 5, Frane flottes@lirmm.fr, pires@lirmm.fr, rouzeyre@lirmm.fr Abstrat This paper presents a method to arry out the register alloation phase of High Level Synthesis with testability onsiderations. Testability problems are identified and eliminated during this step turning testability/area tradeoff to aount. It allows to derease the ost related to the appliation of low-level DFT tehniques. Keywords : High level test synthesis, resoure sharing, register alloation, DFT Introdution High Level Synthesis (HLS) onsists to generate a register transfer level (RTL) struture from a user provided behavior. In general, it is possible to obtain various RTL strutures that implement a given behavior. These strutures differ in some aspets, like area, speed, power or testability. HLS algorithms are guided by user provided onstraints in order to favor one or several partiular features. With respet to testability issues, many ommerial synthesis tools operate at lower level, namely at RT or gate level. They introdue dediated test strutures that may lead to the degradation of some harateristis of the iruit, like performane and area. In order to mitigate these onsequenes, it has been proposed in the early 90 s to take into aount testability at the beginning of design flow, namely during HLS. A survey of HLS for testability tehniques an be found in [], [2]. A favorable step in HLS for solving testability problems is the register alloation/binding phase. During this step a suffiient number of registers is determined for storing behavioral variables, and variables are assigned to aordingly. The large number of ahievable solutions and the strong impat of the solutions on the final struture give many possibilities to improve testability. Several tehniques have been proposed for register alloation with testability onsiderations. They may be divided into two lasses: synthesis of BISTed data paths and synthesis for external test by ATE (Automati Test Equipment). Aording to the BIST strategy, speial modules are added to the iruit: test pattern generators and signature analyzers. During synthesis, the objetives are a) to guarantee that all modules of the iruit will be appropriately tested, and b) to minimize the hardware and performane overhead due to the use of those additional test modules. Examples of suh tehniques are given in [3][4][5]. The present work is foused on the synthesis of data paths to be used in an external testing strategy. In a suh methodology, the proposed tehniques attempt essentially to maximize the number of variables mapped to I/O registers, to redue sequential depth and/or to minimize the formation of loops in the data path. The goal of the register alloation method proposed in [6] is to make the registers as easy to test as possible. For this, a two step proedure is used: a) assigning as many registers as possible to at least one primary input/output variable, thus reating easily ontrollable/observable registers, and b) reduing the sequential depth from ontrollable registers to observable registers (I/O registers). Note that the freedom of the register assignment proess is limited by the ompatibility among variables (their lifetimes must not overlap). The proposed sequential depth redution proess only onsiders the sequential depths values and does not take into aount the nature of rossed operators. A long path that ontains only operations that are favorable to test data propagation may be better than a short one with operations unfavorable to test data propagation. In [7], the goal is sequential loop redution. For data paths with a small number of yli data flows, a nonsan sheme is utilized, otherwise, partial san is applied. The alloation phases are arried out in the following sequene: register alloation, operators alloation and interonnetion alloation. To improve testability during these phases, the synthesis system tries: a) to avoid the reation of sequential loops due to improper resoure sharing, b) to break the sequential loops due to yli data flows, and ) to redue the sequential depth. Register alloation is onsidered to be the key point for ahieving these goals. During this phase, variables on the yli data flow are assigned to I/O or san registers, or sequential paths are introdued to an I/O or san register by appropriate register/operator sharing. Similarly, testability issues targeted in [8] relate to the formation of loops in the data path due to hardware sharing. An alloation sheme is presented to minimize the formation of suh loops. Remaining loops are broken by using a minimal number of san registers. However, a speifi arhiteture is assumed, based on the use of register files, where eah register file is onneted to one input of single funtional unit. The quality of test data propagation through various kinds of operators is not onsidered, as in [6]. Genesis [9] is a synthesis system that uses a table of property transformations assoiated to the arithmeti operators to hek the existene of a test environment (justifiation and propagation paths) for eah module in

2 the data flow graph (DFG). Register alloation and operator alloation are performed simultaneously while minimizing interonnetion. If during alloation, the generation of a test environment for a module fails, Genesis alters the register/operation alloation, or adds a new onnetion from this module to a primary input or output. Unlike previously mentioned, Genesis takes into aount the relation between the harateristis of operations present in the data path and testability. But the sope of this method is limited to data paths ontaining only arithmeti or logi operators with a "neutral" element. Some property transformations annot be set for a onstant multiplier, for instane. In [0], variables are lassified as ompletely ontrollable or non-ompletely ontrollable and ompletely observable or non-ompletely observable. This lassifiation takes into aount testability harateristis of the operations. But testability problems are solved by means of modifiations at the behavioral desription, that leads to the insertion in the data path of additional hardware providing easy aess to hard-to-test nodes. It must be notied that in this approah, testability harateristis of the nodes are derived from an analysis based only on the paths exerised during the system flow. Our method gets rid of the limitations quoted above. It relies on normalized ontrollability and observability measures for all the nodes in the DFG model. These measures take into aount testability problems indued by loops, data orrelation, fault masking and lak of transpareny dereasing the possibilities of test data propagation through any kinds of operators. Register alloation/binding proess is guided by these measures in order to solve as many testability problems as possible without using ostly low-level DFT tehniques. The rest of this paper is organized as follows: next setion presents an overview of the testability analysis method that we use to guide register alloation/binding task. Setion 3 details the register alloation/binding algorithm. Experiments are presented in setion 4, and finally, setion 5 onludes the paper. 2 Testability Analysis The proposed register alloation method is based on the testability analysis presented in []. This analysis assoiates ontrollability and observability measures to all nodes of a DFG. The DFG is a desription of the data path whose nodes are behavioral and/or strutural elements. Thus, in this paper we all DFG any desription level of the data path. The ontrollability measure of a node represents the proportion of patterns that an be justified from this node to the primary inputs. The observability measure represents the proportion of pairs of values at a node that an still be distinguished after propagation to the primary outputs. To alulate these measures, transpareny oeffiients are assoiated to eah module. At the first phases of the HLS, a module may be a variable or an operation, whereas at the last phases it may be a register, an adder, a multiplexer et. The transpareny oeffiients range from 0 to. They represent the easiness of propagating test data through the modules. For instane, the transpareny oeffiient for ontrollability of a one-position shifter whose less signifiant bit is always set to zero is equal to 0.5, beause at its output the maximum number of possible different patterns is the half of the total number of patterns that an be represented. Identified testability problems are due to the presene of modules with low transpareny oeffiients, the presene of losed loops, the possibility of fault masking during test data propagation and the existene of orrelation between test patterns []. At the end of the analysis, every node exhibits a ontrollability value and an observability value. We define the loal testability measure of a node (loal (n)) as the sum of these two values. We also define a global testability measure for the iruit (global()) as the average of the loal testability measures. At the initialization phase of the testability analysis, ontrollability (resp. observability) measures of the primary inputs (resp. outputs) are set to. All the remaining measures are set to 0. Then, all the data transfers issued from the DFG are sanned. Eah time a data transfer is visited, the testability measures of the onerned nodes are updated: the ontrollability measure of the destination node is alulated based on the ontrollability measures of the origin nodes and on the transpareny oeffiients of the rossed module. This sanning is applied iteratively, until stabilization of the measures. Observability measures are omputed in a similar way. It must be notied that it may be neessary to san the list of data transfers a great number of times until omplete stabilization of the testability measures. 3 Register Alloation The proposed register alloation for testability method is part of the HLS system Mah developed at LIRMM [2] and initially devoted to synthesize iruits under area and delay onstraints. a a e d (a) b {d,e} During register alloation, all variables issued from the behavioral desription are mapped onto a set of registers. The goal of this proess is to find a minimum number of registers allowing to store all variables while minimizing the ost of the final struture. Two or more variables an be stored in the same register if their lifetimes are disjoint (ompatible variables). In Mah, the register alloation proess starts from the ompatibility graph of variables. In this graph, an edge onnets eah pair of ompatible variables. A solution to the register alloation problem is a partition of this graph in liques (ompletely onneted sub-graphs). It is well known that finding the optimal (b) Figure : (a) Compatibility graph, (b) Graph updated after merging b

3 (versus any riterion) lique partitioning is a NP-omplete problem. Thus, in order to arry out register alloation in an aeptable amount of time, we have hosen a heuristi, namely hill limbing. Aording to this heuristi, a weight based on area and testability estimations, is assoiated to eah edge. The two variables orresponding to the edge with the highest weight are merged together into the same register. The struture of the graph is then updated and the weights are realulated for remaining edges. This proess is repeated until no more edges exist. Figure (a) shows an arbitrary ompatibility graph with five variables. Figure(b) shows the graph updated after the merging of variables d and e. Note that the edge between a and e has been deleted due to a and d inompatibility. The weight W(i,j) assoiated to eah edge (i,j) is based on area and testability estimations: W(i,j) = α. area (i,j) + β. testability (i,j) () where α and β are user provided tuning fators. These estimations allow to predit the effet of the urrent merging on the final iruit harateristis. The area estimation, area(i,j), takes into aount the redution in the number of onnetions and the redution in the number of multiplexer inputs due to the urrent merging [3]. The testability estimation is based on three fators: global urrent (), global after (i,j) and lookh(i,j). The term global urrent () is the global testability measure of the urrent design. The term global after (i,j) is the global testability measure of the iruit if variables i and j merge into the same register. Finally, lookh(i,j) is a look-ahead term alulated as follows: global after ( id,jd) id,jd deleted_ed ges lookh(i, j) = (2) # deleted_ed ges where #deleted_edges is the number of edges deleted from the ompatibility graph if i and j merge into the same register, and (id,jd) are the ouples of nodes orresponding to the deleted edges. Therefore, lookh(i,j) has a low value when many other good mergings beome impossible, it has a high value when the urrent merging does not prevent other good merging. The testability estimation is done aording to formula (3) in whih oeffiients γ and δ are user provided tuning fators. testability(i,j) = γ. ( global after (i,j) - global urrent () ) + δ.lookh(i,j) (3) As an example, Figure 2(a) shows a part of a DFG with two primary inputs p and p 2, three variables a, b and, two adders and one shifter. For illustration purpose, only ontrollability measures are showed. In this example, a is easy to ontrol, beause it is onneted to the output of an adder (with a ontrollability transpareny oeffiient equal to ), whih in turn, is diretly onneted to primary inputs. Variable b is diffiult to ontrol, beause it is only onneted to the output of a shifter (with a ontrollability transpareny oeffiient equal to 0.5). If a is ompatible with b, these variables an be merged. Figure 2(b) shows that the resultant register is easy to ontrol, beause it inherits the onnetions from a. As a onsequene, (a) (b) p p2 = = = adder shifter = =0.5 p adder = p2 = = shifter = a b =0.5 {a,b} adder2 =0.5 adder2 and variable also beome more ontrollable. It must be mentioned that the testability analysis an be time onsuming and that the omputation of global after (dp, i, j) needs to simulate the merging of i and j, and to reapply the testability analysis proess on the resulting data path. As a onsequene, the register alloation algorithm as presented above an be very time onsuming due to numerous Testability Analysis Runs (TAR) involved. As example, for an initial ompatibility graph with 300 edges, 300 TAR are required for hoosing the first best merging. After this merging, the graph is updated. Let assume that the number of remaining edges is 295. To hoose the seond merging, 295 TAR are required. The proess iterates until no edge remains. Thus, in this example, the total number of TAR would be Assuming that the number of edges eliminated after eah merging is a onstant p, and that A is the initial number of edges, it omes that the total number of TAR is approximately A 2 /2p. In the example above, the number of TAR would be To overome this drawbak, we deide to pre-selet a subset of edges as andidates for merging. The preseletion is done aording to a loal testability improvement estimation. The pre-seletion weight assoiated to eah edge is: pw(i,j)= ontrollability(i) - ontrollability(j) + observability(i) - observability(j) (4) The pre-seleted edges subset is formed by the n edges with the highest pw(i,j), where n is an user provided parameter. The omputation of the pw weights is straightforward and does not require extra testability analysis. The funtion testability(i,j) is then only omputed for n preseleted edges, and testability(i,j) = 0 for the other ones. Doing so, the number of TAR equals to n.a/p (vs A 2 /2p). The main differene between the two metris pw(i,j) = adder2 Figure 2: (a) DFG and assoiated ontrollability measures, (b) DFG updated after merging = = = =

4 b (, 0.5) (, 0.5) and testability(i,j) is that pw is only an estimate of the loal testability gain resulting from the merge of i and j. It does not quantify the testability hanges on other nodes. Figure 3(a) shows a part of a DFG where testability measures are indiated as pairs (ontrollability, observability). In the orresponding ompatibility graph pw(a,b) =. However, if a and b are merged, the resulting register has a very good ontrollability but a very poor observability due to the reonvergent fanout on the adder (see Figure 3(b)). Only the global metri testability(a,b), based on the analysis of the data transfers, allows to predit this low observability. In fat, the testability analysis heks this kind of testability bottlenek and returns a very low observability measure (<< 0.) for the resulting register. Consequently, the omputation of testability (i,j) is still neessary on pre-seleted edges To present the register alloation algorithm (Figure 4), we define the following parameters:. A is the set of edges in the ompatibility graph,. a i, j is the edge onneting variables i and j,. W i, j is the weight resulting from W(i, j) (),. area i,j is the area estimation resulting from area(i,j),. n is the number of pre-seleted edges,. pw i,j is the pre-seletion weight assoiated to the edge a i, j and resulting from pw (i, j) (4),. the funtion pre-seleted(a i, j, n) returns true if a i, j belongs to the subset onstituted by the n edges with highest pre-seletion weights,. testability i, j is the simulated weight resulting from testability(i, j) (3),. MaxW( ) returns the edge with the highest W i, j,. UpdateDFG( ) updates the DFG after variables merging and UpdateCompatGraph( ) updates the orresponding ompatibility graph. 4 Results {a, b} (, << 0.) (, ) 2 adder d (, 0.5) multiplier 2 multiplier a (0.5, ) d (, ) Figure 3: (a) A part of a DFG, (b) DFG updated after merging In this setion, we first present the designs on whih experiments have been done. Then we ompare the harateristis of the strutural implementations obtained from ) lassial HLS flow, and 2) proposed HLS for Testability methodology. Finally, we ompare the 2 2 adder output (a) output (b) while A { TestabilityAnalysis(DFG); for all a i, j { pw i, j = pw (i, j); area i, j = area (i, j);} for all a i, j { if pre-seleted (a i, j, n) then testability i, j = testability (i, j); else testability i, j = 0; W i, j = W(i, j); } Merge (MaxW ( ) ); UpdateDFG ( ); UpdateCompatGraph ( ); } Figure 4: Algorithm for register alloation proposed strategy with a gate level DFT tehnique. 4. Design examples We first applied the presented algorithm on lassial design examples: the differential equation example (difeq) from [4], the elliptial wave filter (ewfil) from [5] and the Tseng s example (tseng) from [6]. The only testability bottleneks enountered in these High Level Synthesis benhmarks are loops whih are well known to have an impat on ATPG proess omplexity. It is diffiult to ompare our results with those presented in the literature [9] [0] [6] [7] [8] in terms of fault overage or in terms of test generation run time beause of the use of different ATPG tools. Our experiments show that, for these benhmarks, the lassial register alloation/binding proess generates easily testable strutures though only area onstraints are taken into aount. Nevertheless, we applied our method to these benhmarks and heked that designs synthesized under testability onstraints are atually more testable than those obtained without regard to testability. More interestingly, we modified these benhmarks in order to introdue other testability bottleneks than loops, for instane, FU transpareny related problems and reonvergent fanouts. We also defined several behavioral desriptions in order to explore various onfigurations. Experimental data obtained from modified benhmarks (difeq_, ewfil_, tseng_) and from our examples (x_, y_, z_) [7] are summarized in Table. 4.2 Classial HLS vs HLS for Testability For eah behavioral desription, example_n represents the design synthesized without testability onsiderations (β=0 in expression (), only area ost is taken into aount), while example_x (p) represents the design synthesized under testability onstraints (x is the number of edges pre-seleted at eah iteration of the register alloation/binding proess, p is the orresponding perentage of pre-seleted edges over all edges in the initial ompatibility graph). Several instanes example_x (p) were generated for eah behavioral desription by using various perentage p. Only one instane is presented in the table, this is the one for whih the best testability measures are ahieved, the results not being improved by pre-seleting more edges. The RTL desription of eah iruit is obtained from

5 Mah (High Level Synthesis run time is reported in Table, olumn CPU time-hls). Then, designs are expanded to gate-level and the ATPG tool from an industrial suite is applied on these lower level desriptions. Fault overage (FC), test effiieny (TE), test time, ATPG CPU time, total number of faults (# f), number of testable faults (# tf), number of non-deteted faults (# nd) and number of non-testable faults (# nt) are also reported in Table. Area overheads resulting from the proposed register alloation/binding proess are reported in the last olumn for eah example_x (p), these measures are obtained using an industrial tool after layout generation using a µm tehnology (area orresponding to the I/O ports is not onsidered). Conerning the pre-seletion proess: it is introdued to save CPU time and, as expeted, synthesis time dereases with the number of pre-seleted edges. Note that the pre-seletion proess does not neessarily impat the results quality. For example, ewfil_50 (2) is synthesized in 32mn8s by performing testability evaluation on only 2% of the possible merging at eah iteration, while the design synthesized without pre-seletion (ewfil_all (00), not shown on the table) needs 2h23 of HLS CPU time and does not lead to a better fault overage. The probability of finding the best variables merging during one iteration obviously inreases with the number of pre-seleted edges. Nevertheless, better results may be obtained by preseleting a given perentage of edges than without preseletion (all edges being taken into aount at eah iteration). The ause of these "unexpeted" results is the greedy nature of the register alloation algorithm. As a matter of fat, even if at eah iteration the best possible merging is done (loal optimum), it is possible that the final solution is not the optimal one (global optimum). The look-ahead term in expression (3) is used to smooth this effet, but it is limited in the sense that it looks only at the next iteration. Experiments show that good results are obtained using a pre-seletion ratio lower than 5 perent and giving more importane to the testability gain resulting from one merging than to the loss of possible merging during next iteration: γ = 20 and δ = in expression (3). The main fat to notie from Table is that for all iruits, the design example_x (p) is muh more testable than the orresponding design example_n (see olumns FC, TE, ATPG CPU time, # nd, # nt). Moreover, experiments show that using testability onsiderations during synthesis does not neessarily lead to area penalties (see olumn Area Over. for difeq_, ewfil_, z_ examples). As expeted, it exists several strutural design solutions orresponding to one behavioral desription, these solutions are not neessarily equivalent with respet to testability but are equivalent with respet to area. That is why guiding the register alloation/binding proess using simultaneously area and testability onstraints is important. Here, the trade-off area/testability is tuned using α = and β = 20 in expression (). 4.3 HLS for Testability versus gate level DFT In order to ompare the proposed HLS for testability method with lower level DFT tehniques, we have generated a partial san version for every example_n design using an industrial gate-level san hain identifiation tool. Charateristis of these new designs are reported in Table on lines example_n_s (y%). The term y% is the perentage of flip-flops inserted in the san hain in order to ahieve the fault overage of example_x (p). Note that for three examples (difeq_, y_, z_), even the full san methodology applied on the design synthesized under area onstraint only does not allow to reah the same fault overage than the HLS for testability method. The neessary omputation time to establish the san hain is reported in the third olumn (CPU time-dft) for eah example_n_s. The san hain identifiation is based on ATPG results: the test pattern generation proess is first run on the full san implementation (example_n_ns(00%)). If the reahed fault overage is satisfatory, a seond run is performed on the implementation where only 50% of the flip-flops are inserted in the san hain (example_n_s(50%)). The proess is then iterated in a dihotomi manner until obtaining the minimum san hain allowing to reah the fault overage target. The neessary omputation time is approximately equal to the sum of the ATPG run times. This time plus the synthesis time reported in the seond olumn (CPU time-hls) for eah example_n are to be ompared with the omputation time of the HLS for testability proess (CPU time-hls for eah example_x (p)). Obviously, when the full san hain does not allow to reah the fault overage goal, the CPU time orresponding to the low level DFT tehnique is very low sine only one ATPG run is performed on the full san implementation (see examples difeq_, y_ and z_). Otherwise, the omputation time orresponding to the methodology HLS plus gate level DFT (T-DFT) and the omputation time orresponding to the HLS for testability methodology (T-SFT) mainly depend on the example: T- DFT < T-SFT for ewfil_, T-DFT T-SFT for tseng_ and T-DFT > T-SFT for x_. Finally, note that the test time is muh more shorter with the proposed methodology than with the partial san approah see 6 th olumn-. This is mainly due to the neessary shift operations in the san sheme. In the same way, the area overhead is generally muh smaller -2 th olumn- (lets reall that san-in/san-out pins area overhead is not onsidered in the presented results). 5 Conlusion Register alloation offers many possibilities for obtaining various design solutions, eah of them having different harateristis. This proess an be thus advantageously guided to generate highly testable data paths, eliminating the need of using lower level DFT tehniques suh as a san path. In a data path, testability problems are due to several different auses: loops, lak of transpareny through funtional units, data orrelation and fault masking. Unlike previous works, the present one takes into aount all of these problems simultaneously. To ahieve this, the register alloation/binding proess is guided by numerial testability measures, but this algorithm is general in the sense that it may be guided by any other numerial measures. Finally, note that the freedom offered during register

6 alloation/binding may be insuffiient to ahieve required fault overage (for instane, 85.36% may not be suffiient of example difeq_). In this ase, another tehnique suh as partial san must be applied in a seond step to inrease testability to the desired level. However appliation of the presented algorithm is still justifiable sine it dereases the number of testability problems in the final struture and also dereases the ost of using omplementary tehniques. Aknowledgment Authors would like to thank Laurent Volpe for his assistane with the ATPG ativity 6 Referenes [] K.D.Wagner, S.Dey "High-Level Synthesis for Testability: a Survey and Perspetive", Pro. DAC, pp.3-36, 996 [2] L.J.Avra, E.J.MCluskey "High-Level Synthesis of Testable Designs: an Overview of University Systems", Test Synthesis Seminar, Digest of Papers, International Test Conferene, pp.- 8, 994 [3] H.Harmanani, C.Papahristou "An Improved Method for RTL Synthesis with Testability Tradeoffs", Pro. ICCAD, pp , 993 [4] L.J.Avra, E.J.MCluskey "Synthesizing for San Dependene in Built-in Self-Testable Designs", Pro. ITC, pp , 993 [5] I.Harris, A.Orailoglu "Miroarhitetural Synthesis of VLSI Designs with High Test Conurreny", Pro. DAC, pp.206-2, 994 [6] T.C.Lee, W.H.Wolf, N.K.Jha, J.M.Aken "Behavioral Synthesis for Easy Testability in Data Path Alloation", Pro. ICCAD pp.66-69, 992 [7] T.C.Lee, N.K.Jha, W.H.Wolf "Behavioral Synthesis of Highly Testable Data Paths under the Non-San and Partial San Environments", Pro. DAC, pp , 993 [8] M.Potkonjak, S.Dey, R.K.Roy "Behavioral Synthesis of Area-Effiient Testable Designs Using Interation Between Hardware Sharing and Partial San", IEEE Trans. on Computer- Aided Design of Integrated Ciruits and Systems, september 995, vol.4, No 9, pp.4-53 [9] S.Bhatia, N.K.Jha "Genesis: a Behavioral Synthesis System for Hierarhial Testability", Pro. European Design and Test Conferene, pp , 994 [0] C.H.Chen, T.Karnik, D.G.Saab "Strutural and Behavioral Synthesis for Testability Tehniques", IEEE Trans. on Computer-Aided Design of Integrated Ciruits and Systems, vol.3, No 6, pp , June 994 [] M.L.Flottes, R.Pires, B.Rouzeyre "Analyzing Testability from Behavioral to RT Level", Pro. European Design and Test Conferene, pp.58-65, 997 [2] B.Rouzeyre, D.Dupont, G.Sagnes "Component Seletion, Sheduling and Control Shemes for High-Level Synthesis", Pro. European Design and Test Conferene, pp , 994 [3] B.Rouzeyre, G.Sagnes "A New Method for the Minimization of Memory Related Area", Pro. EURO-ASIC, pp.84-89, 99 [4] P.G.Paulin, J.P.Knight "Sheduling and Binding Algorithm for High-Level Synthesis", Pro. DAC, pp.-6, 989 [5] P.Dewilde, E.Deprettere, R.Nouta "Parallel and Pipelined VLSI Implementation of Signal Proessing Algorithms", in VLSI and Modern Signal Proessing, S.Y.Kung, H.J.Whitehouse - T.Kailath Editors. Prentie Hall. pp , 985. [6] C.J.Tseng, D.Siewiorek "Automated Synthesis of Data Paths in Digital Systems", IEEE Trans. on CAD, vol.5, No.3, July 986 [7] Sheduled data flow graphs available at ~rouzeyre/alloreg.ps. Table : Experimental results Ciruit CPU time Test time ATPG Area FC TE # f # tf # nd # nt HLS DFT (# lk) CPU time Over (%) difeq_n 7s s difeq_ (5.9) 8s s difeq_n_s (00%) - 4s s ,7 ewfil_n 44s >3h ewfil_50 (2) 32mn8s s ewfil_n_s (75%) s s tseng_n 4s s tseng_ (6.7) 26s s tseng_n_s (3%) s s x_n 33s s x_0 (7.) 3mns s x_n_s (2%) - >6h >6h y_n 33s >6h y_30 (5) 5mn5s s y_n_s (00%) - 8.8s s z_n mns >24h z_0 (5.) 4mn3s s z_n_s (00%) - 5s s