Implementing Load-Balanced Switches With Fat-Tree Networks

Size: px
Start display at page:

Download "Implementing Load-Balanced Switches With Fat-Tree Networks"

Transcription

1 Implementing Load-Balaned Swithes With Fat-Tree Networks Hung-Shih Chueh, Ching-Min Lien, Cheng-Shang Chang, Jay Cheng, and Duan-Shin Lee Department of Eletrial Engineering & Institute of Communiations Engineering National Tsing Hua University, Hsinhu, Taiwan, R.O.C. Abstrat Load-balaned swithes have reeived a lot of attention lately as they are muh more salable than other existing swith arhitetures in the literature. One of the most salient features of load-balaned swithes is the simpliity of implementing deterministi and periodi onnetion patterns for its swith fabris. In this paper, we propose to use fat-tree networks as the swith fabris in load balaned swithes. Fat-tree networks have been widely used for interonneting omputers in data enters and for other appliations in Network-on-Chip (NoC). One of the main problems in fat-tree networks is that the link apaity has to be inreased rapidly from the leaves to the root of the tree. This poses a serious salability problem as the omplexity of implementing the swithes near the root of the tree ould be very high, espeially when a fat-free network is required to be nonbloking. As we only require an N N fat-tree network to realize a set of N permutations needed for the implementation of N N load-balaned swithes, in this paper we show that the implementation omplexity an be greatly redued. For this, we first derive a lower bound on the link apaity for eah swith in a fat-tree network. By using the uniform mapping property of the bit-reversal permutation, we show that there exists a set of N permutations that ahieves the lower bound. To further redue the implementation omplexity, we propose a fully meshed fattree network that replaes the upper half of the tree by a simple mesh. We then show a fully meshed fat-tree network an be implemented by folding a banyan-type network that realizes this set of N permutations. I. INTRODUCTION Load-balaned swithes [] [] have reeived a lot of attention reently as they are muh more salable than other existing swith arhitetures in the literature. In Figure, we show a typial two-stage load-balaned swith: the first stage is for load-balaning that onverts inoming traffi into the uniform traffi, and the seond stage is for swithing of the uniform traffi. It was shown in [] that load-balaned swithes ahieve % throughput and have delay performane omparable to ideal output-buffered swithes (when the traffi is heavy and bursty). In this paper, we onsider the disrete-time setting and assume that time is slotted and synhronized so that a fixedsize paket an be transmitted over a link within a time slot. One of the most salient features of load-balaned swithes is that the onnetion patterns for the swith fabris in both stages in Figure are deterministi and periodi. As suh, N Fig.. Load-balaning Swithing The generi two-stage load-balaned swith. there is no need to find mathings as required in most inputbuffered swithes, and there are no omputational overheads in load-balaned swithes. Speifially, for an N N loadbalaned swith, the swith fabris in both stages in Figure only need to realize in every period of N time slots any N N N permutation matries P, P,..., P N that satisfy P + P + + P N = e, () where e is the N N matrix with all its elements being. Clearly, there are many possible hoies of the N permutation matries P, P,..., P N for implementing N N loadbalaned swithes. In the literature, there are two well-known onditionally nonbloking swithes, i.e., rotators (whih realize all of the powers of the irular shift matrix) and symmetri TDM swithes [] [], that an be used for realizing the needed onnetion patterns for the swith fabris in load balaned swithes. In [] and [], respetively, it was shown that twister networks (whih are speial types of multistage interonnetion networks) and degenerate banyan networks (whih only use half of the inputs/outputs in the lassial banyan networks) an be used as rotators and symmetri TDM swithes, and hene they an be used as the swith fabris in load balaned swithes. In this paper, we propose to use fat-tree networks [] as the swith fabris in load balaned swithes. Fat-tree networks (and many variants of them) are ommonly used for the onstrutions of data enter interonnetion networks []. They have also been widely deployed in Network-on-Chip (NoC) []. As suggested by its name, a fat-tree network is a swithing network onstruted from a omplete binary tree, N

2 where eah leaf is an input/ouput port and eah non-leaf node is a swith. To aommodate the traffi multiplexed into the tree, the link apaity of a swith has to be inreased rapidly from the leaves to the root of the tree (this is why it is alled a fat-tree network). In partiular, if a fat-tree network with N input/output ports is required to be nonbloking, i.e., the fatfree network an realize all of the N! permutations between its input and output ports, then eah node has to be a nonbloking swith and the link apaity of a swith has to be inreased exponentially from the bottom to the top of the tree. This poses a serious salability issue in designing the swithes near the root of the tree when N is very large. Fortunately, as our purpose in this paper is to use fat-tree networks as the swith fabris in load balaned swithes, we only require a fat-tree network with N input/output ports to realize N permutation matries P, P,..., P N that satisfy the ondition in () in every period of N time slots. We will show that the salability problem in a nonbloking fat-tree network an be solved in this senario by appropriate hoies of the N permutation matries P, P,..., P N and by replaing the upper half of the fat-tree network by a simple mesh. In this paper, we first show a lower bound on the link apaity for eah swith in a fat-tree network that is apable of realizing any N permutation matries P, P,..., P N satisfying the ondition in (). The lower bound is derived based on averaging the traffi flows that need to go through a swith in the fat-tree network. Unfortunately, both rotators and symmetri TDM swithes require link apaities that are substantially higher than those given by the lower bound. Then we propose new permutation matries P, P,..., P N that not only satisfy the ondition in () but also ahieve the lower bound, i.e., they an be realized by a fat-tree network with link apaities speified by the lower bound. The idea is based on the bit-reversal permutation previously proposed in []. One key property of the bit-reversal permutation is the uniform mapping property that maps the inputs in a subtree uniformly to the outputs in other subtrees. We show that any permutation that has the uniform mapping property an be realized by a fat-tree network with link apaities speified by the lower bound. We also show that the bitreversal permutation and its variants obtained by irular shifts all have the uniform mapping property, and hene they an be realized by a fat-tree network with link apaities speified by the lower bound. To further redue the implementation omplexity, we propose a fully meshed fat-tree network by replaing the upper half of a fat-tree network by a simple mesh. As suh, there is no need to implement the swithes in the upper half of the usual fat-tree network, and hene we do not have the salability problem for the swithes near the root in the usual nonbloking fat-tree network. We show that any permutation that has the uniform mapping property an also be realized by a fully meshed fat-tree network. To implement the swithes in a fully meshed fat-tree network, i.e., in the lower half of a fat-tree network, we onsider a speifi banyan-type network. Suh a banyan-type network is onstruted by onneting a olletion of reversed baseline networks (with a muh smaller size) and another olletion of baseline networks (with a muh smaller size). We show that a permutation an be realized by suh a banyantype network if and only if the permutation has the uniform mapping property. By folding suh a banyan-type network, we are able to map suh a folded banyan-type network to the orresponding fully meshed fat-tree network with the same number of input/output ports. We further show that eah swith in the orresponding fully meshed fat-tree network an be onstruted by a olletion of swithes in the folded banyan-type network. As any banyan-type network possesses the self-routing property, the orresponding fully meshed fattree network also inherits suh a self-routing property. This solves both the swith implementation problem and the routing problem in a fully meshed fat-tree network. This rest of this report is organized as follows. In Setion II, we introdue fat-tree networks and show a lower bound on the link apaity for eah swith in a fat-tree network that an realize the permutations needed for load-balaned swithes. In Setion III, we introdue the bit-reversal permutation and show that any permutation that has the uniform mapping property, inluding the bit-reversal permutation and its variants obtained by irular shifts, an be realized by a fat-tree network with the link apaities speified by the lower bound. We then propose fully meshed fat-tree networks in Setion IV and show that a fully meshed fat-tree network an be implemented by folding a speifi banyan-type network. We also show that any permutation that has the uniform mapping property an be realized by a fully meshed fat-tree network with the link apaities speified by the lower bound. Finally, the report is onluded in Setion VI, where we address possible extensions of our work. II. FAT-TREE NETWORKS A fat-tree network, first proposed in [], is a swithing network onstruted from a omplete binary tree. To explain how a fat-tree network works, we first onsider a omplete binary tree with n leaves, indexed from to n (see Figure for a omplete binary tree with leaves). In suh a omplete binary tree, there are n + levels, indexed from to n. The root is the only node at level and a node is at level j+ if it is a hild of a node at level j for j n. Index the root as node (, ), and reursively index the two hildren of node (j, k) as node (j +, k) and node (j +, k + ) for j n and k j. Clearly, there are j nodes at level j and in this report we also all node (j, k) as the k th node at level j for j n and k j. Note that the n leaves are nodes (n, ), (n, ),..., (n, n ), and we also all node (n, x) as leaf x for x n in this report. For j n and k j, let T (j, k) be the subtree rooted at node (j, k), and let S(j, k) be the set of all of the leaves in the subtree T (j, k), namely, S(j, k) = {x : k n j x (k + ) n j } ()

3 Fig.. A omplete binary tree with leaves. Note that the total number of leaves in the subtree T (j, k) is S(j, k) = n j. For example, for the omplete binary tree with leaves in Figure, we have S(, ) = {, }, S(, ) = {, }, and S(, ) = S(, ) S(, ) = {,,, }. For x n, let the n-tuple (I n (x), I n (x),..., I (x)) be the binary representation of x, i.e., x = n m= I m(x) m, where I m (x) is the (n m+) th most signifiant bit of x for m n. Then the set S(j, k) an be alternatively expressed as S(j, k) = {x : x n, and I n j+m (x) = I m (k) for m j}. () In other words, S(j, k) ontains all of the leaves of whih the first j most signifiant bits are the same as the last j most signifiant bits of k (note that the first n j most signifiant bits of k are ). Fig.. Level A nonbloking fat-tree network with input/output ports. Now we show how one onstruts a n n nonbloking fat-tree network (with n input/output ports) by using the omplete binary tree with n leaves. For this, we view every leaf of the tree as both an input port and an output port of a n n swithing network and view every non-leaf node in the tree as a nonbloking swith (see Figure for a nonbloking fat-tree network with input/ouptut ports). For j n and k j, let the upward apaity C u (j, k) of node (j, k) be the number of parallel links from node (j, k) to its parent. For j n and k j, let the downward apaity C d (j, k) of node (j, k) be the number of parallel links from node (j, k) to its two hildren. In this report, we assume that the downward apaity of a node is evenly split between its two hildren. For suh a n n fat-tree network to be nonbloking, it has to realize all of the ( n )! n n permutations between its input and output ports. In other words, for eah n n permutation there is a non-onfliting path for every pair of input/output ports speified by the permutation. Clearly, this requires that the upward apaity and downward apaity of a node in the tree must not be less than the total number of leaves in the subtree rooted at this node. As the total number of leaves in the subtree T (j, k) is S(j, k) = n j for j n and k j, we have C u (j, k) n j, j n, k j, () C d (j, k) n j, j n, k j. () Conversely, if the upward apaities and the downward apaities of the nodes in a fat-tree network satisfy the onditions in () and (), respetively, then there is always a non-onfliting path from an input to the root and there is always a nononfliting path from the root to an output, and it follows that the fat-tree network is nonbloking. Therefore, the onditions in () and () are the neessary and suffiient onditions for a fat-tree network to be nonbloking. In this report, we define a n n nonbloking fat-tree network to be the fat-tree network with C u (j, k) = n j for j n and k j, and C d (j, k) = n j for j n and k j. Note that the link apaity of a swith in a nonbloking fattree network grows exponentially from the leaves to the root, and this poses a serious salability problem in designing the swithes near the root. As mentioned in Setion I, our purpose in this report is to use fat-tree networks as the swith fabris in load balaned swithes, and hene we only require a n n fat-tree network to realize n permutation matries P, P,..., P n that satisfy the ondition in () in every period of n time slots. As suh, it seems that the upward apaities and the downward apaities of the nodes in suh a fat-tree network ould be greatly redued. In the following theorem, we first show lower bounds for the upward apaities and the downward apaities of the nodes in suh a fat-tree network. Theorem Suppose that a n n fat-tree network is apable of realizing n permutation matries P, P,..., P n that satisfy the ondition in () in every period of n time slots. Then for eah k j, we have C u (j, k) n j n j { n j n j, if j n/, = n j, if n/ + j n, C d (j, k) n j n j { n j n j, if j n/, = n j, if n/ j n. Proof. Consider node (j, k), where j n and k j. Our idea for the proof of () and () is by averaging. Consider a frame of n time slots, indexed from to n, alled the tagged frame. Assume that there is always a paket () ()

4 at every input port in every time slot and assume that fat-tree network realizes permutation matrix P i in the i th time slot for i =,,..., n. Sine the sum of the n permutation matries P, P,..., P n is a n n matrix with all its elements being, there is exatly one paket transmitted from every input to every output in the tagged frame. For j n, every leaf in the subtree T (j, k) sends a paket to every leaf that is not in the subtree T (j, k) in the tagged frame, and eah of these pakets has to go through an upward link of node (j, k). As there are n j leaves in the subtree T (j, k) and there are n n j leaves that are not in the subtree T (j, k), the total number of pakets that have to go through the upward links of node (j, k) in the tagged frame is n j ( n n j ). On the average, there are n j n j pakets that need to go through the upward links of node (j, k) per time slot. Clearly, the upward apaity C u (j, k) of node (j, k) is not less than the maximum number of pakets that need to go through its upward links in a time slot, and hene is also not less than the average number of pakets that need to go through its upward links per time slot. Therefore, it follows that C u (j, k) n j n j for j n, whih is the desired result in (). For j n, every leaf that is not in the subtree T (j +, k) (resp., subtree T (j +, k + )) sends a paket to every leaf in the subtree T (j +, k) (resp., subtree T (j +, k + )) in the tagged frame, and eah of these pakets has to go through a downward link of node (j, k) that is direted to node (j +, k) (resp., node (j +, k + )). On the average, there are n j n j pakets that need to go through the downward links of node (j, k) per time slot that are direted to node (j +, k) (resp., node (j +, k + )). As we assume that the downward apaity of a node is evenly split between its two hildren, we then see that C d (j, k) n j n j for j n, whih is the desired result in (). Observe that lower bounds for the upward apaities and the downward apaities in () and () are the same as those of nonbloking fat-tree networks in () and () for the lower half of the tree, but are smaller for the upper half of the tree. As the salability problem is mainly due to the design of the swithes in the upper half of the tree, it is of highly importane and interest to see if there exist n permutation matries P, P,..., P n that satisfy the ondition in () and ahieve the lower bounds in () and (). It an be seen that the n permutation matries realized by rotators and symmetri TDM swithes do not ahieve the lower bounds in () and (). In the next setion, we will find n permutation matries P, P,..., P n that satisfy the ondition in () and ahieve the lower bounds in () and (). III. BIT-REVERSAL PERMUTATION In the previous setion, we derive lower bounds for the upward apaities and the downward apaities of a fat-tree network to realize the needed permutations for a load-balaned swith. In this setion, we will show that these lower bounds are indeed ahievable by using the bit-reverse permutation introdued in [] and its variants obtained by irular shifts. We first introdue some notations that will be used for desribing the bit-reversal permutation. Let Z N = {,,..., N }. For a permutation σ on Z N, we denote P σ as the N N permutation matrix orresponding to σ. For a set S Z N, let σ(s) be the range of S under σ, i.e., σ(s) = {σ(x) : x S}. Let σ be the irular shift permutation on Z N, i.e., σ (x) = (x + ) mod N for all x N. Also, let σ i be the identity permutation on Z N for i = and let σ i = σ i σ for i. Clearly, σ i is the permutation that performs irular shift permutation i times for i, i.e., σ(x) i = (x + i) mod N for x N. As it is easy to see that P σ + P σ + + P σ N = e, () we have that P σ, P σ,..., P σ N satisfy the ondition in (). Furthermore, for a permutation σ on Z N, we denote σ i = σ i σ for i, i.e., σ i (x) = σ(σ(x)) i = (σ(x) + i) mod N for x N. Sine P σi = P σ i P σ for i, we see from () that P σ + P σ + + P σn = (P σ + P σ + + P σ N )P σ = ep σ = e. () Note that as σ is the identity permutation on Z N, we have σ = σ σ = σ. Therefore, it follows from () that P σ, P σ, P σ,..., P σn satisfy the ondition in (). Definition (Bit-Reversal Permutation) Let N = n and let (I n (x), I n (x),..., I (x)) be the binary representation of x Z N, where I m (x) is the (n m + ) th most signifiant bit of x for m n. The bit-reversal permutation π on Z N is the permutation suh that I m (π(x)) = I n+ m (x), for m n, () namely, π(x) = n m= I n+ m(x) m, for x N. Note that P π, P π, P π,..., P πn satisfy the ondition in (), where π i = σ i π for i N. In Figure, we show the permutations π, π,..., π on Z. The olumn marked with on the top row is π, and the olumn marked with i on the top row is π i for i. As π, π,..., π satisfy the ondition in (), the matrix in Figure is a Latin square, where every symbol in Z = {,,,..., } appears exatly one in every row and every olumn. One prominent property of the bit-reversal permutation is the uniform mapping property as defined below. Definition (Uniform Mapping Property) Let N = n. A permutation σ on Z N is said to have the uniform mapping property if σ(s(j, k)) S(n j, l) = () for all j n, k j, and l n j, where S(j, k) and S(n j, l) are given by ().

5 Fig.. The permutations π, π,..., π on Z = {,,,..., }. When a permutation σ is realized in a fat-tree network, σ(s(j, k)) is the set of outputs with their inputs in the subtree T (j, k). As there are n j leaves in the subtree T (j, k) and there are n j subtrees at level n j, the uniform mapping property implies that all of the n j leaves in the subtree T (j, k) are mapped uniformly to the n j subtrees at level n j. In the following theorem, we show that the bit-reversal permutation and its variants obtained by irular shifts all have the uniform mapping property. Theorem Let N = n. The permutations π, π,..., π N all have the uniform mapping property. Proof. Sine we know that π = π, it suffies to show that π i has the uniform mapping property for i N. Let i N, j n, k j, and l n j. From (), we see that it suffies to show that π i (S(j, k)) S(n j, l) ontains exatly one element. Let x S(j, k). Then we have from I m (π(x)) = I n+ m (x) for m n in () and I n+ m (x) = I (n j)+(j+ m) (x) = I j+ m (k) for m j in () that π(x) = = = n I m (π(x)) m = m= n m=j+ n j m= n I n+ m (x) m m= I n+ m (x) m + I n+ m j (x) m+j + j I n+ m (x) m m= j I j+ m (k) m m= = q (x) j + r (j, k), () where q (x) = n j m= I n+ m j(x) m and r (j, k) = j m= I j+ m(k) m. Let r (j, k) + i = q (i, j, k) j + r (i, j, k), where q (i, j, k) and r (i, j, k), respetively, are the quotient and the remainder of r (j, k) + i divided by j. Then we have from () that (π(x) + i) mod n = (q (x) j + r (j, k) + i) mod n = ((q (x) + q (i, j, k)) j ) mod n + r (i, j, k). () Note that sine x S(j, k), we have from () that k n j x (k + ) n j. As x goes from k n j, k n j +,..., (k + ) n j, the last n j most signifiant bits (I n j (x), I n j (x),..., I (x)) goes from (,,..., ), (,,..., ),..., (,,..., ). As q (x) = n j m= I n+ m j(x) m, it then follows that {q (x) : x S(j, k)} = {,,..., n j }. () It is easy to see from () that {(q (x) + q (i, j, k)) j mod n : x S(j, k)} = {q j : q n j }. () As suh, we have from (), (), and r (i, j, k) j that π i (S(j, k)) = {π i (x) : x S(j, k)} = {(π(x) + i) mod n : x S(j, k)} = {((q (x) + q (i, j, k)) j ) mod n + r (i, j, k) : = {q j + r (i, j, k) : q n j } = {y : y n, x S(j, k)} and I m (y) = I m (r (i, j, k)) for m j}.() Furthermore, we have from () that S(n j, l) = {y : y n, and I j+m (x) = I m (l) for m n j}.() Therefore, we see from () and () that there is exatly one element in π i (S(j, k)) S(n j, l), and it is uniquely determined by the binary representation (I n j (l),..., I (l), I j (r (i, j, k)),..., I (r (i, j, k))). In the following theorem, we show that any permutation that satisfies the uniform mapping property an be realized by a fat-tree network with link apaities speified by the lower bounds in Theorem. Theorem Let N = n. Suppose that an N N fat-tree network has link apaities given by the lower bounds in () and (), i.e., the inequalities in () and () hold with equality. Then suh an N N fat-tree network an realize any permutation on Z N that satisfies the uniform mapping property. Proof. Let σ be a permutation on Z N that satisfies the uniform mapping property. To show that the permutation σ an be realized by the fat-tree network, we need to show that there is a non-onfliting path for every pair of input/output ports speified by the permutation σ. In fat, we will show that the

6 shortest paths for all of the pairs of input/output ports speified by σ are non-onfliting paths. The shortest path from an input port x to its output port σ(x) is given by first going up the tree from x to the first ommon anestor of x and σ(x), and then going down the tree to σ(x). (i) We first show that there is no onflit in the upward links of node (j, k) for j n and k j by proving that C u (j, k) is not less than the total number of shortest paths that go through its upward links. We onsider the two ases j n/ and n/ + j n separately. Case : j n/. Note that a shortest path needs to go through an upward link of node (j, k) if its input x is a leaf of the subtree T (j, k) and its output σ(x) is a leaf outside the subtree T (j, k). The set of the leaves that are outside the subtree T (j, k) an be written as k ks(j, k ). Sine in this ase we have j n/, the set of the leaves in the subtree T (j, k ) an be expressed as the union of the sets of the leaves in the subtrees T (n j, l), l = n j k, n j k +,..., n j (k + ), and hene we have S(j, k ) = n j (k +) l= n j k S(n j, l). Therefore, it follows from the uniform mapping property in () and () that the total number of shortest paths that go through the upward links of node (j, k) is given by σ(s(j, k)) ( k ks(j, k )) = σ(s(j, k)) ( k k n j (k +) l= n j k S(n j, l)) = k k n j (k +) l= n j k (σ(s(j, k)) S(n j, l)) = k k n j (k +) l= n j k σ(s(j, k)) S(n j, l) n j (k +) = k k = C u (j, k). () l= n j k = ( j ) n j Case : n/ + j n. Clearly, the total number of shortest paths that go through the upward links of node (j, k) is bounded above by S(j, k), i.e., the total number of leaves in the subtree T (j, k). As in this ase we have from () that C u (j, k) = n j = S(j, k), the proof is ompleted. (ii) Now we show that there is no onflit in the downward links of node (j, k) for j n and k j by proving that C d (j, k) is not less than the total number of shortest paths that go through its downward links. We onsider the two ases j n/ and n/ j n separately. Case : j n/. Note that a shortest path needs to go through a downward link of node (j, k) that is direted to node (j +, k) (resp., node (j +, k + )) if its input x is a leaf outside the subtree T (j +, k) (resp., subtree T (j +, k + )) and its output σ(x) is a leaf of the subtree T (j +, k) (resp., subtree T (j +, k + )). The set of the leaves that are outside the subtree T (j +, k) (resp., subtree T (j +, k + )) an be written as k ks(j +, k ) (resp., k k+s(j +, k )). Sine in this ase we have j + n/, the set of the leaves in the subtree T (j +, k ) an be expressed as the union of the sets of the leaves in the subtrees T (n j, l), l = n j k, n j k +,..., n j (k + ), and hene we have S(j +, k ) = n j (k +) l= n j k S(n j, l). As suh, it follows from the uniform mapping property in () and () that the total number of shortest paths that go through the downward links of node (j, k) that are direted to node (j +, k) (resp., node (j +, k + )) is given by σ( k ks(j +, k )) S(j +, k)) = σ( k k n j (k +) l= n j k S(n j, l)) S(j +, k)) = k k n j (k +) l= n j k σ(s(n j, l)) S(j +, k)) = k k = k k = C d(j, k). n j (k +) l= n j k σ(s(n j, l)) n j (k +) S(j +, k)) l= n j k = ( j+ ) n j Similarly, the total number of shortest paths that go through the downward links of node (j, k) that are direted to node (j+, k+)) is given by σ( k ks(j+, k )) S(j+, k+ )) = C d(j, k). Therefore, the total number of shortest paths that go through the downward links of node (j, k) is exatly C d (j, k). Case : n/ j n. Clearly, the total number of shortest paths that go through the downward links of node (j, k) is bounded above by S(j, k), i.e., the total number of leaves in the subtree T (j, k). As in this ase we have from () that C d (j, k) = n j = S(j, k), the proof is ompleted. From Theorem, Theorem, and the fat that the N permutations P π, P π, P π,..., P πn, where N = n, satisfy the ondition in (), we obtain the following theorem. Theorem Let N = n. Suppose that an N N fat-tree network has link apaities given by the lower bounds in () and (). Then suh an N N fat-tree network an realize the N permutations P π, P π, P π,..., P πn, and hene an be used as the swith fabri for an N N load-balaned swith. IV. FULLY MESHED FAT-TREE NETWORKS There is a very important observation from the proof of Theorem. Note that the total number of paths that go through the subtree T (j, k) to another subtree T (j, k ) at the same level is σ(s(j, k)) S(j, k ) under the shortest path routing for realizing a permutation σ in a fat-tree network. If σ satisfies the uniform mapping property, then it an be seen from () that this number is n j for j n/.

7 In partiular, for j = n/, we have n j = when n is even and we have n j = when n is odd. Therefore, the onstrution omplexity an be greatly redued if we simply provide diret links among the subtrees at level n/ and route pakets diretly through these links. In other word, we replae the upper half of the tree by a simple mesh, and this leads to a muh more simplified onstrution, alled a fully meshed fat-tree network. Speifially, a n n fully meshed fat-tree network is onstruted by n/ n/ n/ nonbloking fat-tree networks. There are n n/ links from eah root of a n/ n/ fat-tree network to the root of another n/ n/ fat-tree network. In Figure, we show a fully-meshed fat-tree network. To see why the n/ n/ n/ fat-tree networks in a n n fully meshed fat-tree network are nonbloking, observe that level j in the n/ n/ n/ fat-tree networks is the level j + n/ in the original n n fat-tree network with link apaities given by the lower bounds in () and (). Let C u (j, k) (resp., C d (j, k)) be the upward (resp., downward) apaity of node (j, k) in the n/ n/ n/ fat-tree networks for j n/ (resp., j n/ ) and k j. Then we have from () and () that C u (j, k) = C u (j + n/, k) = n j n/ = n/ j, for j n/, () C d (j, k) = C d (j + n/, k) = n j n/ = n/ j, for j n/. () The link apaities in () and () are exatly the same as those required for a nonbloking n/ n/ fat-tree network. Fig.. A fully meshed fat-tree network. Level By following the same argument as in the proof of Theorem, we also have the following theorem. Theorem Let N = n. Consider the N N fully meshed fat-tree network as desribed in this setion. Suh an N N fully meshed fat-tree network an realize any permutation on Z N that satisfies the uniform mapping property. In partiular, it an realize the N permutations P π, P π, P π,..., P πn, and hene an be used as the swith fabri for an N N load-balaned swith. V. IMPLEMENTATION OF THE SWITCHES IN A FULLY MESHED FAT-TREE NETWORK It is shown in the previous setion that a n n fully meshed fat-tree network is apable of realizing the needed n permutations for a n n load-balaned swith. Although the onstrution omplexity of a n n fully meshed fattree network is muh smaller than that of a n n nonbloking fat-tree network, it still needs to implement n/ n/ n/ nonbloking fat-tree networks. As eah node in these n/ n/ nonbloking fat-tree networks is itself a nonbloking swith with many input/output ports, the onstrution omplexity is still very high. To further redue the onstrution omplexity, we will show that one does not need to implement nonbloking swithes for the nodes in these n/ n/ n/ fat-tree networks. Speifially, for a node with upward apaity j and downward apaity j, it an be implemented by a olletion of j swithes. Our idea of ahieving this is folding a speifi banyan-type network. A. A Banyan-Type Network In this setion, we onsider a n n banyan-type network (see e.g., []), where n is an even number. A n n banyantype network is a multistage interonnetion network with n stages, indexed from to n. Eah stage onsists of n swithes, indexed from to n. As there are two inputs and two outputs in a swith, there are n inputs and n outputs in eah stage. For eah stage, index the upper input (resp., output) and the lower input (resp., output) of swith k as input (resp., output) k and input k +, respetively. To ompletely speify the banyan-type network onsidered in this report, we need to desribe how the n outputs from one stage are onneted to the n inputs of the next stage. For x n, let (I n (x), I n (x),..., I (x)) be the binary representation of x, where I m (x) is the (n m + ) th most signifiant bit of x for m n. For j n/, output x of the j th stage is onneted to input y of the (j +) th stage, where y has the following binary representation: (I n (y), I n (y),..., I (y)) = (I n (x), I n (x),..., I j+ (x), I j (x), I j (x),..., I (x), I j+ (x)). () In the middle of the banyan-type network, output x of the (n/) th stage is onneted to input y of the (n/ + ) th stage, where y has the following binary representation: (I n (y), I n (y),..., I (y)) = (I n/ (x), I n/ (x),..., I (x), I n (x), I n (x),..., I n/+ (x)). () Finally, for n/ + j n, output x of the j th stage is onneted to input y of the (j + ) th stage, where y has the following binary representation: (I n (y), I n (y),..., I (y)) = (I n (x), I n (x),..., I n j+ (x), I (x), I n j+ (x), I n j (x),..., I (x)). () In Figure, we show a banyan-type network with suh onnetions. Readers who are familiar with the onstrutions

8 of banyan-type networks might observe that the first n/ stages are n/ n/ n/ reversed baseline networks and the last n/ stages are n/ n/ n/ baseline networks. They are joined by a perfet shuffle in the middle. With suh an observation, we will show how one an fold this banyan-type network from the middle to onstrut a fully meshed fat-tree network in Setion V-B. Stage Fig.. A banyan-type network. It is well-known that for every input/output pair in a banyantype network, there is a unique routing path from the input to the output, and it an be used for the self-routing of a paket from the input to the output []. The unique routing path for an input/output pair is speified by setting the j th swith (in the j th stage) on the path aording to the j th most signifiant bit of the output. Speifially, onsider an input/output pair (i, o) and let u j (resp., v j ) be the input (resp., output) of the j th swith on its routing path for j n. The unique routing path for the input/output pair (i, o) is speified by starting the path from input i, i.e., u = i, and setting the j th swith on the path in suh a way that its input u j is onneted to the upper output link (resp., lower output link) if I n j+ (o) = (resp., I n j+ (o) = ) for j n, i.e., (I n (v j ), I n (v j ),..., I (v j ), I (v j )) = (I n (u j ), I n (u j ),..., I (u j ), I n j+ (o)). () In Appendix A, we show that for j n/, the binary representations of u j and v j are given as follows: (I n (u j ), I n (u j ),..., I (u j )) = (I n (i),..., I n/+ (i), I n/ (i),..., I j+ (i), I n (o), I n (o),..., I n j+ (o), I j (i)) (I n (v j ), I n (v j ),..., I (v j )) = (I n (i),..., I n/+ (i), I n/ (i),..., I j+ (i), I n (o), I n (o),..., I n j+ (o), I n j+ (o)). () Furthermore, for n/ + j n, the binary representations of u j and v j are given as follows: (I n (u j ), I n (u j ),..., I (u j )) = (I n (o), I n (o),..., I n/+ (o),..., I n j+ (o), I n (i), I n (i),..., I j+ (i), I j (i)), (I n (v j ), I n (v j ),..., I (v j )) = (I n (o), I n (o),..., I n/+ (o),..., I n j+ (o) I n (i), I n (i),..., I j+ (i), I n j+ (o)). () Therefore, we have from () (with j = n) that (I n (v n ), I n (v n ),..., I (v n )) =(I n (o), I n (o),..., I (o)), i.e., v n = o, and hene the end v n of the unique routing path is indeed output o. Theorem A permutation on Z n an be realized by the n n banyan-type network as desribed in this setion if and only if the permutation has the uniform mapping property. Proof. Let σ be a permutation on Z n. Suppose that σ has the uniform mapping property. We show that σ an be realized by the n n banyan-type network by ontradition. Assume that the routing paths for two distint input/output pairs (i, σ(i )) and (i, σ(i )), where i i, share a ommon link between stages j and j + for some j n. It follows that the two routing paths traverse the same output of a swith in the j th stage, and we have from () (in the ase that j n/) and () (in the ase that n/ + j n ) that I m (i ) = I m (i ), for j + m n, () I m (σ(i )) = I m (σ(i )), for n j + m n. () From () and (), we see that the i, i S(n j, l), where l = n j m= I j+m(i ) m. From () and (), we also see that σ(i ), σ(i ) S(j, k), where k = j m= I n j+m(σ(i )) m. It follows that {σ(i ), σ(i )} σ(s(n j, l)) S(j, k) and hene σ(s(n j, l)) S(j, k), ontraditing to σ(s(n j, l)) S(j, k) = in (). Conversely, suppose that σ an be realized by the banyantype network. To show that σ has the uniform mapping property, it suffies to show that σ(s(n j, l)) S(j, k) = for all j n, k j, and l n j. We first prove that σ(s(n j, l)) S(j, k) for all j n, k j, and l n j by ontradition. Assume that σ(s(n j, l)) S(j, k) for some j n, k j, and l n j, then there exist i i and i, i S(n j, l), suh that σ(i ), σ(i ) S(j, k). It follows from () that () and () hold. Therefore, in the ase that j n/ (resp., n/ + j n), we see from (), (), and () (resp., (), (), and ()) that the routing paths for the two distint input/output pairs (i, σ(i )) and (i, σ(i )) share a ommon link between stages j and j +, and we have reahed a ontradition. Let j n and l n j. Sine σ is a

9 permutation, we have j k= σ(s(n j, l)) S(j, k) = σ(s(n j, l)) j k= S(j, k) = σ(s(n j, l) = S(n j, l) = j. () As we have already proved that σ(s(n j, l)) S(j, k) for all k j, it is lear that () holds if and only if σ(s(n j, l)) S(j, k) = for all k j. We note that a theorem similar to Theorem was previously shown in Theorem in [] for the reverse-exhange network. Furthermore, the speifi banyan-type network in this setion an be shown to be equivalent to the baseline network and the reverse-exhange network with fixed input/output ports by using the trae and guide in Li s book []. B. Folding the Banyan-Type Network In the following, we desribe how to onstrut a n n fully meshed fat-tree network by folding the n n banyantype network speified in Setion V-A (when n is an even number). (i) For i n, the i th input and the i th output of the banyan-type network is merged as the i th leaf of the fully meshed fat-tree network. (ii) Eah link from an input port to the first stage (resp., from the last stage to an output port) and eah direted link from stage j to stage j + for j n/ (resp., n/ + j n ) in the banyan-type network is viewed as an upward link (resp., a downward link) in the fully meshed fat-tree network. (iii) For j n/ and k n j, let F j (k) (resp., F n j+ (k)) be the olletion of the swithes in the j th stage (resp., (n j + ) th stage) with indies in S(n j +, k) = {x : k j x (k + ) j } in the banyan-type network. It is easy to see that for j n/, the set of all of the n swithes in the j th stage (resp., the (n j + ) th stage) is partitioned into n j sets of swithes F j (), F j (),..., F j ( n j ) (resp., F n j+ (), F n j+ (),..., F n j+ ( n j )), eah ontaining j swithes. For j n/ and k n j, onstrut the swith at node (n j, k) of the fully meshed fat-tree network by the olletion of the j swithes in F j (k) F n j+ (k). Note that for j n/ and k n j, eah of the j swithes in F j (k) has two upward links, and hene the upward apaity of the swith at node (n j, k) is j, whih is the same as that in (). Also, for j n/ and k n j, eah of the j swithes in F n j+ (k) has two downward links, and hene the downward apaity of the swith at node (n j, k) is j, whih is the same as that in () Furthermore, it an be seen from the link onnetions in () for the first n/ stages in the banyan-type network that the two output links of eah swith in F j (k) are onneted to two different swithes in F j+ ( k/ ) for j n/ and k n j. Therefore, the upward links of the swith at node (n j, k) are all onneted to the swith at node (n j, k/ ) in the fully meshed fat-tree network for j n/ and k n j. Similarly, it an be seen from the link onnetions in () for the last n/ stages in the banyan-type network that the two output links of eah swith in F n j+ (k) are onneted to one swith in F n j+ (k) and another swith in F n j+ (k + ) for j n/ and k n j. Therefore, half of the downward links of the swith at node (n j, k) are onneted to the swith at node (n j +, k) and the other half are onneted to the swith at node (n j +, k +) in the fully meshed fat-tree network for j n/ and k n j. Finally, the link onnetions in () for the perfet shuffle in the middle of the banyan-type network guarantee that exatly one of the n/ output links of the n/ swithes in F n/ (k) is onneted to a swith in F n/+ (k ) for all k, k n/. Therefore, there is exatly one link from the swith at node (n/, k) to the swith at node (n/, k ) in the fully-meshed fat-tree network for all k, k n/ (note that this implies that there is an internal link inside the swith at node (n/, k) for k n/ ). The proof of the above laims is given in Appendix B. For example, we show in Figure the folded banyantype network. The swithes represented by solid (resp., dotted) squares are from the first (resp., seond) half of the banyan-type network. In partiular, the swith at node (, ) in the fully meshed fat-tree network ontains the swith with index in the st stage and the swith with index in the th stage of the banyan-type network. Level Fig.. Constrution of a fully meshed fat-tree network by folding the banyan-type network in Setion V-A. VI. CONCLUSION In this report, we proposed to use fat-tree networks as the swith fabris in load balaned swithes. One of the main problems in fat-tree networks is that the link apaity has to be inreased rapidly from the leaves to the root of the tree, and hene the omplexity of implementing the swithes near the root of the tree ould be very high. As we only require a fat-tree network to realize a set of N permutations needed for the implementation of N N load-balaned swithes, we showed that the implementation omplexity an be greatly redued. We first derived a lower bound on the link apaity for eah swith in a fat-tree network, and then we found a

10 set of N permutations that ahieves the lower bound by using the uniform mapping property of the bit-reversal permutation. To further redue the implementation omplexity, we also proposed a fully meshed fat-tree network that replaes the upper half of the tree by a simple mesh, and showed a fully meshed fat-tree network an be implemented by olleting swithes in a folded banyan-type network that realizes this set of N permutations. There are some researh topis that require further study. (i) Inremental update of the number of lineards: In this report, the number of input/output ports is assumed to be a power of. For the purpose of inremental update of the number of lineards, there are solutions by using twister networks [] and degenerated banyan networks []. It seems that the approahes used there might also be appliable to our setting in this report. (ii) Uniform mapping property: It is our belief that the uniform mapping property should be equivalent to the ondition previously stated in Theorem in []. As shown in Theorems in [], there are other sets of permutations that have the uniform mapping property. In partiular, if a permutation σ has the uniform mapping property, then pσ defined by (pσ)(x) = pσ(x) mod N for x Z N, also has the uniform mapping property when p is an odd number. This implies that one an ombine the bit-reversal permutation and the n permutations in a n n symmetri TDM swith to form another set of permutations that an also be used for implementing load-balaned swithes with fat-tree networks. Further development along this diretion will be reported separately. APPENDIX A PROOF OF () AND () We first note from u = i and () (with j = ) that the binary representations of u and v given by (I n (u ), I n (u ),..., I (u )) = (I n (i),..., I n/+ (i), I n/ (i),..., I (i), I (i)), (I n (v ), I n (v ),..., I (v )) = (I n (i),..., I n/+ (i), I n/ (i),..., I (i), I n (o)). By using () with j =,,..., n/ (in that order) and () with j =,,..., n/ (in that order), we an obtain the binary representations of u j and v j for j n/ as follows: (I n (u j ), I n (u j ),..., I (u j )) = (I n (i),..., I n/+ (i), I n/ (i),..., I j+ (i), I n (o), I n (o),..., I n j+ (o), I j (i)) (I n (v j ), I n (v j ),..., I (v j )) = (I n (i),..., I n/+ (i), I n/ (i),..., I j+ (i), Thus, () is proved. I n (o), I n (o),..., I n j+ (o), I n j+ (o)). After the perfet shuffle in the middle, we have from () (with j = n/), (), and () (with j = n/ + ) that the binary representations of u n/+ and v n/+ are given by (I n (u n/+ ), I n (u n/+ ),..., I (u n/+ )) = (I n (o), I n (o),..., I n/+ (o), I n (i), I n (i),..., I n/+ (i), I n/+ (i)), (I n (v n/+ ), I n (v n/+ ),..., I (v n/+ )) = (I n (o), I n (o),..., I n/+ (o), I n (i), I n (i),..., I n/+ (i), I n/ (o)). Finally, by using () with j = n/+, n/+,..., n (in that order) and () with j = n/ +, n/ +,..., n (in that order), we an obtain the binary representations of u j and v j for n/ + j n as follows: (I n (u j ), I n (u j ),..., I (u j )) = (I n (o), I n (o),..., I n/+ (o),..., I n j+ (o), I n (i), I n (i),..., I j+ (i), I j (i)), (I n (v j ), I n (v j ),..., I (v j )) = (I n (o), I n (o),..., I n/+ (o),..., I n j+ (o) I n (i), I n (i),..., I j+ (i), I n j+ (o)). Therefore, () is proved. APPENDIX B PROOF OF THE CLAIMS IN SECTION V-B In this appendix, we show the following laims in Setion V-B: (i) The two output links of eah swith in F j (k) are onneted to two different swithes in F j+ ( k/ ) for j n/ and k n j. (ii) The two output links of eah swith in F n j+ (k) are onneted to one swith in F n j+ (k) and another swith in F n j+ (k + ) for j n/ and k n j. (iii) Exatly one of the n/ output links of the n/ swithes in F n/ (k) is onneted to a swith in F n/+ (k ) for all k, k n/. (i) First we show that the two output links of eah swith in F j (k) are onneted to two different swithes in F j+ ( k/ ) for j n/ and k n j. To see this, let j n/ and k n j, and onsider a swith in F j (k) with index x S(n j +, k). From () and I n j+ (k) = (as k n j ), we see that the binary representation of x is given by (I n (x), I n (x),..., I (x)) = (, I n j (k), I n j (k),..., I (k), I (k), I j (x), I j (x),..., I (x)). () Clearly, the binary representations of the two outputs x and

11 x + of swith x in the j th stage are given by (I n (x), I n (x),..., I (x)) = (I n j (k), I n j (k),..., I (k), I (k), I j (x), I j (x),..., I (x), ), () (I n (x + ), I n (x + ),..., I (x + )) = (I n j (k), I n j (k),..., I (k), I (k), I j (x), I j (x),..., I (x), ). () Let output x (resp., x + ) of swith x in the j th stage be onneted to input y (resp., z) of swith y/ (resp., z/ ) in the (j + ) th stage. Then we have from (), (), and () that the binary representations of y and z are given by (I n (y), I n (y),..., I (y)) = (I n j (k), I n j (k),..., I (k), I j (x), I j (x),..., I (x),, I (k)), () (I n (z), I n (z),..., I (z)) = (I n j (k), I n j (k),..., I (k), I j (x), I j (x),..., I (x),, I (k)). () As we have from () and () that y/ = n j m= n j I m (k) j+m + j m= j I m (x) m, z/ = I m (k) j+m + I m (x) m +, m= m= it follows from n j m= I m(k) j+m = (k I (k)) j = k/ j and j m= I m(x) m j that k/ j y/ ( k/ + ) j, () k/ j z/ ( k/ + ) j. () As suh, we see from (), (), and () that y/ = z/ and y/, z/ S(n j, k/ ), and hene the two output links of swith x in F j (k) are onneted to two different swithes in F j+ ( k/ ). (ii) Now we show that the two output links of eah swith in F n j+ (k) are onneted to one swith in F n j+ (k) and another swith in F n j+ (k + ) for j n/ and k n j. To see this, let j n/ and k n j, and onsider a swith in F n j+ (k) with index x S(n j +, k). As before, the binary representations of the two outputs x and x + of swith x in the (n j + ) th stage are given by () and (), respetively. Let output x (resp., x + ) of swith x in the (n j + ) th stage be onneted to input y (resp., z) of swith y/ (resp., z/ ) in the (n j + ) th stage. Then we have from (), (), and () that the binary representations of y and z are given by (I n (y), I n (y),..., I (y)) = (I n j (k), I n j (k),..., I (k),, I j (x), I j (x),..., I (x), I (x)), () (I n (z), I n (z),..., I (z)) = (I n j (k), I n j (k),..., I (k),, I j (x), I j (x),..., I (x), I (x)). () As we have from () and () that y/ = n j m= n j I m (k) j+m + j m= z/ = I m (k) j+m + j + m= I m (x) m, j m= I m (x) m, it follows from n j m= I m(k) j+m = k j = k j and j m= I m(x) m j that k j y/ (k + ) j, () (k + ) j z/ (k + ) j. () As suh, we see from (), (), and () that y/ = z/, y/ S(n j +, k), and z/ S(n j +, k + ), and hene the two output links of swith x in F n j+ (k) are onneted to one swith in F n j+ (k) and another swith in F n j+ (k + ). (iii) Finally, we show that exatly one of the n/ output links of the n/ swithes in F n/ (k) is onneted to a swith in F n/+ (k ) for all k, k n/. To see this, let k n/, and onsider a swith in F n/ (k) with index x S(n/ +, k). It an be seen that () () still hold for j = n/, and hene the binary representations of x and its two outputs x and x + are given by (I n (x), I n (x),..., I (x)) = (, I n/ (k), I n/ (k),..., I (k), I n/ (x), I n/ (x),..., I (x)), () (I n (x), I n (x),..., I (x)) = (I n/ (k), I n/ (k),..., I (k), I n/ (x), I n/ (x),..., I (x), ), () (I n (x + ), I n (x + ),..., I (x + )) = (I n/ (k), I n/ (k),..., I (k), I n/ (x), I n/ (x),..., I (x), ). () Let output x (resp., x+) of swith x in the (n/) th stage be onneted to input y (resp., z) of swith y/ (resp., z/ ) in the (n/ + ) th stage. Then we have from (), (), and

12 () that the binary representations of y and z are given by (I n (y), I n (y),..., I (y)) = (I n/ (x), I n/ (x),..., I (x),, I n/ (k), I n/ (k),..., I (k), I (k)), () (I n (z), I n (z),..., I (z)) = (I n/ (x), I n/ (x),..., I (x),, I n/ (k), I n/ (k),..., I (k), I (k)). () From () and (), we have y/ = z/ = n/ m= n/ m= I m (x) n/+m + n/ m= I m (x) n/+m + n/ + I m (k) m, n/ m= I m (k) m. Let k = n/ m= I m (x) m (note that k ( n/ ) = n/ ). It then follows from n/ m= I m(k) m n/ that k n/ y/ (k + ) n/, () (k + ) n/ z/ (k + ) n/. () Sine k, k + n/, we see from (), (), and () that y/ S(n/ +, k ) and z/ S(n/ +, k + ), and hene the two output links of swith x in F n/ (k) are onneted to one swith in F n/+ (k ) and another swith in F n/+ (k +). As I n/ (x), I n/ (x),..., I (x) goes from (,,..., ), (,,..., ),..., (,,..., ) (note that there are n/ swith in F n/ (k)), we see from k (, ), (, ),..., ( n/, n/ ). As suh, exatly one of the n/ output links of the n/ swithes in F n/ (k) is onneted to a swith in F n/+ (k ) for all k n/. = n/ m= I m (x) m that (k, k + ) goes from [] C.-M. Lien, C.-S. Chang, J. Cheng, D.-S. Lee, and J.-T. Liao, Using banyan networks for load-balaned swithes with inremental update, in Proeedings IEEE International Conferene on Communiations (ICC ), Cape Town, South Afria, May,. [] C. E. Leiserson, Fat-trees: Universal networks for hardware-effiient superomputing, IEEE Transations on Computers, vol., pp., Otober. [] M. Al-Fares, A. Loukissas, and A. Vahdat, A salable, ommodity data enter network arhiteture, in Proeedings ACM Speial Interest Group on Data Communiation (SIGCOMM ), Seattle, WA, USA, August,. [] H. Hossain, M. Akbar, and M. Islam, Extended-butterfly fat tree interonnetion (EFTI) arhiteture for network on hip, in Proeedings IEEE Paifi Rim Conferene on Communiations, Computers and Signal Proessing (PaRim ), Vitoria, B.C., Canada, August,. [] C. -L. Wu and S. -Y. Feng, The Reverse-Exhange Interonnetion Network, IEEE Transations on Computers, vol. -, pp., September. [] S.-Y. R. Li, Algebrai Swithing Theory and Broadband Appliations, San Diego, CA: Aademi Press,. REFERENCES [] C.-S. Chang, D.-S. Lee, and Y.-S. Jou, Load balaned Birkhoff-von Neumann swithes Part I: One-stage buffering, Computer Communiations, vol., pp.,. [] I. Keslassy, S.-T. Chung, K. Yu, D. Miller, M. Horowitz, O. Sloggard, and N. MKeown, Saling Internet routers using optis, in Proeedings ACM Speial Interest Group on Data Communiation (SIGCOMM ), Karlsruhe, Germany, August,. [] I. Keslassy, S.-T. Chung, and N. MKeown, A load-balaned swith with an arbitrary number of lineards, in Proeedings IEEE International Conferene on Computer Communiations (INFOCOM ), Hong Kong, China, Marh,. [] Y. Shen, S. Jiang, S. S. Panwar, and H. J. Chao, Byte-foal: a pratial load-balaned swith, in Proeedings IEEE Workshop on High Performane Swithing and Routing (HPSR ), Hong Kong, China, May,. [] J.-J. Jaramillo, F. Milan, and R. Srikant, Padded frames: a novel algorithm for stable sheduling in load-balaned swithes, IEEE/ACM Transations on Networking, vol., pp., Otober. [] C.-L. Yu, C.-S. Chang, and D.-S. Lee, CR swith: A load-balaned swith with ontention and reservation, IEEE Transations on Communiations, vol., pp., Otober. [] C.-M. Lien, C.-S. Chang, J. Cheng, D.-S. Lee, and J.-T. Liao, Twister networks and their appliations to load-balaned swithes, in Proeedings IEEE International Conferene on Computer Communiations (INFOCOM ), San Diego, CA, USA, Marh,.

Algorithms for External Memory Lecture 6 Graph Algorithms - Weighted List Ranking

Algorithms for External Memory Lecture 6 Graph Algorithms - Weighted List Ranking Algorithms for External Memory Leture 6 Graph Algorithms - Weighted List Ranking Leturer: Nodari Sithinava Sribe: Andi Hellmund, Simon Ohsenreither 1 Introdution & Motivation After talking about I/O-effiient

More information

On - Line Path Delay Fault Testing of Omega MINs M. Bellos 1, E. Kalligeros 1, D. Nikolos 1,2 & H. T. Vergos 1,2

On - Line Path Delay Fault Testing of Omega MINs M. Bellos 1, E. Kalligeros 1, D. Nikolos 1,2 & H. T. Vergos 1,2 On - Line Path Delay Fault Testing of Omega MINs M. Bellos, E. Kalligeros, D. Nikolos,2 & H. T. Vergos,2 Dept. of Computer Engineering and Informatis 2 Computer Tehnology Institute University of Patras,

More information

A Dual-Hamiltonian-Path-Based Multicasting Strategy for Wormhole-Routed Star Graph Interconnection Networks

A Dual-Hamiltonian-Path-Based Multicasting Strategy for Wormhole-Routed Star Graph Interconnection Networks A Dual-Hamiltonian-Path-Based Multiasting Strategy for Wormhole-Routed Star Graph Interonnetion Networks Nen-Chung Wang Department of Information and Communiation Engineering Chaoyang University of Tehnology,

More information

Multi-Channel Wireless Networks: Capacity and Protocols

Multi-Channel Wireless Networks: Capacity and Protocols Multi-Channel Wireless Networks: Capaity and Protools Tehnial Report April 2005 Pradeep Kyasanur Dept. of Computer Siene, and Coordinated Siene Laboratory, University of Illinois at Urbana-Champaign Email:

More information

HEXA: Compact Data Structures for Faster Packet Processing

HEXA: Compact Data Structures for Faster Packet Processing Washington University in St. Louis Washington University Open Sholarship All Computer Siene and Engineering Researh Computer Siene and Engineering Report Number: 27-26 27 HEXA: Compat Data Strutures for

More information

Pipelined Multipliers for Reconfigurable Hardware

Pipelined Multipliers for Reconfigurable Hardware Pipelined Multipliers for Reonfigurable Hardware Mithell J. Myjak and José G. Delgado-Frias Shool of Eletrial Engineering and Computer Siene, Washington State University Pullman, WA 99164-2752 USA {mmyjak,

More information

Flow Demands Oriented Node Placement in Multi-Hop Wireless Networks

Flow Demands Oriented Node Placement in Multi-Hop Wireless Networks Flow Demands Oriented Node Plaement in Multi-Hop Wireless Networks Zimu Yuan Institute of Computing Tehnology, CAS, China {zimu.yuan}@gmail.om arxiv:153.8396v1 [s.ni] 29 Mar 215 Abstrat In multi-hop wireless

More information

Gray Codes for Reflectable Languages

Gray Codes for Reflectable Languages Gray Codes for Refletable Languages Yue Li Joe Sawada Marh 8, 2008 Abstrat We lassify a type of language alled a refletable language. We then develop a generi algorithm that an be used to list all strings

More information

What are Cycle-Stealing Systems Good For? A Detailed Performance Model Case Study

What are Cycle-Stealing Systems Good For? A Detailed Performance Model Case Study What are Cyle-Stealing Systems Good For? A Detailed Performane Model Case Study Wayne Kelly and Jiro Sumitomo Queensland University of Tehnology, Australia {w.kelly, j.sumitomo}@qut.edu.au Abstrat The

More information

Dynamic Algorithms Multiple Choice Test

Dynamic Algorithms Multiple Choice Test 3226 Dynami Algorithms Multiple Choie Test Sample test: only 8 questions 32 minutes (Real test has 30 questions 120 minutes) Årskort Name Eah of the following 8 questions has 4 possible answers of whih

More information

Accommodations of QoS DiffServ Over IP and MPLS Networks

Accommodations of QoS DiffServ Over IP and MPLS Networks Aommodations of QoS DiffServ Over IP and MPLS Networks Abdullah AlWehaibi, Anjali Agarwal, Mihael Kadoh and Ahmed ElHakeem Department of Eletrial and Computer Department de Genie Eletrique Engineering

More information

Analysis of input and output configurations for use in four-valued CCD programmable logic arrays

Analysis of input and output configurations for use in four-valued CCD programmable logic arrays nalysis of input and output onfigurations for use in four-valued D programmable logi arrays J.T. utler H.G. Kerkhoff ndexing terms: Logi, iruit theory and design, harge-oupled devies bstrat: s in binary,

More information

Automatic Physical Design Tuning: Workload as a Sequence Sanjay Agrawal Microsoft Research One Microsoft Way Redmond, WA, USA +1-(425)

Automatic Physical Design Tuning: Workload as a Sequence Sanjay Agrawal Microsoft Research One Microsoft Way Redmond, WA, USA +1-(425) Automati Physial Design Tuning: Workload as a Sequene Sanjay Agrawal Mirosoft Researh One Mirosoft Way Redmond, WA, USA +1-(425) 75-357 sagrawal@mirosoft.om Eri Chu * Computer Sienes Department University

More information

The Minimum Redundancy Maximum Relevance Approach to Building Sparse Support Vector Machines

The Minimum Redundancy Maximum Relevance Approach to Building Sparse Support Vector Machines The Minimum Redundany Maximum Relevane Approah to Building Sparse Support Vetor Mahines Xiaoxing Yang, Ke Tang, and Xin Yao, Nature Inspired Computation and Appliations Laboratory (NICAL), Shool of Computer

More information

Partial Character Decoding for Improved Regular Expression Matching in FPGAs

Partial Character Decoding for Improved Regular Expression Matching in FPGAs Partial Charater Deoding for Improved Regular Expression Mathing in FPGAs Peter Sutton Shool of Information Tehnology and Eletrial Engineering The University of Queensland Brisbane, Queensland, 4072, Australia

More information

Sparse Certificates for 2-Connectivity in Directed Graphs

Sparse Certificates for 2-Connectivity in Directed Graphs Sparse Certifiates for 2-Connetivity in Direted Graphs Loukas Georgiadis Giuseppe F. Italiano Aikaterini Karanasiou Charis Papadopoulos Nikos Parotsidis Abstrat Motivated by the emergene of large-sale

More information

A Partial Sorting Algorithm in Multi-Hop Wireless Sensor Networks

A Partial Sorting Algorithm in Multi-Hop Wireless Sensor Networks A Partial Sorting Algorithm in Multi-Hop Wireless Sensor Networks Abouberine Ould Cheikhna Department of Computer Siene University of Piardie Jules Verne 80039 Amiens Frane Ould.heikhna.abouberine @u-piardie.fr

More information

Incremental Mining of Partial Periodic Patterns in Time-series Databases

Incremental Mining of Partial Periodic Patterns in Time-series Databases CERIAS Teh Report 2000-03 Inremental Mining of Partial Periodi Patterns in Time-series Dataases Mohamed G. Elfeky Center for Eduation and Researh in Information Assurane and Seurity Purdue University,

More information

A DYNAMIC ACCESS CONTROL WITH BINARY KEY-PAIR

A DYNAMIC ACCESS CONTROL WITH BINARY KEY-PAIR Malaysian Journal of Computer Siene, Vol 10 No 1, June 1997, pp 36-41 A DYNAMIC ACCESS CONTROL WITH BINARY KEY-PAIR Md Rafiqul Islam, Harihodin Selamat and Mohd Noor Md Sap Faulty of Computer Siene and

More information

Extracting Partition Statistics from Semistructured Data

Extracting Partition Statistics from Semistructured Data Extrating Partition Statistis from Semistrutured Data John N. Wilson Rihard Gourlay Robert Japp Mathias Neumüller Department of Computer and Information Sienes University of Strathlyde, Glasgow, UK {jnw,rsg,rpj,mathias}@is.strath.a.uk

More information

Performance Benchmarks for an Interactive Video-on-Demand System

Performance Benchmarks for an Interactive Video-on-Demand System Performane Benhmarks for an Interative Video-on-Demand System. Guo,P.G.Taylor,E.W.M.Wong,S.Chan,M.Zukerman andk.s.tang ARC Speial Researh Centre for Ultra-Broadband Information Networks (CUBIN) Department

More information

Colouring contact graphs of squares and rectilinear polygons de Berg, M.T.; Markovic, A.; Woeginger, G.

Colouring contact graphs of squares and rectilinear polygons de Berg, M.T.; Markovic, A.; Woeginger, G. Colouring ontat graphs of squares and retilinear polygons de Berg, M.T.; Markovi, A.; Woeginger, G. Published in: nd European Workshop on Computational Geometry (EuroCG 06), 0 Marh - April, Lugano, Switzerland

More information

Cluster-based Cooperative Communication with Network Coding in Wireless Networks

Cluster-based Cooperative Communication with Network Coding in Wireless Networks Cluster-based Cooperative Communiation with Network Coding in Wireless Networks Zygmunt J. Haas Shool of Eletrial and Computer Engineering Cornell University Ithaa, NY 4850, U.S.A. Email: haas@ee.ornell.edu

More information

Constructing Transaction Serialization Order for Incremental. Data Warehouse Refresh. Ming-Ling Lo and Hui-I Hsiao. IBM T. J. Watson Research Center

Constructing Transaction Serialization Order for Incremental. Data Warehouse Refresh. Ming-Ling Lo and Hui-I Hsiao. IBM T. J. Watson Research Center Construting Transation Serialization Order for Inremental Data Warehouse Refresh Ming-Ling Lo and Hui-I Hsiao IBM T. J. Watson Researh Center July 11, 1997 Abstrat In typial pratie of data warehouse, the

More information

mahines. HBSP enhanes the appliability of the BSP model by inorporating parameters that reet the relative speeds of the heterogeneous omputing omponen

mahines. HBSP enhanes the appliability of the BSP model by inorporating parameters that reet the relative speeds of the heterogeneous omputing omponen The Heterogeneous Bulk Synhronous Parallel Model Tiani L. Williams and Rebea J. Parsons Shool of Computer Siene University of Central Florida Orlando, FL 32816-2362 fwilliams,rebeag@s.uf.edu Abstrat. Trends

More information

A {k, n}-secret Sharing Scheme for Color Images

A {k, n}-secret Sharing Scheme for Color Images A {k, n}-seret Sharing Sheme for Color Images Rastislav Luka, Konstantinos N. Plataniotis, and Anastasios N. Venetsanopoulos The Edward S. Rogers Sr. Dept. of Eletrial and Computer Engineering, University

More information

XML Data Streams. XML Stream Processing. XML Stream Processing. Yanlei Diao. University of Massachusetts Amherst

XML Data Streams. XML Stream Processing. XML Stream Processing. Yanlei Diao. University of Massachusetts Amherst XML Stream Proessing Yanlei Diao University of Massahusetts Amherst XML Data Streams XML is the wire format for data exhanged online. Purhase orders http://www.oasis-open.org/ommittees/t_home.php?wg_abbrev=ubl

More information

We don t need no generation - a practical approach to sliding window RLNC

We don t need no generation - a practical approach to sliding window RLNC We don t need no generation - a pratial approah to sliding window RLNC Simon Wunderlih, Frank Gabriel, Sreekrishna Pandi, Frank H.P. Fitzek Deutshe Telekom Chair of Communiation Networks, TU Dresden, Dresden,

More information

Parallelizing Frequent Web Access Pattern Mining with Partial Enumeration for High Speedup

Parallelizing Frequent Web Access Pattern Mining with Partial Enumeration for High Speedup Parallelizing Frequent Web Aess Pattern Mining with Partial Enumeration for High Peiyi Tang Markus P. Turkia Department of Computer Siene Department of Computer Siene University of Arkansas at Little Rok

More information

System-Level Parallelism and Throughput Optimization in Designing Reconfigurable Computing Applications

System-Level Parallelism and Throughput Optimization in Designing Reconfigurable Computing Applications System-Level Parallelism and hroughput Optimization in Designing Reonfigurable Computing Appliations Esam El-Araby 1, Mohamed aher 1, Kris Gaj 2, arek El-Ghazawi 1, David Caliga 3, and Nikitas Alexandridis

More information

A Load-Balanced Clustering Protocol for Hierarchical Wireless Sensor Networks

A Load-Balanced Clustering Protocol for Hierarchical Wireless Sensor Networks International Journal of Advanes in Computer Networks and Its Seurity IJCNS A Load-Balaned Clustering Protool for Hierarhial Wireless Sensor Networks Mehdi Tarhani, Yousef S. Kavian, Saman Siavoshi, Ali

More information

Cross-layer Resource Allocation on Broadband Power Line Based on Novel QoS-priority Scheduling Function in MAC Layer

Cross-layer Resource Allocation on Broadband Power Line Based on Novel QoS-priority Scheduling Function in MAC Layer Communiations and Networ, 2013, 5, 69-73 http://dx.doi.org/10.4236/n.2013.53b2014 Published Online September 2013 (http://www.sirp.org/journal/n) Cross-layer Resoure Alloation on Broadband Power Line Based

More information

Australian Journal of Basic and Applied Sciences. A new Divide and Shuffle Based algorithm of Encryption for Text Message

Australian Journal of Basic and Applied Sciences. A new Divide and Shuffle Based algorithm of Encryption for Text Message ISSN:1991-8178 Australian Journal of Basi and Applied Sienes Journal home page: www.ajbasweb.om A new Divide and Shuffle Based algorithm of Enryption for Text Message Dr. S. Muthusundari R.M.D. Engineering

More information

Data Structures in Java

Data Structures in Java Data Strutures in Java Leture 8: Trees and Tree Traversals. 10/5/2015 Daniel Bauer 1 Trees in Computer Siene A lot of data omes in a hierarhial/nested struture. Mathematial expressions. Program struture.

More information

SVC-DASH-M: Scalable Video Coding Dynamic Adaptive Streaming Over HTTP Using Multiple Connections

SVC-DASH-M: Scalable Video Coding Dynamic Adaptive Streaming Over HTTP Using Multiple Connections SVC-DASH-M: Salable Video Coding Dynami Adaptive Streaming Over HTTP Using Multiple Connetions Samar Ibrahim, Ahmed H. Zahran and Mahmoud H. Ismail Department of Eletronis and Eletrial Communiations, Faulty

More information

DECODING OF ARRAY LDPC CODES USING ON-THE FLY COMPUTATION Kiran Gunnam, Weihuang Wang, Euncheol Kim, Gwan Choi, Mark Yeary *

DECODING OF ARRAY LDPC CODES USING ON-THE FLY COMPUTATION Kiran Gunnam, Weihuang Wang, Euncheol Kim, Gwan Choi, Mark Yeary * DECODING OF ARRAY LDPC CODES USING ON-THE FLY COMPUTATION Kiran Gunnam, Weihuang Wang, Eunheol Kim, Gwan Choi, Mark Yeary * Dept. of Eletrial Engineering, Texas A&M University, College Station, TX-77840

More information

Reduced-Complexity Column-Layered Decoding and. Implementation for LDPC Codes

Reduced-Complexity Column-Layered Decoding and. Implementation for LDPC Codes Redued-Complexity Column-Layered Deoding and Implementation for LDPC Codes Zhiqiang Cui 1, Zhongfeng Wang 2, Senior Member, IEEE, and Xinmiao Zhang 3 1 Qualomm In., San Diego, CA 92121, USA 2 Broadom Corp.,

More information

Establishing Secure Ethernet LANs Using Intelligent Switching Hubs in Internet Environments

Establishing Secure Ethernet LANs Using Intelligent Switching Hubs in Internet Environments Establishing Seure Ethernet LANs Using Intelligent Swithing Hubs in Internet Environments WOEIJIUNN TSAUR AND SHIJINN HORNG Department of Eletrial Engineering, National Taiwan University of Siene and Tehnology,

More information

1 The Knuth-Morris-Pratt Algorithm

1 The Knuth-Morris-Pratt Algorithm 5-45/65: Design & Analysis of Algorithms September 26, 26 Leture #9: String Mathing last hanged: September 26, 27 There s an entire field dediated to solving problems on strings. The book Algorithms on

More information

Algorithms, Mechanisms and Procedures for the Computer-aided Project Generation System

Algorithms, Mechanisms and Procedures for the Computer-aided Project Generation System Algorithms, Mehanisms and Proedures for the Computer-aided Projet Generation System Anton O. Butko 1*, Aleksandr P. Briukhovetskii 2, Dmitry E. Grigoriev 2# and Konstantin S. Kalashnikov 3 1 Department

More information

Approximate logic synthesis for error tolerant applications

Approximate logic synthesis for error tolerant applications Approximate logi synthesis for error tolerant appliations Doohul Shin and Sandeep K. Gupta Eletrial Engineering Department, University of Southern California, Los Angeles, CA 989 {doohuls, sandeep}@us.edu

More information

Fast Distribution of Replicated Content to Multi- Homed Clients Mohammad Malli Arab Open University, Beirut, Lebanon

Fast Distribution of Replicated Content to Multi- Homed Clients Mohammad Malli Arab Open University, Beirut, Lebanon ACEEE Int. J. on Information Tehnology, Vol. 3, No. 2, June 2013 Fast Distribution of Repliated Content to Multi- Homed Clients Mohammad Malli Arab Open University, Beirut, Lebanon Email: mmalli@aou.edu.lb

More information

NONLINEAR BACK PROJECTION FOR TOMOGRAPHIC IMAGE RECONSTRUCTION. Ken Sauer and Charles A. Bouman

NONLINEAR BACK PROJECTION FOR TOMOGRAPHIC IMAGE RECONSTRUCTION. Ken Sauer and Charles A. Bouman NONLINEAR BACK PROJECTION FOR TOMOGRAPHIC IMAGE RECONSTRUCTION Ken Sauer and Charles A. Bouman Department of Eletrial Engineering, University of Notre Dame Notre Dame, IN 46556, (219) 631-6999 Shool of

More information

Distributed Resource Allocation Strategies for Achieving Quality of Service in Server Clusters

Distributed Resource Allocation Strategies for Achieving Quality of Service in Server Clusters Proeedings of the 45th IEEE Conferene on Deision & Control Manhester Grand Hyatt Hotel an Diego, CA, UA, Deember 13-15, 2006 Distributed Resoure Alloation trategies for Ahieving Quality of ervie in erver

More information

A Novel Bit Level Time Series Representation with Implication of Similarity Search and Clustering

A Novel Bit Level Time Series Representation with Implication of Similarity Search and Clustering A Novel Bit Level Time Series Representation with Impliation of Similarity Searh and lustering hotirat Ratanamahatana, Eamonn Keogh, Anthony J. Bagnall 2, and Stefano Lonardi Dept. of omputer Siene & Engineering,

More information

Fuzzy Meta Node Fuzzy Metagraph and its Cluster Analysis

Fuzzy Meta Node Fuzzy Metagraph and its Cluster Analysis Journal of Computer Siene 4 (): 9-97, 008 ISSN 549-3636 008 Siene Publiations Fuzzy Meta Node Fuzzy Metagraph and its Cluster Analysis Deepti Gaur, Aditya Shastri and Ranjit Biswas Department of Computer

More information

Performance of Histogram-Based Skin Colour Segmentation for Arms Detection in Human Motion Analysis Application

Performance of Histogram-Based Skin Colour Segmentation for Arms Detection in Human Motion Analysis Application World Aademy of Siene, Engineering and Tehnology 8 009 Performane of Histogram-Based Skin Colour Segmentation for Arms Detetion in Human Motion Analysis Appliation Rosalyn R. Porle, Ali Chekima, Farrah

More information

A Novel Validity Index for Determination of the Optimal Number of Clusters

A Novel Validity Index for Determination of the Optimal Number of Clusters IEICE TRANS. INF. & SYST., VOL.E84 D, NO.2 FEBRUARY 2001 281 LETTER A Novel Validity Index for Determination of the Optimal Number of Clusters Do-Jong KIM, Yong-Woon PARK, and Dong-Jo PARK, Nonmembers

More information

1. Inversions. A geometric construction relating points O, A and B looks as follows.

1. Inversions. A geometric construction relating points O, A and B looks as follows. 1. Inversions. 1.1. Definitions of inversion. Inversion is a kind of symmetry about a irle. It is defined as follows. he inversion of degree R 2 entered at a point maps a point to the point on the ray

More information

Using Game Theory and Bayesian Networks to Optimize Cooperation in Ad Hoc Wireless Networks

Using Game Theory and Bayesian Networks to Optimize Cooperation in Ad Hoc Wireless Networks Using Game Theory and Bayesian Networks to Optimize Cooperation in Ad Ho Wireless Networks Giorgio Quer, Federio Librino, Lua Canzian, Leonardo Badia, Mihele Zorzi, University of California San Diego La

More information

THROUGHPUT EVALUATION OF AN ASYMMETRICAL FDDI TOKEN RING NETWORK WITH MULTIPLE CLASSES OF TRAFFIC

THROUGHPUT EVALUATION OF AN ASYMMETRICAL FDDI TOKEN RING NETWORK WITH MULTIPLE CLASSES OF TRAFFIC THROUGHPUT EVALUATION OF AN ASYMMETRICAL FDDI TOKEN RING NETWORK WITH MULTIPLE CLASSES OF TRAFFIC Priya N. Werahera and Anura P. Jayasumana Department of Eletrial Engineering Colorado State University

More information

arxiv: v1 [cs.db] 13 Sep 2017

arxiv: v1 [cs.db] 13 Sep 2017 An effiient lustering algorithm from the measure of loal Gaussian distribution Yuan-Yen Tai (Dated: May 27, 2018) In this paper, I will introdue a fast and novel lustering algorithm based on Gaussian distribution

More information

Dr.Hazeem Al-Khafaji Dept. of Computer Science, Thi-Qar University, College of Science, Iraq

Dr.Hazeem Al-Khafaji Dept. of Computer Science, Thi-Qar University, College of Science, Iraq Volume 4 Issue 6 June 014 ISSN: 77 18X International Journal of Advaned Researh in Computer Siene and Software Engineering Researh Paper Available online at: www.ijarsse.om Medial Image Compression using

More information

Design and Analysis of a Robust Pipelined Memory System

Design and Analysis of a Robust Pipelined Memory System Design and Analysis of a obust Pipelined Memory System Hao ang 1 Haiquan (Chuk) Zhao 2 Bill Lin 1 Jun (Jim) Xu 2 1 Department of Eletrial and Computer Engineering, University of California, San Diego Email

More information

Cluster-Based Cumulative Ensembles

Cluster-Based Cumulative Ensembles Cluster-Based Cumulative Ensembles Hanan G. Ayad and Mohamed S. Kamel Pattern Analysis and Mahine Intelligene Lab, Eletrial and Computer Engineering, University of Waterloo, Waterloo, Ontario N2L 3G1,

More information

An Optimized Approach on Applying Genetic Algorithm to Adaptive Cluster Validity Index

An Optimized Approach on Applying Genetic Algorithm to Adaptive Cluster Validity Index IJCSES International Journal of Computer Sienes and Engineering Systems, ol., No.4, Otober 2007 CSES International 2007 ISSN 0973-4406 253 An Optimized Approah on Applying Geneti Algorithm to Adaptive

More information

1. The collection of the vowels in the word probability. 2. The collection of real numbers that satisfy the equation x 9 = 0.

1. The collection of the vowels in the word probability. 2. The collection of real numbers that satisfy the equation x 9 = 0. C HPTER 1 SETS I. DEFINITION OF SET We begin our study of probability with the disussion of the basi onept of set. We assume that there is a ommon understanding of what is meant by the notion of a olletion

More information

Unsupervised Stereoscopic Video Object Segmentation Based on Active Contours and Retrainable Neural Networks

Unsupervised Stereoscopic Video Object Segmentation Based on Active Contours and Retrainable Neural Networks Unsupervised Stereosopi Video Objet Segmentation Based on Ative Contours and Retrainable Neural Networks KLIMIS NTALIANIS, ANASTASIOS DOULAMIS, and NIKOLAOS DOULAMIS National Tehnial University of Athens

More information

Recommendation Subgraphs for Web Discovery

Recommendation Subgraphs for Web Discovery Reommation Subgraphs for Web Disovery Arda Antikaioglu Department of Mathematis Carnegie Mellon University aantika@andrew.mu.edu R. Ravi Tepper Shool of Business Carnegie Mellon University ravi@mu.edu

More information

Multi-hop Fast Conflict Resolution Algorithm for Ad Hoc Networks

Multi-hop Fast Conflict Resolution Algorithm for Ad Hoc Networks Multi-hop Fast Conflit Resolution Algorithm for Ad Ho Networks Shengwei Wang 1, Jun Liu 2,*, Wei Cai 2, Minghao Yin 2, Lingyun Zhou 2, and Hui Hao 3 1 Power Emergeny Center, Sihuan Eletri Power Corporation,

More information

Dynamic Programming. Lecture #8 of Algorithms, Data structures and Complexity. Joost-Pieter Katoen Formal Methods and Tools Group

Dynamic Programming. Lecture #8 of Algorithms, Data structures and Complexity. Joost-Pieter Katoen Formal Methods and Tools Group Dynami Programming Leture #8 of Algorithms, Data strutures and Complexity Joost-Pieter Katoen Formal Methods and Tools Group E-mail: katoen@s.utwente.nl Otober 29, 2002 JPK #8: Dynami Programming ADC (214020)

More information

RAC 2 E: Novel Rendezvous Protocol for Asynchronous Cognitive Radios in Cooperative Environments

RAC 2 E: Novel Rendezvous Protocol for Asynchronous Cognitive Radios in Cooperative Environments 21st Annual IEEE International Symposium on Personal, Indoor and Mobile Radio Communiations 1 RAC 2 E: Novel Rendezvous Protool for Asynhronous Cognitive Radios in Cooperative Environments Valentina Pavlovska,

More information

Capturing Large Intra-class Variations of Biometric Data by Template Co-updating

Capturing Large Intra-class Variations of Biometric Data by Template Co-updating Capturing Large Intra-lass Variations of Biometri Data by Template Co-updating Ajita Rattani University of Cagliari Piazza d'armi, Cagliari, Italy ajita.rattani@diee.unia.it Gian Lua Marialis University

More information

Exploring the Commonality in Feature Modeling Notations

Exploring the Commonality in Feature Modeling Notations Exploring the Commonality in Feature Modeling Notations Miloslav ŠÍPKA Slovak University of Tehnology Faulty of Informatis and Information Tehnologies Ilkovičova 3, 842 16 Bratislava, Slovakia miloslav.sipka@gmail.om

More information

Drawing lines. Naïve line drawing algorithm. drawpixel(x, round(y)); double dy = y1 - y0; double dx = x1 - x0; double m = dy / dx; double y = y0;

Drawing lines. Naïve line drawing algorithm. drawpixel(x, round(y)); double dy = y1 - y0; double dx = x1 - x0; double m = dy / dx; double y = y0; Naïve line drawing algorithm // Connet to grid points(x0,y0) and // (x1,y1) by a line. void drawline(int x0, int y0, int x1, int y1) { int x; double dy = y1 - y0; double dx = x1 - x0; double m = dy / dx;

More information

Anonymity Trilemma: Strong Anonymity, Low Bandwidth, Low Latency Choose Two

Anonymity Trilemma: Strong Anonymity, Low Bandwidth, Low Latency Choose Two Anonymity Trilemma: Strong Anonymity, Low Bandwidth, Low Lateny Choose Two Debajyoti Das Purdue University, USA das48@purdue.edu Sebastian Meiser University College London, U s.meiser@ul.a.uk Esfandiar

More information

Detecting Outliers in High-Dimensional Datasets with Mixed Attributes

Detecting Outliers in High-Dimensional Datasets with Mixed Attributes Deteting Outliers in High-Dimensional Datasets with Mixed Attributes A. Koufakou, M. Georgiopoulos, and G.C. Anagnostopoulos 2 Shool of EECS, University of Central Florida, Orlando, FL, USA 2 Dept. of

More information

Path Diversity for Overlay Multicast Streaming

Path Diversity for Overlay Multicast Streaming Path Diversity for Overlay Multiast Streaming Matulya Bansal and Avideh Zakhor Department of Eletrial Engineering and Computer Siene University of California, Berkeley Berkeley, CA 9472 {matulya, avz}@ees.berkeley.edu

More information

Detection and Recognition of Non-Occluded Objects using Signature Map

Detection and Recognition of Non-Occluded Objects using Signature Map 6th WSEAS International Conferene on CIRCUITS, SYSTEMS, ELECTRONICS,CONTROL & SIGNAL PROCESSING, Cairo, Egypt, De 9-31, 007 65 Detetion and Reognition of Non-Oluded Objets using Signature Map Sangbum Park,

More information

LRED: A Robust and Responsive AQM Algorithm Using Packet Loss Ratio Measurement

LRED: A Robust and Responsive AQM Algorithm Using Packet Loss Ratio Measurement IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, TPDS-179-5 1 LRED: A Robust and Responsive AQM Algorithm Using Paket Loss Ratio Measurement Chonggang Wang, Member, IEEE, Jianghuan Liu, Member, IEEE,

More information

Methods for Multi-Dimensional Robustness Optimization in Complex Embedded Systems

Methods for Multi-Dimensional Robustness Optimization in Complex Embedded Systems Methods for Multi-Dimensional Robustness Optimization in Complex Embedded Systems Arne Hamann, Razvan Rau, Rolf Ernst Institute of Computer and Communiation Network Engineering Tehnial University of Braunshweig,

More information

The Happy Ending Problem

The Happy Ending Problem The Happy Ending Problem Neeldhara Misra STATUTORY WARNING This doument is a draft version 1 Introdution The Happy Ending problem first manifested itself on a typial wintery evening in 1933 These evenings

More information

And, the (low-pass) Butterworth filter of order m is given in the frequency domain by

And, the (low-pass) Butterworth filter of order m is given in the frequency domain by Problem Set no.3.a) The ideal low-pass filter is given in the frequeny domain by B ideal ( f ), f f; =, f > f. () And, the (low-pass) Butterworth filter of order m is given in the frequeny domain by B

More information

DoS-Resistant Broadcast Authentication Protocol with Low End-to-end Delay

DoS-Resistant Broadcast Authentication Protocol with Low End-to-end Delay DoS-Resistant Broadast Authentiation Protool with Low End-to-end Delay Ying Huang, Wenbo He and Klara Nahrstedt {huang, wenbohe, klara}@s.uiu.edu Department of Computer Siene University of Illinois at

More information

Hard-Potato Routing. Maurice Herlihy y Brown University Providence, Rhode Island packets.

Hard-Potato Routing. Maurice Herlihy y Brown University Providence, Rhode Island packets. Hard-Potato Routing Costas Bush Λ Brown University Providene, Rhode Island b@s.brown.edu Maurie Herlihy y Brown University Providene, Rhode Island herlihy@s.brown.edu Roger Wattenhofer z Brown University

More information

Outline: Software Design

Outline: Software Design Outline: Software Design. Goals History of software design ideas Design priniples Design methods Life belt or leg iron? (Budgen) Copyright Nany Leveson, Sept. 1999 A Little History... At first, struggling

More information

Space- and Time-Efficient BDD Construction via Working Set Control

Space- and Time-Efficient BDD Construction via Working Set Control Spae- and Time-Effiient BDD Constrution via Working Set Control Bwolen Yang Yirng-An Chen Randal E. Bryant David R. O Hallaron Computer Siene Department Carnegie Mellon University Pittsburgh, PA 15213.

More information

Abstract. Key Words: Image Filters, Fuzzy Filters, Order Statistics Filters, Rank Ordered Mean Filters, Channel Noise. 1.

Abstract. Key Words: Image Filters, Fuzzy Filters, Order Statistics Filters, Rank Ordered Mean Filters, Channel Noise. 1. Fuzzy Weighted Rank Ordered Mean (FWROM) Filters for Mixed Noise Suppression from Images S. Meher, G. Panda, B. Majhi 3, M.R. Meher 4,,4 Department of Eletronis and I.E., National Institute of Tehnology,

More information

Multiple-Criteria Decision Analysis: A Novel Rank Aggregation Method

Multiple-Criteria Decision Analysis: A Novel Rank Aggregation Method 3537 Multiple-Criteria Deision Analysis: A Novel Rank Aggregation Method Derya Yiltas-Kaplan Department of Computer Engineering, Istanbul University, 34320, Avilar, Istanbul, Turkey Email: dyiltas@ istanbul.edu.tr

More information

References. December 1992, pp. 71 { 81. pp.457{467. Magazine, June for very large high throughput database systems,"

References. December 1992, pp. 71 { 81. pp.457{467. Magazine, June for very large high throughput database systems, the overall working time for other appliations. In ase, data ltering was the only appliation being run, then using distributed indexing, we an serve 00 times as many requests. 6 Conlusion We have explored

More information

On the Generation of Multiplexer Circuits for Pass Transistor Logic

On the Generation of Multiplexer Circuits for Pass Transistor Logic Preprint from Proeedings of DATE 2, Paris, rane, Marh 2 On the Generation of Multiplexer Ciruits for Pass Transistor Logi Christoph Sholl Bernd Beker Institute of Computer Siene Albert Ludwigs University

More information

Total 100

Total 100 CS331 SOLUTION Problem # Points 1 10 2 15 3 25 4 20 5 15 6 15 Total 100 1. ssume you are dealing with a ompiler for a Java-like language. For eah of the following errors, irle whih phase would normally

More information

Calculation of typical running time of a branch-and-bound algorithm for the vertex-cover problem

Calculation of typical running time of a branch-and-bound algorithm for the vertex-cover problem Calulation of typial running time of a branh-and-bound algorithm for the vertex-over problem Joni Pajarinen, Joni.Pajarinen@iki.fi Otober 21, 2007 1 Introdution The vertex-over problem is one of a olletion

More information

Solutions to Tutorial 2 (Week 9)

Solutions to Tutorial 2 (Week 9) The University of Syney Shool of Mathematis an Statistis Solutions to Tutorial (Week 9) MATH09/99: Disrete Mathematis an Graph Theory Semester, 0. Determine whether eah of the following sequenes is the

More information

Self-Adaptive Parent to Mean-Centric Recombination for Real-Parameter Optimization

Self-Adaptive Parent to Mean-Centric Recombination for Real-Parameter Optimization Self-Adaptive Parent to Mean-Centri Reombination for Real-Parameter Optimization Kalyanmoy Deb and Himanshu Jain Department of Mehanial Engineering Indian Institute of Tehnology Kanpur Kanpur, PIN 86 {deb,hjain}@iitk.a.in

More information

B4 and After: Managing Hierarchy, Partitioning, and Asymmetry for Availability and Scale in Google s Software-Defined WAN

B4 and After: Managing Hierarchy, Partitioning, and Asymmetry for Availability and Scale in Google s Software-Defined WAN B4 and After: Managing Hierarhy, Partitioning, and Asymmetry for Availability and Sale in Google s Software-Defined WAN Chi-Yao Hong Subhasree Mandal Mohammad Al-Fares Min Zhu Rihard Alimi Kondapa Naidu

More information

Divide-and-conquer algorithms 1

Divide-and-conquer algorithms 1 * 1 Multipliation Divide-and-onquer algorithms 1 The mathematiian Gauss one notied that although the produt of two omplex numbers seems to! involve four real-number multipliations it an in fat be done

More information

A Support-Based Algorithm for the Bi-Objective Pareto Constraint

A Support-Based Algorithm for the Bi-Objective Pareto Constraint Proeedings of the Twenty-Eighth AAAI Conferene on Artifiial Intelligene A Support-Based Algorithm for the Bi-Ojetive Pareto Constraint Renaud Hartert and Pierre Shaus UCLouvain, ICTEAM, Plae Sainte Bare

More information

PERSISTENT NAMING FOR PARAMETRIC MODELS

PERSISTENT NAMING FOR PARAMETRIC MODELS PERSISTENT NAMING FOR PARAMETRIC MODELS Dago AGBODAN, David MARCHEIX and Guy PIERRA Laboratory of Applied Computer Siene (LISI) National Shool of Engineers in Mehanis and Aeronautis (ENSMA) Téléport 2

More information

The Tofu Interconnect D

The Tofu Interconnect D 2018 IEEE International Conferene on Cluster Computing The Tofu Interonnet D Yuihiro Ajima, Takahiro Kawashima, Takayuki Okamoto, Naoyuki Shida, Kouihi Hirai, Toshiyuki Shimizu Next Generation Tehnial

More information

High-level synthesis under I/O Timing and Memory constraints

High-level synthesis under I/O Timing and Memory constraints Highlevel synthesis under I/O Timing and Memory onstraints Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eri Senn, Eri Martin To ite this version: Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eri Senn,

More information

Chapter 2: Introduction to Maple V

Chapter 2: Introduction to Maple V Chapter 2: Introdution to Maple V 2-1 Working with Maple Worksheets Try It! (p. 15) Start a Maple session with an empty worksheet. The name of the worksheet should be Untitled (1). Use one of the standard

More information

2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media,

2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any urrent or future media, inluding reprinting/republishing this material for advertising

More information

Automatic Generation of Transaction-Level Models for Rapid Design Space Exploration

Automatic Generation of Transaction-Level Models for Rapid Design Space Exploration Automati Generation of Transation-Level Models for Rapid Design Spae Exploration Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rainer Dömer and Daniel D. Gajski Center for Embedded Computer Systems University

More information

A Unified Subdivision Scheme for Polygonal Modeling

A Unified Subdivision Scheme for Polygonal Modeling EUROGRAPHICS 2 / A. Chalmers and T.-M. Rhyne (Guest Editors) Volume 2 (2), Number 3 A Unified Subdivision Sheme for Polygonal Modeling Jérôme Maillot Jos Stam Alias Wavefront Alias Wavefront 2 King St.

More information

Parallel Block-Layered Nonbinary QC-LDPC Decoding on GPU

Parallel Block-Layered Nonbinary QC-LDPC Decoding on GPU Parallel Blok-Layered Nonbinary QC-LDPC Deoding on GPU Huyen Thi Pham, Sabooh Ajaz and Hanho Lee Department of Information and Communiation Engineering, Inha University, Inheon, 42-751, Korea Abstrat This

More information

Bayesian Belief Networks for Data Mining. Harald Steck and Volker Tresp. Siemens AG, Corporate Technology. Information and Communications

Bayesian Belief Networks for Data Mining. Harald Steck and Volker Tresp. Siemens AG, Corporate Technology. Information and Communications Bayesian Belief Networks for Data Mining Harald Stek and Volker Tresp Siemens AG, Corporate Tehnology Information and Communiations 81730 Munih, Germany fharald.stek, Volker.Trespg@mhp.siemens.de Abstrat

More information

A Support-Based Algorithm for the Bi-Objective Pareto Constraint

A Support-Based Algorithm for the Bi-Objective Pareto Constraint A Support-Based Algorithm for the Bi-Ojetive Pareto Constraint Renaud Hartert and Pierre Shaus UCLouvain, ICTEAM, Plae Sainte Bare 2, 1348 Louvain-la-Neuve, Belgium {renaud.hartert, pierre.shaus,}@ulouvain.e

More information

TMIX: Temporal Model for Indexing XML Documents

TMIX: Temporal Model for Indexing XML Documents TMIX: Temporal Model for Indexing XML Douments Rasha Bin-Thalab Department of Information System Faulty of omputers and Information Cairo University, Egypt azi_z30@yahoo.om Neamat El-Tazi Department of

More information

Acoustic Links. Maximizing Channel Utilization for Underwater

Acoustic Links. Maximizing Channel Utilization for Underwater Maximizing Channel Utilization for Underwater Aousti Links Albert F Hairris III Davide G. B. Meneghetti Adihele Zorzi Department of Information Engineering University of Padova, Italy Email: {harris,davide.meneghetti,zorzi}@dei.unipd.it

More information