EECS150 - Digital Design Lecture 6 - Logic Simulation. Encoder Example
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1 EECS150 - Digital Design Lecture 6 - Logic Simulation Feb 7, 2013 John Wawrzynek Spring 2013 EECS150 - Lec06-sim Page 1 Encoder Example What is y if x == 4 b1111? : encode if (x == 4'b0001) y = 2'b00; else if (x == 4'b0010) y = 2'b01; else if (x == 4'b0100) y = 2'b10; else if (x == 4'b1000) y = 2'b11; else y = 2'bxx; Spring 2013 EECS150 - Lec06-sim Page 2
2 Encoder Example (cont.) What is y if x == 4 b1111? : encode case (x) 4 b0001: y = 2'b00; 4 b0010: y = 2'b01; 4'b0100: y = 2'b10; 4'b1000: y = 2'b11; default: y = 2'bxx; case Spring 2013 EECS150 - Lec06-sim Page 3 Encoder Example (cont.) If you can guarantee that only one 1 appears in the input, then simpler logic can be generated: : encode if (x[0]) y = 2'b00; else if (x[1]) y = 2'b01; else if (x[2]) y = 2'b10; else if (x[3]) y = 2'b11; else y = 2'bxx; If the input applied has more than one 1, then this version functions as a priority encoder. The least significant 1 gets priority (the more significant 1 s are ignored). Again the circuit will be simplified when possible. Spring 2013 EECS150 - Lec06-sim Page 4
3 EECS150 Design Methodology Hierarchically define structure and/or behavior of circuit. HDL Specification Simulation Functional verification. Synthesis Maps specification to resources of implementation platform (FPGA for us). Let s look at the other branch. Spring 2013 EECS150 - Lec06-sim Page 5 Design Verification Industrial design teams sp a large percentage of the design time on design verification: Removing functional bugs, messaging the design to meet performance, cost, and power constraints. Particularly important for IC design, less so for FPGAs. A variety of tools and strategies are employed. Simulation: software that interprets the design description and mimics signal behavior and timing (and power consumption). Simulation provides better controllability and observability over real hardware. Saves on wasted development time and money. Emulation: hardware platform (usually FPGAs) are used to mimic behavior of another system. Fast simulation. Static Analysis: tools examines circuit structure and reports on expected performance, power, or compares alternative design representations looking for differences. Spring 2013 EECS150 - Lec06-sim Page 6
4 Simulation Verilog/VHDL simulators use 4 signals values: 0, 1, X (unknown), Z (undriven) Simulation engine algorithm typically discrete event simulation ModelSim: waveform viewer, GUI. Spring 2013 EECS150 - Lec06-sim Page 7 Discrete Event Simulation Engine A time-ordered list of events is maintained Event: a value-change scheduled to occur at a given time All events for a given time are kept together The scheduler removes events for a given time propagates values, executes models, and creates new events... all the events for time tj time-ordered event list ti tj tk tn remove current events Gate Outputs updates Scheduler looks at Network Connections (fanouts) schedules new event executes Gate Models Slide from Thomas. The Verilog Hardware Description Language, By Thomas and Moorby, Kluwer Academic Publishers Spring 2013 EECS150 - Lec06-sim Page 8
5 Simulation Testing Strategies Unit Testing: Large systems are often too complex to test all at once, so an bottom-up hierarchical approach. Sub-modules are tested in isolation. Combinational Logic blocks: when practical, exhaustive testing. Otherwise a combination of random and directed tests. Finite state machines: test every possible transition and output. Processors: use software to expose bugs. In all cases, the simulated output values are checked against the expected values. Expected values are derived through a variety of means: HDL behavior model running along side the design under test precomputed inputs and outputs (vectors) co-simulation. Ex: C-language model runs along side ModelSim Spring 2013 EECS150 - Lec06-sim Page 9 module testmux; reg a, b, s; wire f; reg expected; Testbench Top-level modules written specifically to test other modules. mux2 mymux (.select(s),.in0(a),.in1(b),.out(f)); s=0; a=0; b=1; expected=0; #10 a=1; b=0; expected=1; #10 s=1; a=0; b=1; expected=1; $monitor( Generally no ports. Assignments used to set inputs. "select=%b in0=%b in1=%b out=%b, expected out=%b time=%d", s, a, b, f, expected, $time); module // testmux Usually never synthesized to circuits. Therefore free to use simulation only language constructs. Instantiation of DUT (device under test). Initial block similar to always block without a trigger. It triggers once automatically at the ning of simulation. (Also supported on FPGAs). #n used to advance time in simulation. Delays some action by a number of simulation time units. Note multiple blocks. $monitor triggers whenever any of its inputs change. Ss output to console. A variety of other system functions exist for displaying output and controlling the simulation. Most simulators also include a Spring 2013 EECS150 - Lec06-sim way to view waveforms of a Page 10 set of signals.
6 Mux4 Testbench module testmux4; Declaration and ization all at once. reg [5:0] count = 6 b000000; Generally not available in synthesis. reg a, b, c, d, expected; reg [1:0] S; DUT instantiation wire f; mux4 mymux (.select(s),.in0(a),.in1(b),.in2(c),.in3(d),.out(f)); repeat(64) {S, d, c, b, a} = count[5:0]; $stop; module case (S) 2 b00: expected = a; 2 b01: expected = b; 2 b10: expected = c; 2 b11: expected = d; case // case(s) Enumerate all possible input patterns. #8 $strobe( "select=%b in0=%b in1=%b in2=%b in3=%b out=%b, expected=%b time=%d", S, a, b, c, d, f, expected, $time); #2 count = count + 1 b1; Wait a bit, then bump count. Apply pattern to DUT Behavioral model of mux4 $strobe displays data at a selected time. That time is just before simulation time is advanced (after all other events). Delay to allow mux outputs to stabilize. Here we assume mux delay < 2ns. Alternative to $strobe in this case, #8 if (f!= expected) $display( Mismatch:...); Spring 2013 EECS150 - Lec06-sim Page 11 module testfsm; reg in; wire out; reg clk=0, rst; reg expect; DUT instantiation FSM1 myfsm (.out(out),.in(in),.clk(clk),.rst(rst)); always #5 clk = clk; rst=1; #10 in=0; rst=0; expect=0; #10 in=1; rst=0; expect=0; #10 in=0; rst=0; expect=0; #10 in=1; rst=0; expect=0; #10 in=1; rst=0; expect=1; #10 in=1; rst=0; expect=1; #10 in=0; rst=0; expect=0; #10 $stop; FSM Testbench Example Test all arcs. 100MHz clk signal start in IDLE self-loop transition to S0 transition to IDLE transition to S0 transition to S1 self-loop transition to IDLE Note: Input changes are forced to occur on negative edge of clock. always Strobe output occurs 1ns before rising edge of clock. #4 $strobe($time," in=%b, rst=%b, expect=%b out=%b", in, rst, expect, out); #6 ; Debug is easier if you have access to state value also. module Spring 2013 Either 1) bring out to EECS150 ports, - or Lec06-sim 2) use waveform viewer. Page 12
7 Final Words (for now) on Simulation Testing is not always fun, but you should view it as part of the design process. Untested potentially buggy designs are a dime-a-dozen. Verified designs have real value. Devising a test strategy is an integral part of the the design process. It shows that you have your head around the design. It should not be an afterthought. Spring 2013 EECS150 - Lec06-sim Page 13
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