Quick Introduction to SystemVerilog: Sequental Logic


 Dylan Neal
 10 months ago
 Views:
Transcription
1 ! Quick Introduction to SystemVerilog: Sequental Logic Lecture L Advanced Digital Design ECE Department Many elements Don Thomas, 24, used with permission with credit to G. Larson
2 Today Quick synopsis of Finite State Machines (FSM) Moore, Mealy Design process SystemVerilog for a Flip flop SystemVerilog for a FSM Exercise: Design, implement and synthesize a FSM 2
3 Designing FSMs: Step State Transition Diagrams represent FSMs at a high level of abstraction. Each state is represented by a circle A/, C/ 2. Each state is labeled with a symbolic name. An output value is specified for each state Reset B/ 3. A directed edge from state Sx to Sy indicates a potential transition 5. Whenever reset is asserted, the FSM transitions to a special initial state Each transition is labeled with input values that, should they be present, would cause the state to change from Sx to Sy 4. One of the state transitions occurs for each clock event 824 L9 3
4 What does it mean? E.g. bit input, bit output, 3state FSM  trace the execution for input sequence after Reset  What will the output be? The next state? Reset A/, B/ C/ clock event State A A B B B C Output Input X Reset 824 L9 4
5 State Transition Diagram Example Things to note  Output is a function of state not input out = (state == B)? : ;  Next state is a function of current state and input Reset if (state == B && input == ) then next state is B else next state is C A/, B/ C/ An FSM is a 5tuple  A set of states here {A, B, C}  A set of allowable inputs ( alphabet ) here {, }  A set of allowable outputs ( alphabet ) {, }  A next state function here a combinational fn of (state, input)  An output function here a combinational fn of (state) 824 L9 5
6 Reset Putting it in context A/, C/ inputs Next State Generator (comb logic) Current State Register Output Generator (comb logic) outputs B/ clock Let CS be current state and NS be next state if (Reset) NS=A else if (CS==A) if (Input==) NS=A else NS=B else if (CS==B) if (Input==) NS=C else NS=B else if (CS==C) NS=A 2bit state register for example means A means B means C don t care Hmm, can you imagine describing these as always_comb blocks? Let CS be current state out = (CS == B)? : ; 824 L9 6
7 Moore vs. Mealy Machines At the start of this lecture  We said a machine s output was a function of the state Actually Two different types of FSMs  Moore machines: output = a fn of only state (We just did this)  Mealy machines: output = a fn of the state and the inputs Mealy machines = Moore + wire the only difference inputs Next State Generator (comb logic) Current State Register Output Generator (comb logic) outputs clock 824 L9 7
8 Mealy State Diagram and Table The state transition arcs must show the inputs/outputs Output is now a function of both state & input  If you re in state A the output is if the input is, and if the input is  If you re in state B, the output is different from above Reset A / / /,/ / C input/output / B Present state Next State X = X = Output X = X = A B C A C A B B A 824 L9 8
9 Mealy Output Notation Mealy outputs are a function of state and inputs Reset A In Out X Placing a truth table in each state is a bit clumsy  Though less confusing for new students As the transitions already have input specifications, we reuse them to describe outputs B In X Out C In Out X BE CAREFUL: Mealy notation is confusing! You don t have to actually take the transition for the output to occur 824 L9 9
10 Example: Series Recognizer Let s do one example in both Moore and Mealy  Want a series recognizer FSM that outputs a every time it detects sequence in input stream INPUT OUTPUT Moore State Transition Diagram Mealy State Transition Diagram R s? / s / s / R / s? / / s / 824 L9
11 Example: The Timing Is Different! INPUT OUTPUT INPUT OUTPUT Moore State Transition Diagram Mealy State Transition Diagram R s? / s / s / R / s? / / s / 824 L9
12 Example: Essential differences Moore  Need a state for reset that is also the last wasn t  Need a state for the last input was  Need a state for I just saw a after a I recognized a pattern Mealy  Need a state for reset which is also the last wasn t  Need a state for the last input was  Transitions get labeled with correct outputs, not the states  Notice that the start state is target of 2 transitions with different output values this is how we save that extra state  Outputs appear at different times wrt Moore machines The example is small  But you see the Mealy approach is different, results in one less state 824 L9 2
13 To infer a flipflop Flipflops are edgetriggered need to with posedge or negedge side effect every variable on the lefthand side assigned with a <= will be an edge triggered flipflop (or vector of flipflops) Some combinational logic can be specified in certain places module Dff (output logic Q, input clk, d, resetn); clk, negedge resetn) if (~resetn) Q <= ; else Q <= d; endmodule What happens on the clock edge is inferred it s the last (default) action. The assignment is made to a logic (or bit ) variable, not a reg as in old Verilog. Synthesis infers an FF Q, d, clk, and resetn are not keywords <= needed for synthesis and simulation SVbook 3. 3
14 New SystemVerilog Constructs A new flavor of always statement  clk) ;  this statement models a flipflop or register  this statement will synthesize to a flipflop or register clk) means to wait for the specified change on the listed signal posedge to negedge to module DFF (input logic d, clk, output logic q); clk) q <= d; endmodule: DFF Current state (Now) Next State (after clk) Clk D Q Q + X X X X X X 824 L2 4
15 Big Idea: Concurrent assignment What about that <=???  Called nonblocking assignment Sometimes called concurrent, buffered or delayed assignment Use it to assign to a state value, like a flipflop or register output module DFF (input logic d, clk, output logic q); clk) q <= d; endmodule: DFF <= is not less than or equal!! Why a new assignment type?  This models how an edge triggered flipflop works All clocktriggered state updates in the design happen instantaneously, at the same time, indivisibly, you can t tell one happened before any other If your design has K flipflops, then all K assignments happen instantaneously in simulation After all, in the physical hardware, the same clock triggers all K flipflops and they change concurrently (and instantaneously)! 824 L2 5
16 What about reset? Asynchronous reset  happens anytime rstn becomes Trace behavior  anytime reset changes to, set q to  while reset remains, if the clock edge occurs, q still remains  when reset changes to, q remains until the next clock event module DFF_rst (input logic d, clk, rstn output logic q); clk, negedge rstn) if (~rstn) q <= ; else q <= d; endmodule: DFF_rst If reset asserted This is a list of what the always_ff block is sensitive to This is how to describe a flipflop. Just do it this way! Copy it!!
17 How reset works reset is generally asynchronous... module Dff (output logic Q, input logic clk, d, resetn); clk, negedge resetn) if (~resetn) Q <= ; else Q <= d; endmodule : Dff... but could be rising edge module Dff (output logic Q, input logic clk, d, reset); clk, posedge reset) if (reset) Q <= ; else Q <= d; endmodule : Dff 824 L2 7
18 Finite State Machines Defined formally by  Set of states, including reset  set of input combinations not necessarily all 2 n are possible due to don tcares  set of output combinations not necessarily all 2 n are possible  next state (δ) and output (λ) combinational functions  clock event (or clock domain)  reset signal R / A B / Legend s s i/a,b inputs next state logic / / C D Q D Q output logic x/ outputs MOC: starting in the reset state, the clock event causes the system to change to another (or same) state as defined by the δ function 824 L2 8
19 FSM in SystemVerilog Next State Logic Output Logic X Q D D Q Q Z Clk Q Q Q' D D Clk Q Q Q clock reset_l Two always_comb blocks (or continuous assigns)  one for the combinational next state logic  one for the output logic We ll have another always_ff block for the D flipflops 824 L2 9
20 Explicit FSM Style module myfsm2 (input logic clk, rstn, x, output logic z); logic [:] ns, cs; clk, negedge rstn) if (~rstn) cs <= ; else cs <= ns; always_comb begin ns[] = cs[] & x cs[] & x; ns[] = cs[] & x ~cs[] & x; end assign z = cs[] & cs[]; endmodule: myfsm2 Called explicit FSM style because everything is explicitly defined: state register, output logic, next state logic, and state assignment Done here as 3 blocks  The sequential part: generates current state (cs) from the next state (ns) synchronously  The next state generator: combinational logic to create the next state inputs (D, D) from the current state and input (x)  The output generator: combinational logic to create the output (z) from the current state
21 Where does clock come from? module clock (output logic clk); initial begin clk = ; forever # clk = ~clk; end endmodule: clock clk time = clk has value one time = clk = zero time = 2 clk = one In HW, the clock is driven from outside of the design A clock module  Used in simulation  Initialization to one (or zero) It will have this value when simulation starts (not x!)  Execution forever loop just keeps executing the statement # says to wait time units Every units clk gets ~clk Someplace else in the design must have a $finish!! 824 L2 2
22 enum enumerate for state encoding enum enumerate statement, similar to what is found in programming languages Below, 2bit logic variables state and nextstate are defined A set of symbols are defined: ZERO, ONE, TWO, and THREE The bit patterns that represent these symbols are defined shown below These are strongly typed Can leave out type and size (integers with values starting at assumed) enum can also be typedef ed keyword labels and values enum logic [:] {ZERO = 2'd, ONE = 2'd, TWO = 2'd2, THREE = 2'd3} state, nextstate; type and size SVbook 3.4. declared variables 22
23 Style Points What are the logic components? module explicitfsm (output logic a, b, input ck, r_l, i); enum logic [:] {A=2'b, B=2'b, C=2'b} state, nextstate; One way to do state assignment Why set a to and later back to? but don t do that with b? Why ~r_l instead of switching the sense of the ifelse? always_comb begin a = 'b; b = nextstate == A; if ((state == C) && i) a = 'b; end always_comb case (state) A: nextstate = (i)? B : A; B: nextstate = C; C: nextstate = (~i): A : C; default: nextstate = A; endcase ck, negedge r_l) if (~r_l) state <= A; else state <= nextstate; endmodule: explicitfsm Why have a default? 23
24 Other organizations module explicitfsm (output logic a, b, input ck, r_l, i); enum logic [:] {A=2'b, B=2'b, C=2'b} state, nextstate; always_comb begin a = 'b; b = nextstate == A; if ((state == C) && i) a = 'b; end always_comb case (state) A: nextstate = (i)? B : A; B: nextstate = C; C: nextstate = (~i): A : C; default: nextstate = A; endcase ck, negedge r_l) if (~r_l) state <= A; else state <= nextstate; endmodule: explicitfsm module explicitfsm (output logic a, b, input ck, r_l, i); enum logic [:] {A=2'b, B=2'b, C=2'b} state, nextstate; always_comb begin a = 'b; b = nextstate == A; if ((state == C) && i) a = 'b; end ck, negedge r_l) if (~r_l) state <= A; else case (state) A: state <= (i)? B : A; B: state <= C; C: state <= (~i): A : C; default: state <= A; endcase endmodule: explicitfsm This combines state and nextstate together. OKAY?? hmm, needs to change too. Why? 24
25 Combining parts of an explicit fsm Potential problem combining the output logic with the state update OK with a Mealy machine? OK with a Moore machine? module explicitfsm (output logic a, b, input ck, r_l, i); enum logic [:] {A=2'b, B=2'b, C=2'b} state, nextstate; always_comb begin a = 'b; b = nextstate == A; if ((state == C) && i) a = 'b; end always_comb case (state) A: nextstate = (i)? B : A; B: nextstate = C; C: nextstate = (~i): A : C; default: nextstate = A; endcase ck, negedge r_l) if (~r_l) state <= A; else state <= nextstate; endmodule: explicitfsm 25
26 Models of Computation R / A B A B C F / Legend s s i/a,b / x/ C / inputs next state logic D Q output logic outputs D Q Combinational Logic Where we ve been What are the assumptions about how new values are generated in each of these? specifically combinational logic and STDs Can think of this as the beginnings of a behavioral hierarchy What s next up? 26
Testbenches for Sequential Circuits... also, Components
! Testbenches for Sequential Circuits... also, Components Lecture L04 18545 Advanced Digital Design ECE Department Many elements Don Thomas, 2014, used with permission with credit to G. Larson State Transition
More informationLast Lecture: Divide by 3 FSM
Last Lecture: Divide by 3 FSM Output should be 1 every 3 clock cycles S2 S0 S1 The double circle indicates the reset state Slide derived from slides by Harris & Harris from their book 1 Finite State Machines
More informationFSM and Efficient Synthesizable FSM Design using Verilog
FSM and Efficient Synthesizable FSM Design using Verilog Introduction There are many ways to code FSMs including many very poor ways to code FSMs. This lecture offers guidelines for doing efficient coding,
More informationECE 4514 Digital Design II. Spring Lecture 15: FSMbased Control
ECE 4514 Digital Design II Lecture 15: FSMbased Control A Design Lecture Overview Finite State Machines Verilog Mapping: one, two, three always blocks State Encoding Userdefined or tooldefined State
More informationSequential Logic Design
Sequential Logic Design Design of Digital Circuits 2017 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan) http://www.syssec.ethz.ch/education/digitaltechnik_17 Adapted
More informationEE178 Lecture Verilog FSM Examples. Eric Crabill SJSU / Xilinx Fall 2007
EE178 Lecture Verilog FSM Examples Eric Crabill SJSU / Xilinx Fall 2007 In Realtime Objectoriented Modeling, Bran Selic and Garth Gullekson view a state machine as: A set of input events A set of output
More informationBlocking(=) vs Nonblocking (<=) Assignment. Lecture 3: Modeling Sequential Logic in Verilog HDL. Procedural assignments
Blocking(=) vs Nonblocking (
More informationCSE 502: Computer Architecture
CSE 502: Computer Architecture SystemVerilog More Resources Cannot cover everything in one day You will likely need to look up reference material: SystemVerilog for VHDL Users: http://www.systemverilog.org/techpapers/date04_systemverilog.pdf
More informationGraduate Institute of Electronics Engineering, NTU. Lecturer: Chihhao Chao Date:
Design of Datapath Controllers and Sequential Logic Lecturer: Date: 2009.03.18 ACCESS IC LAB Sequential Circuit Model & Timing Parameters ACCESS IC LAB Combinational Logic Review Combinational logic circuits
More informationECE 2300 Digital Logic & Computer Organization. More Verilog Finite State Machines
ECE 2300 Digital Logic & Computer Organization Spring 2017 More Verilog Finite State Machines Lecture 8: 1 Announcements 1 st batch of (raw) quiz scores released on CMS Solutions to HW 13 released on
More informationBuilding Bigger Systems: Interfacing
! Building Bigger Systems: Interfacing Lecture L07 18545 Advanced Digital Design ECE Department Many elements Don Thomas, 2014, used with permission with credit to G. Larson Basic Principles Reading:
More informationECEN 468 Advanced Logic Design
ECEN 468 Advanced Logic Design Lecture 28: Synthesis of Language Constructs Synthesis of Nets v An explicitly declared net may be eliminated in synthesis v Primary input and output (ports) are always retained
More informationModeling of Finite State Machines. Debdeep Mukhopadhyay
Modeling of Finite State Machines Debdeep Mukhopadhyay Definition 5 Tuple: (Q,Σ,δ,q 0,F) Q: Finite set of states Σ: Finite set of alphabets δ: Transition function QχΣ Q q 0 is the start state F is a set
More informationWriting Circuit Descriptions 8
8 Writing Circuit Descriptions 8 You can write many logically equivalent descriptions in Verilog to describe a circuit design. However, some descriptions are more efficient than others in terms of the
More informationEECS150  Digital Design Lecture 5  Verilog Logic Synthesis
EECS150  Digital Design Lecture 5  Verilog Logic Synthesis Jan 31, 2012 John Wawrzynek Spring 2012 EECS150  Lec05verilog_synth Page 1 Outline Quick review of essentials of state elements Finite State
More informationA short introduction to SystemVerilog. For those who know VHDL We aim for synthesis
A short introduction to SystemVerilog For those who know VHDL We aim for synthesis 1 Verilog & SystemVerilog 1984 Verilog invented, Clike syntax First standard Verilog 95 Extra features Verilog 2001 A
More informationDigital Integrated Circuits
Digital Integrated Circuits Lecture 3 Jaeyong Chung SystemonChips (SoC) Laboratory Incheon National University GENERAL MODEL OF MEALY MACHINE Chung EPC6055 2 GENERAL MODEL OF MOORE MACHINE Chung EPC6055
More informationGraduate Institute of Electronics Engineering, NTU Design of Datapath Controllers
Design of Datapath Controllers Lecturer: WeinTsung Shen Date: 2005.04.01 ACCESS IC LAB Outline Sequential Circuit Model Finite State Machines Useful Modeling Techniques pp. 2 Model of Sequential Circuits
More informationLecture 15: System Modeling and Verilog
Lecture 15: System Modeling and Verilog Slides courtesy of Deming Chen Intro. VLSI System Design Outline Outline Modeling Digital Systems Introduction to Verilog HDL Use of Verilog HDL in Synthesis Reading
More informationThe Verilog Language COMS W Prof. Stephen A. Edwards Fall 2002 Columbia University Department of Computer Science
The Verilog Language COMS W499502 Prof. Stephen A. Edwards Fall 2002 Columbia University Department of Computer Science The Verilog Language Originally a modeling language for a very efficient eventdriven
More informationFinite State Machines
Finite State Machines Design methodology for sequential logic  identify distinct states  create state transition diagram  choose state encoding  write combinational Verilog for nextstate logic
More informationGeneral FSM design procedure
Sequential logic examples Basic design approach: a 4step design process Hardware description languages and finite state machines Implementation examples and case studies finitestring pattern recognizer
More informationTSEA44: Computer hardware a system on a chip
TSEA44: Computer hardware a system on a chip Lecture 2: A short introduction to SystemVerilog (System)Verilog 20161102 2 Assume background knowledge of VHDL and logic design Focus on coding for synthesis
More informationDIGITAL SYSTEM DESIGN
DIGITAL SYSTEM DESIGN Prepared By: Engr. Yousaf Hameed Lab Engineer BASIC ELECTRICAL & DIGITAL SYSTEMS LAB DEPARTMENT OF ELECTRICAL ENGINEERING Digital System Design 1 Name: Registration No: Roll No: Semester:
More informationControl in Digital Systems
CONTROL CIRCUITS Control in Digital Systems Three primary components of digital systems Datapath (does the work) Control (manager, controller) Memory (storage) B. Baas 256 Control in Digital Systems Control
More informationVHDL: RTL Synthesis Basics. 1 of 59
VHDL: RTL Synthesis Basics 1 of 59 Goals To learn the basics of RTL synthesis. To be able to synthesize a digital system, given its VHDL model. To be able to relate VHDL code to its synthesized output.
More informationEECS 470 Lab 3. SystemVerilog Style Guide. Department of Electrical Engineering and Computer Science College of Engineering University of Michigan
EECS 470 Lab 3 SystemVerilog Style Guide Department of Electrical Engineering and Computer Science College of Engineering University of Michigan Thursday, 18 th January 2018 (University of Michigan) Lab
More informationTechniques for Digital Systems Lab. Verilog HDL. Tajana Simunic Rosing. Source: Eric Crabill, Xilinx
CSE140L: Components and Design Techniques for Digital Systems Lab Verilog HDL Tajana Simunic Rosing Source: Eric Crabill, Xilinx 1 More complex behavioral model module life (n0, n1, n2, n3, n4, n5, n6,
More informationCSE140L: Components and Design Techniques for Digital Systems Lab. FSMs. Instructor: Mohsen Imani. Slides from Tajana Simunic Rosing
CSE4L: Components and Design Techniques for Digital Systems La FSMs Instructor: Mohsen Imani Slides from Tajana Simunic Rosing Source: Vahid, Katz Flipflops Hardware Description Languages and Sequential
More informationWhy Should I Learn This Language? VLSI HDL. Verilog2
Verilog Why Should I Learn This Language? VLSI HDL Verilog2 Different Levels of Abstraction Algorithmic the function of the system RTL the data flow the control signals the storage element and clock Gate
More informationFSM Components. FSM Description. HDL Coding Methods. Chapter 7: HDL Coding Techniques
FSM Components XST features: Specific inference capabilities for synchronous Finite State Machine (FSM) components. Builtin FSM encoding strategies to accommodate your optimization goals. You may also
More informationGeneral FSM design procedure
Sequential logic examples Basic design approach: a 4step design process Hardware description languages and finite state machines Implementation examples and case studies finitestring pattern recognizer
More informationVerilog Execution Semantics
System Verilog (SV) is a parallel, hardware description language. SV differs from procedural languages such as C in that it models concurrency in digital logic. Logic gates operate in parallel, but software
More informationParallel versus serial execution
Parallel versus serial execution F assign statements are implicitly parallel Ì = means continuous assignment Ì Example assign E = A & D; assign A = B & C; Ì A and E change if B changes F always blocks
More informationVerilog Sequential Logic. Verilog for Synthesis Rev C (module 3 and 4)
Verilog Sequential Logic Verilog for Synthesis Rev C (module 3 and 4) Jim Duckworth, WPI 1 Sequential Logic Module 3 Latches and FlipFlops Implemented by using signals in always statements with edgetriggered
More informationCMPE 415 Verilog CaseStatement Based State Machines II
Department of Computer Science and Electrical Engineering CMPE 415 Verilog CaseStatement Based State Machines II Prof. Ryan Robucci Finite State Machine with Datapath A very common framework being described
More information(System)Verilog Tutorial Aleksandar Milenković
(System)Verilog Tutorial Aleksandar Milenković The LaCASA Laboratory Electrical and Computer Engineering Department The University of Alabama in Huntsville Email: milenka@ece.uah.edu Web: http://www.ece.uah.edu/~milenka
More informationStuart Sutherland, Sutherland HDL, Inc.
SystemVerilog Design: User Experience Defines MultiTool, MultiVendor Language Working Set Ways Design Engineers Can Benefit from the Use of SystemVerilog Assertions Stuart Sutherland, Sutherland HDL,
More informationLab 7 (Sections 300, 301 and 302) Prelab: Introduction to Verilog
Lab 7 (Sections 300, 301 and 302) Prelab: Introduction to Verilog Name: Sign the following statement: On my honor, as an Aggie, I have neither given nor received unauthorized aid on this academic work
More information271/471 Verilog Tutorial
271/471 Verilog Tutorial Prof. Scott Hauck, last revised 9/15/14 Introduction The following tutorial is inted to get you going quickly in circuit design in Verilog. It isn t a comprehensive guide to System
More information!== vs.!= and === vs. ==
!== vs.!= and === vs. == In SystemVerilog, logic is a 4state signal type with values 0, 1, X, Z. If a signal is never assigned to, ModelSim will assume that has an xxx xxx value. This means if you do
More informationRTL Design (Using ASM/SM Chart)
Digital Circuit Design and Language RTL Design (Using ASM/SM Chart) Chang, Ik Joon Kyunghee University Process of Logic Simulation and Synthesis Design Entry HDL Description Logic Simulation Functional
More informationSequential Logic Implementation. Mealy vs. Moore Machines. Specifying Outputs for a Mealy Machine. Specifying Outputs for a Moore Machine
uential Logic Implementation! Models for representing sequential circuits " bstraction of sequential elements " Finite state machines and their state diagrams " Inputs/ " Mealy, Moore, and synchronous
More informationL5: Simple Sequential Circuits and Verilog
L5: Simple Sequential Circuits and Verilog Courtesy of Rex Min. Used with permission. 1 Key Points from L4 (Sequential Blocks) Classification: Latch: level sensitive (positive latch passes input to output
More informationECE 353 Lab 4. Verilog Review. Professor Daniel Holcomb With material by Professor Moritz and Kundu UMass Amherst Fall 2016
ECE 353 Lab 4 Verilog Review Professor Daniel Holcomb With material by Professor Moritz and Kundu UMass Amherst Fall 2016 Recall What You Will Do Design and implement a serial MIDI receiver Hardware in
More informationCS6710 Tool Suite. Verilog is the Key Tool
CS6710 Tool Suite VerilogXL Behavioral Verilog Your Library Cadence SOC Encounter Synopsys Synthesis Structural Verilog Circuit Layout CSI VerilogXL AutoRouter Cadence Virtuoso Layout LVS LayoutXL Cadence
More informationEECS150  Digital Design Lecture 6  Logic Simulation
EECS150  Digital Design Lecture 6  Logic Simulation Sep. 17, 013 Prof. Ronald Fearing Electrical Engineering and Computer Sciences University of California, Berkeley (slides courtesy of Prof. John Wawrzynek)
More informationSequential Logic. Reminder: Lab #2 due Thursday Fall 2016 Lecture 4
Sequential Logic Digital state: the DRegister Timing constraints for DRegisters Specifying registers in Verilog Blocking and nonblocking assignments Examples Reminder: Lab #2 due Thursday 1 Use Explicit
More informationModeling Synchronous Logic Circuits. Debdeep Mukhopadhyay IIT Madras
Modeling Synchronous Logic Circuits Debdeep Mukhopadhyay IIT Madras Basic Sequential Circuits A combinational circuit produces output solely depending on the current input. But a sequential circuit remembers
More informationDesigning Safe Verilog State Machines with Synplify
Designing Safe Verilog State Machines with Synplify Introduction One of the strengths of Synplify is the Finite State Machine compiler. This is a powerful feature that not only has the ability to automatically
More informationVerilog Nonblocking Assignments with Delays  Myths & Mysteries
Verilog Nonblocking Assignments with Delays  Myths & Mysteries Clifford E. Cummings, Inc. cliffc@sunburstdesign.com www.sunburstdesign.com 2 of 67 Agenda IEEE 1364 reference model & event queue Review
More informationECEU530. Homework 4 due Wednesday Oct 25. ECE U530 Digital Hardware Synthesis. VHDL for Synthesis with Xilinx. Schedule
EEU530 EE U530 igital Hardware Synthesis Lecture 11: Prof. Miriam Leeser mel@coe.neu.edu October 18, 2005 Sequential Logic in VHL Finite State Machines in VHL Project proposals due now HW 4 due Wednesday,
More informationECE 353 Lab 4. Verilog Review. Professor Daniel Holcomb UMass Amherst Fall 2017
ECE 353 Lab 4 Verilog Review Professor Daniel Holcomb UMass Amherst Fall 2017 What You Will Do In Lab 4 Design and implement a serial MIDI receiver Hardware in an Altera Complex Programmable Logic Device
More informationDesign of Digital Circuits ( L) ETH Zürich, Spring 2017
Name: Student ID: Final Examination Design of Digital Circuits (252002800L) ETH Zürich, Spring 2017 Professors Onur Mutlu and Srdjan Capkun Problem 1 (70 Points): Problem 2 (50 Points): Problem 3 (40
More informationMemory Controller. System Integration Issues. Encoding numbers 1GB RAM FSM. Communicating FSMs Clocking, theory and practice. Combinational Logic
Memory Controller System Integration Issues Communicating FSMs Clocking, theory and practice Encoding numbers 0 1 0 4 2 3 1 2 1GB RAM FSM Clock D Current Combinational Logic Next Input Output always @(posedge
More informationStandard Gotchas Subtleties in the Verilog and SystemVerilog Standards That Every Engineer Should Know
Standard Gotchas Subtleties in the Verilog and SystemVerilog Standards That Every Engineer Should Know Stuart Sutherland Sutherland HDL, Inc. stuart@sutherlandhdl.com Don Mills Microchip Technology don.mills@microchip.com
More informationEECS150  Digital Design Lecture 4  Verilog Introduction. Outline
EECS150  Digital Design Lecture 4  Verilog Introduction Feb 3, 2009 John Wawrzynek Spring 2009 EECS150  Lec05Verilog Page 1 Outline Background and History of Hardware Description Brief Introduction
More informationThis Lecture. Some components (useful for the homework) Verilog HDL (will continue next lecture)
Last Lecture The basic component of a digital circuit is the MOS transistor Transistor have instrinsic resistance and capacitance, so voltage values in the circuit take some time to change ( delay ) There
More informationLecture 12 VHDL Synthesis
CPE 487: Digital System Design Spring 2018 Lecture 12 VHDL Synthesis Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030 1 What is Synthesis?
More informationCMPE 415 Verilog CaseStatement Based State Machines II
Department of Computer Science and Electrical Engineering CMPE 415 Verilog CaseStatement Based State Machines II Prof. Ryan Robucci Finite State Machine (FSM) Characterized by A set of states A set of
More informationFederal Urdu University of Arts, Science and Technology, Islamabad VLSI SYSTEM DESIGN. Prepared By: Engr. Yousaf Hameed.
VLSI SYSTEM DESIGN Prepared By: Engr. Yousaf Hameed Lab Engineer BASIC ELECTRICAL & DIGITAL SYSTEMS LAB DEPARTMENT OF ELECTRICAL ENGINEERING VLSI System Design 1 LAB 01 Schematic Introduction to DSCH and
More informationProblem Set 3 Solutions
Problem Set 3 Solutions ECE 551: Digital System Design and Synthesis Fall 2001 Final Version 1) For each of the following always behaviors: a) Does the given always behavior need a default statement as
More informationRegister Transfer Level
Register Transfer Level Something between the logic level and the architecture level A convenient way to describe synchronous sequential systems State diagrams for pros Hierarchy of Designs The design
More informationEN2911X: Reconfigurable Computing Lecture 05: Verilog (2)
EN2911X: Lecture 05: Verilog (2) Prof. Sherief Reda Division of Engineering, Brown University Fall 09 http://scale.engin.brown.edu Dataflow modeling Module is designed by specifying the data flow, where
More informationVHDL And Synthesis Review
VHDL And Synthesis Review VHDL In Detail Things that we will look at: Port and Types Arithmetic Operators Design styles for Synthesis VHDL Ports Four Different Types of Ports in: signal values are readonly
More informationECE 4514 Digital Design II. Spring Lecture 9: Review of Key Ideas, System Commands and Testbenches
ECE 4514 Digital Design II Lecture 9: Review of Key Ideas, System Commands and Testbenches A Language Lecture Iterating the Key Ideas Verilog is a modeling language. It cannot express hardware directly.
More informationChapter 5 Registers & Counters
University of Wisconsin  Madison ECE/Comp Sci 352 Digital Systems Fundamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 Chapter 5 Registers & Counters Originals by: Charles R. Kime Modified for course
More informationLecture 24: Sequential Logic Design. Let s refresh our memory.
18 100 Lecture 24: equential Logic esign 15 L24 1 James C. Hoe ept of ECE, CMU April 21, 2015 Today s Goal: tart thinking about stateful stuff Announcements: Read Rizzoni 12.6 HW 9 due Exam 3 on April
More informationVerilog Overview. The Verilog Hardware Description Language. Simulation of Digital Systems. Simulation of Digital Systems. Don Thomas, 1998, Page 1
The Verilog Hardware Description Language These slides were created by Prof. Don Thomas at Carnegie Mellon University, and are adapted here with permission. The Verilog Hardware Description Language, Fifth
More informationECE 4514 Digital Design II. Spring Lecture 7: Dataflow Modeling
ECE 4514 Digital Design II Lecture 7: Dataflow Modeling A language Lecture Today's topic Dataflow Modeling input input input module output output Model with submodules and gates = Structural Model with
More informationSequential Circuit Design: Principle
Sequential Circuit Design: Principle Chapter 8 1 Outline 1. Overview on sequential circuits 2. Synchronous circuits 3. Danger of synthesizing asynchronous circuit 4. Inference of basic memory elements
More informationVerilog Overview. The Verilog Hardware Description Language. Simulation of Digital Systems. Simulation of Digital Systems. Don Thomas, 1998, Page 1
The Verilog Hardware Description Language These slides were created by Prof. Don Thomas at Carnegie Mellon University, and are adapted here with permission. The Verilog Hardware Description Language, Fifth
More informationMidterm Exam Thursday, October 24, :002:15PM (75 minutes)
Last (family) name: Answer Key First (given) name: Student I.D. #: Department of Electrical and Computer Engineering University of Wisconsin  Madison ECE 551 Digital System Design and Synthesis Midterm
More informationTutorial 3. Appendix D. D.1 Design Using Verilog Code. The RippleCarry Adder Code. Functional Simulation
Appendix D Tutorial 3 This tutorial introduces more advanced capabilities of the Quartus II system. We show how Verilog code is organized and compiled and illustrate how multibit signals are represented
More informationUsing Programmable Logic and the PALCE22V10
Using Programmable Logic and the PALCE22V10 Programmable logic chips (like the PALCE22V10) provide a convenient solution for glue logic and state machine control required by your design. A single PAL chip
More informationCprE 583 Reconfigurable Computing
Recap 4:1 Multiplexer CprE / ComS 583 Reconfigurable Computing Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #18 VHDL for Synthesis I LIBRARY ieee
More informationTopics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 Xilinx FPGAs Chapter 7 Spartan 3E Architecture Source: Spartan3E FPGA Family Datasheet CLB Configurable Logic Blocks Each CLB contains four slices Each slice
More informationHDL Compiler Directives 7
7 HDL Compiler Directives 7 Directives are a special case of regular comments and are ignored by the Verilog HDL simulator HDL Compiler directives begin, like all other Verilog comments, with the characters
More informationECE 353 Lab 4. MIDI Receiver in Verilog. Professor Daniel Holcomb UMass Amherst Fall 2016
ECE 353 Lab 4 MIDI Receiver in Verilog Professor Daniel Holcomb UMass Amherst Fall 2016 Timeline and Grading for Lab 4 Lectures on 11/15 and 11/17 Due on 12/12 Demos in Duda hall Schedule will be posted
More informationLecture 4: Modeling in VHDL (Continued ) EE 3610 Digital Systems
EE 3610: Digital Systems 1 Lecture 4: Modeling in VHDL (Continued ) Sequential Statements Use Process process (sensitivity list) variable/constant declarations Sequential Statements end process; 2 Sequential
More informationRegister Transfer Level in Verilog: Part I
Source: M. Morris Mano and Michael D. Ciletti, Digital Design, 4rd Edition, 2007, Prentice Hall. Register Transfer Level in Verilog: Part I LanDa Van ( 范倫達 ), Ph. D. Department of Computer Science National
More informationVerilog Fundamentals. Shubham Singh. Junior Undergrad. Electrical Engineering
Verilog Fundamentals Shubham Singh Junior Undergrad. Electrical Engineering VERILOG FUNDAMENTALS HDLs HISTORY HOW FPGA & VERILOG ARE RELATED CODING IN VERILOG HDLs HISTORY HDL HARDWARE DESCRIPTION LANGUAGE
More informationECEN 468 Advanced Digital System Design
ECEN 468 Advanced Digital System Design Lecture 22: Verilog Behavioral Description Structural vs. Behavioral Descriptions module my_module(); assign ; // continuous assignment and (); // instantiation
More informationVerilog 1  Fundamentals
Verilog 1  Fundamentals FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1 b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2],
More informationIn this lecture, we will focus on two very important digital building blocks: counters which can either count events or keep time information, and
In this lecture, we will focus on two very important digital building blocks: counters which can either count events or keep time information, and shift registers, which is most useful in conversion between
More informationPollard s Tutorial on Clocked Stuff in VHDL
Pollard s Tutorial on Clocked Stuff in VHDL Welcome to a biased view of how to do register type of stuff in VHDL. The object of this short note is to identify one way to easily handle registered logic
More informationTopics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 ROM (review) Memory device in which permanent binary information is stored. Example: 32 x 8 ROM Five input lines (2 5 = 32) 32 outputs, each representing a memory
More informationSpiral 1 / Unit 4 Verilog HDL. Digital Circuit Design Steps. Digital Circuit Design OVERVIEW. Mark Redekopp. Description. Verification.
14.1 14.2 Spiral 1 / Unit 4 Verilog HDL Mark Redekopp OVERVIEW 14.3 14.4 Digital Circuit Design Steps Digital Circuit Design Description Design and computerentry of circuit Verification Input Stimulus
More informationTiming in synchronous systems
BO 1 esign of sequential logic Outline Timing in synchronous networks Synchronous processes in VHL VHLcode that introduces latches andf flipflops Initialization of registers Mealy and Moore machines
More informationAdvanced Digital Design with the Verilog HDL
Copyright 2001, 2003 MD Ciletti 1 Advanced Digital Design with the Verilog HDL M. D. Ciletti Department of Electrical and Computer Engineering University of Colorado Colorado Springs, Colorado ciletti@vlsic.uccs.edu
More informationHardware Description Languages: Verilog. Quick History of HDLs. Verilog/VHDL. Design Methodology. Verilog Introduction. Verilog.
Hardware Description Languages: Verilog Quick History of HDLs Verilog Structural Models (Combinational) Behavioral Models Syntax Examples CS 150  Fall 2005  Lecture #4: Verilog  1 ISP (circa 1977) 
More informationSynthesis from VHDL. Krzysztof Kuchcinski Department of Computer Science Lund Institute of Technology Sweden
Synthesis from VHDL Krzysztof Kuchcinski Krzysztof.Kuchcinski@cs.lth.se Department of Computer Science Lund Institute of Technology Sweden March 23, 2006 Kris Kuchcinski (LTH) Synthesis from VHDL March
More informationVerilog Lecture Gandhi Puvvada, USC always statements, Coding a FlipFlop. blocking and nonblocking assignments. Copyright 2008 Gandhi Puvvada 1
EE201L and EE560 Verilog Lecture by Gandhi Puvvada, USC always statements, t t Coding a FlipFlop Counters, Basics of Data Path, blocking and nonblocking assignments Copyright 2008 Gandhi Puvvada 1 always
More informationImage Courtesy CS250 Section 2. Yunsup Lee 9/4/09
CS250 Section 2 Image Courtesy www.intel.com Yunsup Lee 9/4/09 Upcoming dates! 9/8/09 (12:30pm)  Lab 1 due (No late days for Lab 1!)! Submit using SVN (source, build, writeup)! 9/8/09  Lab 2 out! Write
More informationFINITE STATE MACHINES (FSM) DESCRIPTION IN VHDL. Cristian Sisterna UNSJ
FINITE STATE MACHINES (FSM) DESCRIPTION IN VHDL UNSJ FSM Review 2 A sequential circuit that is implemented in a fixed number of possible states is called a Finite State Machine (FSM). Finite state machines
More informationLectures 11 & 12: Synchronous Sequential Circuits Minimization
Lectures & 2: Synchronous Sequential Circuits Minimization. This week I noted that our sevenstate edge detector machine on the left side below could be simplified to a fivestate machine on the right.
More informationEECS Components and Design Techniques for Digital Systems. Lec 20 RTL Design Optimization 11/6/2007
EECS 5  Components and Design Techniques for Digital Systems Lec 2 RTL Design Optimization /6/27 Shauki Elassaad Electrical Engineering and Computer Sciences University of California, Berkeley Slides
More informationChapter 9: Sequential Logic Modules
Chapter 9: Sequential Logic Modules Prof. MingBo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog HDL and
More informationECE 545 Lecture 6. Behavioral Modeling of SequentialCircuit Building Blocks. Behavioral Design Style: Registers & Counters.
ECE 55 Lecture 6 Behavioral Modeling of SequentialCircuit Building Blocks Required reading P. Chu, RTL Hardware esign using VHL Chapter 5.1, VHL Process Chapter 8, Sequential Circuit esign: Principle
More informationEE 3170 Microcontroller Applications
EE 3170 Microcontroller Applications Lecture 4 : Processors, Computers, and Controllers  1.2 (reading assignment), 1.31.5 Based on slides for ECE3170 by Profs. Kieckhafer, Davis, Tan, and Cischke Outline
More information