EECS 470 Lab 4. Version Control System. Thursday, 27 th September, 2018

Transcription

1 EECS 470 Lab 4 Version Control System Department of Electrical Engineering and Computer Science College of Engineering niversity of ichigan Thursday, 27 th September, 2018 (niversity of ichigan) Lab 4: VCS Thursday, 27 th September, / 63

2 Administrivia Administrivia Homework I Homework 2 is due Tuesday, 2 nd October I If you haven t, you need to get started now We are available to answer questions on anything here. Office hours can be found in the course web site. (niversity of ichigan) Lab 4: VCS Thursday, 27 th September, / 63

3 Overview Administrivia Git VCS Basics Distributed VCS Git Preliminaries Git Basics by Example Assignment (niversity of ichigan) Lab 4: VCS Thursday, 27 th September, / 63

4 Overview Administrivia Git VCS Basics Distributed VCS Git Preliminaries Git Basics by Example Assignment (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

5 VCS Basics Version Control Systems What is a version control system? I Stores text files I Keeps old versions around I Allows parallel work Why do I care? I Prevents/helps prevent loss of data (nothing is foolproof) I Great for group work I Required for Project 3 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

6 VCS Basics History of VCS otivation Avoid having I isr.v.old I isr.v.old2 I isr.v.working I isr.v.really_working AShortHistory 1950 anual file naming 1982 Revision Control System Local 1986 Concurrent Versions System 2000 Subversion Central 2005 Git Distributed (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

7 Distributed VCS Centralized VCS What does it mean to be centralized? I Clients talk to a server, which is the one, true version I Server copy keeps history I Clients have a(n) (incomplete) working copy (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

8 Distributed VCS Distributed VCS VCS Structure Centralized (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

9 Distributed VCS Distributed VCS What does it mean to be distributed? I Every copy is created equal (can all act as the server) I No one, true version (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

10 Distributed VCS Distributed VCS VCS Structure Distributed (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

11 Distributed VCS Hybrid VCS The Hybrid Approach I se a DVCS I Set up a server to be the synchronization point I Possibly still connect directly to colleagues, but generally not (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

12 Distributed VCS Distributed VCS VCS Structure Hybrid (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

13 Git Preliminaries Subsection 3 Git Preliminaries (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

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15 Git Preliminaries Secure Shell What is ssh? I Secured remote connection to a server, e.g. I Remote shell I How git (should) communicate(s) with other machines What do I need to know? I Requires that you identify yourself: I Key (RSA or DSA) I Password (keyboard-interactive) I Kerberos (gssapi-with-mic) I Necessary for Bitbucket (coming up) (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

16 Git Preliminaries Secure Shell: Keys SSH Keys I Public-private key pair authentication I Can also be password protected ssh-keygen I Creates /.ssh/id_rsa (your private key) and /.ssh/id_rsa.pub (your public key) (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

17 Git Preliminaries Example: ssh-keygen ~] $ ssh-keygen -t rsa -b 4096 Generating public/private rsa key pair. Enter file in which to save the key (/home/wcunning/.ssh/id_rsa): Enter passphrase (empty for no passphrase): Enter same passphrase again: Your identification has been saved in /home/wcunning/.ssh/id_rsa. Your public key has been saved in /home/wcunning/.ssh/id_rsa.pub. The key fingerprint is: 3f:91:f9:7f:d7:be:4e:62:56:27:88:1d:3a:5d:b4:56 wcunning@dahak The key's randomart image is: +--[ RSA 4096] E. o. + B = S B o.+...o.o + o= (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

18 Git Preliminaries Bitbucket What is Bitbucket? I Free, online git repositories I ore friendly to private repos than Github What do I need to know? I sed for Project 3 and the final project I You need to make an account, right now I Once you have an account, add it to this spreadsheet How to make a Bitbucket account... (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

19 Git Preliminaries Git Configuration Follow Along I Run the following commands: I git config --global user.name Your Name I git config --global user. uniqname@umich.edu I Optionally: I Download wcunning-dotfiles.tar.gz I Open it up I Copy.gitconfig and.gitignore to your home directory I Optionally copy other configs/google those programs (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

20 Git Basics by Example Example Execution ~] $ git clone git@bitbucket.org:eecs470staff/course_material.git Cloning into 'course_material'... Warning: Permanently added the RSA host key for IP address ' ' to the list of known hosts. remote: Counting objects: 183, done. remote: Compressing objects: 100% (166/166), done. remote: Total 183 (delta 39), reused 0 (delta 0) Receiving objects: 100% (183/183), KiB 0 bytes/s, done. Resolving deltas: 100% (39/39), done. Checking connectivity... done [wcunning@dahak Documents] $ cd course_material/ [wcunning@dahak project1] [master] $ vim projects/project1/testd.v [wcunning@dahak project1] [master *] $ git add projects/project1/testd.v [wcunning@dahak project1] [master +] $ git commit [master 4caae96] pdated Project 1 to clock); 1 file changed, 11 insertions(+), 11 deletions(-) [wcunning@dahak project1] [master] $ git push Counting objects: 10, done. Delta compression using up to 4 threads. Compressing objects: 100% (5/5), done. Writing objects: 100% (5/5), 544 bytes 0 bytes/s, done. Total 5 (delta 3), reused 0 (delta 0) To git@bitbucket.org:eecs470staff/course_material.git da0cf7a..4caae96 master -> master (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

21 Git Basics by Example Git Basics Introduction Structure For each command you need to know, we will 1. Occasionally, an aside with a Git Concept we need to describe a command 2. Describe the command, along with any useful flags/options 3. Show how the command affects the repositories 4. Show an example with output (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

22 Git Basics by Example Git Diagram Git Repo Structure Commit Tree 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

23 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=9a12490 ark HEAD=9a12490 Will HEAD=9a a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

24 Git Basics by Example Git Commands: clone What does git clone do? I akes a copy of a repository Syntax and Options I Example: git clone <protocol>:/<repo> <directory> Clones the repo at <repo> into <directory> I Repos can be accessed through several different protocols I Git: nsecured, do not use I HTTP(S): sed for freely available things, but push should use the secured version I SSH: The right answer, always secure, likely passwordless (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

25 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=9a12490 ark HEAD=9a12490 Jon HEAD=9a12490 Will HEAD=9a a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

26 Git Basics by Example Git Commands by Example: clone ~] $ git clone git@bitbucket.org:eecs470staff/course_material.git Cloning into '.'... remote: Counting objects: 79, done. remote: Compressing objects: 100% (68/68), done. remote: Total 79 (delta 13), reused 0 (delta 0) Receiving objects: 100% (79/79), KiB, done. Resolving deltas: 100% (13/13), done. (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

27 Git Basics by Example Git Concepts: Working Copy vs. Local Repo What is the working copy? I The files/folders you actually operate on I e.g. group1/ What is the local repo? I The hidden folder containing the stored history for the repo I e.g. group1/.git/ Consequences I.git/ directory is a full repo I seful in the event that you needed a backup I Commits get stored here I Synchronization with the remote is explicit (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

28 Git Basics by Example Git Concepts: Remotes What is a remote? I Remotes are bookmarked repositories to synchronize with Consequences I Clone automatically creates a remote named origin, which is the default for all remote operations (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

29 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=9a12490 ark HEAD=9a12490 Jon* HEAD=9a12490 Will HEAD=9a a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

30 Git Basics by Example Git Concepts: Tracked Files What does it mean for a file to be tracked? I Files that are tracked are stored in the repository Consequences I ntracked files have no history I Tracked files can be compared for changes I Files can be ignored (.gitignore) (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

31 Git Basics by Example Git Commands: status What does git status do? I Shows the contents of the staging area I Shows the files with differences to the most recent commit I Shows the files untracked by git Syntax and Options I Example: git status (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

32 Git Basics by Example Git Commands by Example: status slides] [master *] $ git status # On branch master # Changes not staged for commit: # (use "git add <file>..." to update what will be committed) # (use "git checkout -- <file>..." to discard changes in working directory) # # modified: eecs470lab4slides.tex # (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

33 Git Basics by Example Git Commands: add What does git add do? I If a file is untracked it becomes tracked I Otherwise, the current version is taken as a snapshot and added to the staging area Syntax and Options I Example: git add <files> I <files> can be any normal shell file structure (globs, wildcards, directories, etc.) I if <files> has a directory, it is added recursively I git add interactive: Lets you add files and parts of files from the status output interactively; possibly good for commit building after a complex set of changes (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

34 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=9a12490 ark HEAD=9a12490 Jon+ HEAD=9a12490 Will HEAD=9a a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

35 Git Basics by Example Git Commands by Example: add slides] [master *] $ git add eecs470lab4slides.tex [jbbeau@dahak slides] [master +] $ git status # On branch master # Changes to be committed: # (use git reset HEAD <file>..." to unstage # # modified: eecs470lab4slides.tex # (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

36 Git Basics by Example Git Concepts: Snapshots What is a snapshot? I git add doesn t follow a file in perpetuity I Instead, it saves a snapshot (the state of the file at the time the command was called) Consequences I Files need to be added every time they are changed I Can add only certain files to a commit (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

37 Git Basics by Example Git Concepts: The Staging Area What is the staging area? I Contains the snapshots to be used in creating the next commit Consequences I Commits can be built thematically I Commits can be relatively small, even if changes to be committed are large (useful for git bisect) (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

38 Git Basics by Example Git Commands: commit What does git commit do? I Combines everything in the staging area into a commit, described by your log message I Adds it all to the local repo I Points at it with a commit hash I Changes HEAD to point at that commit hash Syntax and Options I Example: git commit I Interesting things are possible with commit hooks (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

39 Git Basics by Example Git Ettiquette: Commits What is a good commit? I Informative message short one liner followed by thorough paragraphs describing all of the changes I Thematic all of the changes should go together logically (e.g. added amoduleandintegratedit) I Small keeping your changes small makes it easier to find what broke everything by binary searching the commit history (bisect) Why? I All of these rules make it easier to find bugs and understand the progression of a project I ost are mandatory at companies (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

40 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=9a12490 ark HEAD=9a12490 Jon HEAD=f2ea0f5 Will HEAD=9a12490 f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

41 Git Basics by Example Git Commands by Example: commit slides] [master +] $ git commit [master f2ea0f5] Lab 4 diagram change 1 file changed, 1 insertion(+), 1 deletion(-) (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

42 Git Basics by Example Git Commands: push What does git push do? I Puts all of your local commits on some remote Syntax and Options I Example: git push I Defaults to pushing the master branch to the origin repo I Interesting things are possible with push hooks (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

43 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=f2ea0f5 ark HEAD=9a12490 Jon HEAD=f2ea0f5 Will HEAD=9a12490 f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

44 Git Basics by Example Git Commands by Example: push slides] [master] $ git push Counting objects: 11, done. Delta compression using up to 8 threads. Compressing objects: 100% (5/5), done. Writing objects: 100% (6/6), 475 bytes 0 bytes/s, done. Total 6 (delta 3), reused 0 (delta 0) To git@bitbucket.org:eecs470staff/course_material.git 9a f2ea0f5 master -> master (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

45 Git Basics by Example Git Commands: pull What does git pull do? I Gets all commits from some remote I This is actually a combination of git fetch followed by git merge Syntax and Options I Example: git pull I Defaults to pulling the master branch from the origin repo (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

46 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=f2ea0f5 ark HEAD=f2ea0f5 Jon HEAD=f2ea0f5 Will HEAD=f2ea0f5 f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

47 Git Basics by Example Git Commands by Example: pull course_material] [master] $ git pull remote: Counting objects: 13, done. remote: Compressing objects: 100% (7/7), done. remote: Total 8 (delta 2), reused 0 (delta 0) npacking objects: 100% (8/8), done. From bitbucket.org:eecs470staff/course_material 9a f2ea0f5 master -> origin/master (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

48 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=f2ea0f5 ark HEAD=f2ea0f5 Jon HEAD=f2ea0f5 Will* HEAD=f2ea0f5 f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

49 Git Basics by Example Git Commands: reset What does git reset do? I Replaces modified files in the working directory with the versions in the local repo (at some commit hash, generally) Syntax and Options I Example: git reset <hash> <file> I Replaces the contents of <file> with the version in <hash> I <hash> can be specified in relation the HEAD (e.g. HEAD 3) (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

50 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=f2ea0f5 ark HEAD=f2ea0f5 Jon HEAD=f2ea0f5 Will HEAD=f2ea0f5 f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

51 Git Basics by Example Git Commands by Example: reset slides] [master *] $ git status # On branch master # Changes not staged for commit: # (use "git add/rm <file>..." to update what will be committed) # (use "git checkout -- <file>..." to discard changes in working directory) # # deleted: beamerthemelab.sty # no changes added to commit (use "git add" and/or "git commit -a") [wcunning@mycroft-holmes slides] [master *] $ git reset --hard HEAD is now at f2ea0f5 Lab 4 diagram change (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

52 Git Basics by Example Git Commands: branch What does git branch do? I Creates a pointer to a particular commit hash, future commits update this pointer Syntax and Options I Example: git branch <branchname> I Creates a branch named <branchname> starting at the current HEAD (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

53 Git Basics by Example Git Commands: checkout What does git checkout do? I oves the working directory to the specified commit hash or pointer to a commit hash Syntax and Options I Example: git checkout <hash> I <hash> can be I an older commit (e.g. HEAD 2) I a branch, or other pointer, (e.g. lab4) (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

54 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=f2ea0f5 ark HEAD=f2ea0f5 Jon HEAD=f2ea0f5 Will HEAD=f2ea0f5 f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

55 Git Basics by Example Git Commands by Example: branch, checkout slides] [master] $ git branch lab4 [wcunning@mycroft-holmes slides] [master] $ git status On branch master Your branch is up-to-date with 'origin/master'. [wcunning@mycroft-holmes slides] [master] $ git checkout lab4 Switched to branch 'lab4' (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

56 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=f2ea0f5 ark HEAD=f2ea0f5 Jon HEAD=f2ea0f5 Will* HEAD=f2ea0f5 f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

57 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=f2ea0f5 ark HEAD=f2ea0f5 Jon HEAD=f2ea0f5 Will+ HEAD=f2ea0f5 f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

58 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=f2ea0f5 8e4bab6 ark HEAD=f2ea0f5 Jon HEAD=f2ea0f5 Will HEAD=8e4bab6 f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

59 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=f2ea0f5 8e4bab6 ark* HEAD=f2ea0f5 Jon HEAD=f2ea0f5 Will HEAD=8e4bab6 f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

60 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=f2ea0f5 8e4bab6 ark+ HEAD=f2ea0f5 Jon HEAD=f2ea0f5 Will HEAD=8e4bab6 f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

61 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=f2ea0f5 8e4bab6 b73416d ark HEAD=b73416d Jon HEAD=f2ea0f5 Will HEAD=8e4bab6 f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

62 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=f2ea0f5 8e4bab6 b73416d ark* HEAD=b73416d Jon HEAD=f2ea0f5 Will HEAD=8e4bab6 f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

63 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=f2ea0f5 8e4bab6 b73416d ark+ HEAD=b73416d Jon HEAD=f2ea0f5 Will HEAD=8e4bab6 f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

64 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=f2ea0f5 4b3d3cb 8e4bab6 b73416d ark HEAD=4b3d3cb Jon HEAD=f2ea0f5 Will HEAD=8e4bab6 f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

65 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=4b3d3cb 4b3d3cb 8e4bab6 b73416d ark HEAD=4b3d3cb Jon HEAD=f2ea0f5 Will HEAD=8e4bab6 f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

66 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=4b3d3cb 4b3d3cb 8e4bab6 b73416d ark HEAD=4b3d3cb Jon HEAD=f2ea0f5 Will* HEAD=8e4bab6 f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

67 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=4b3d3cb 4b3d3cb 8e4bab6 b73416d ark HEAD=4b3d3cb Jon HEAD=f2ea0f5 Will+ HEAD=8e4bab6 f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

68 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=4b3d3cb 06505f6 4b3d3cb 8e4bab6 b73416d ark HEAD=4b3d3cb Jon HEAD=f2ea0f5 Will HEAD=06505f6 f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

69 Git Basics by Example Git Diagram Git Repo Structure Commit Tree [origin] HEAD=4b3d3cb 06505f6 4b3d3cb 8e4bab6 b73416d ark HEAD=4b3d3cb Jon HEAD=f2ea0f5 Will HEAD=06505f6 f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

70 Git Basics by Example Git Commands: merge What does git merge do? I Combines two branches (when used manually) I Can mangle a repository I Can have conflicts Syntax and Options I Example: git merge lab4 I erges the lab4 branch into the current branch I git mergetool helps you handle merge conflicts I See me in office hours if you need to do this... (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

71 Git Basics by Example Git Diagram Git Repo Structure Commit Tree a [origin] HEAD=4b3d3cb 06505f6 4b3d3cb 8e4bab6 b73416d ark HEAD=4b3d3cb Jon HEAD=f2ea0f5 Will HEAD=a f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

72 Git Basics by Example Git Commands by Example: merge slides] [master $] $ git merge lab4 pdating f2ea0f5..25cbbce Fast-forward.gitignore labs/lab4/assignment/tex/eecs470lab4assignment.tex 2 +- labs/lab4/slides/eecs470lab4slides.tex labs/lab4/slides/script.txt labs/lab4/slides/ssh-keygen.txt files changed, 841 insertions(+), 11 deletions(-) create mode gitignore create mode labs/lab4/slides/script.txt create mode labs/lab4/slides/ssh-keygen.txt (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

73 Git Basics by Example Git Commands: tag What does git tag do? I Creates an additional pointer to a particular commit hash Syntax and Options I Example: git tag -a <tagname> <hash> I Creates a pointer to <hash> called <tagname> I This pointer can be checked out just like a branch I Tags are local by default, push with git push <tagname> (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

74 Git Basics by Example Git Diagram Git Repo Structure Commit Tree lab4 a [origin] HEAD=4b3d3cb 06505f6 4b3d3cb 8e4bab6 b73416d ark HEAD=4b3d3cb Jon HEAD=f2ea0f5 Will HEAD=a f2ea0f5 9a12490 (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

75 Git Basics by Example Git Commands by Example: merge w14] [master] $ git tag -a lab4-release HEAD [wcunning@mycroft-holmes w14] [master] $ git push origin lab4-release Counting objects: 1, done. Writing objects: 100% (1/1), 187 bytes 0 bytes/s, done. Total 1 (delta 0), reused 0 (delta 0) To git@bitbucket.org:eecs470staff/course_material.git * [new tag] lab4-release -> lab4-release [wcunning@mycroft-holmes w14] [master] $ git tag -l lab4-release (niversity of ichigan) Lab 4: VCS Friday, Sept. 29 th, / 63

76 Bitbucket Guide Bitbucket Account Setup 1. Go to Bitbucket Sign p 2. Fill out the form. I Preferably, use your uniqname as your username I se address I Choose Personal Account 3. Click on the little silhouette of a person in the upper right corner. 4. Select anage Account from the list. 5. Click on SSH Keys in the list on the left. 6. Click on Add Key. 7. In the pop up, paste the contents of /.ssh/id_rsa.pub, and name the key whatever you would like. 8. Check that this worked by running 9. Add your Bitbucket username to the spreadsheet. (niversity of ichigan) Lab 4: VCS Thursday, 27 th September, / 63

77 Verisimple Pipeline Same basic pipeline as book/class If need more info: Appendix A of the book Need to add hazard logic to a simple five stage pipeline Given pipeline without hazard detection or forwarding logic Programs still run because only one instruction is allowed in the pipeline at a time

78 Fetch Decode Execute emory WB 1 PC + Inst mem PC+1 instruction rega regb data Register file R0 R1 R2 R3 R4 R5 R6 R7 0 PC+1 vala valb offset + A L target eq? AL result valb Data memory AL result mdata op op op IF/ ID fwd fwd fwd ID/ E E/ em em/ WB

79 Verisimple Pipeline Forwarding Like what covered in class Need to forward results from later stages to E Structural Hazards Only one memory port for fetch and memory accesses emory gets priority over fetch Control Hazards Predict not taken, resolved in E stage Flush IF/ID, ID/E, E/E if incorrect

80 Alpha ISA Project 3 and your final project will use a subset of the Alpha ISA You ll have a decode stage given to you that works for Project 3 You may need to make very minor changes to it for your final project Just to add additional signals that your design may consider useful For example a functional unit selection bit Alpha has 32 architected registers $r0 - $r31. $r31 is always read as 0, writes have no effect Self-modifying code isn t valid All registers must be written before being read

81 Instructions General format addq $r1, $r2, $r3 $r1 + $r2 $r3 In many cases second register can be an immediate value addq $r1, 0x5, $r3 $r1 + 0x5 $r3 Load/Store format ldq $r2, 0x10($r3) E[$r3+ 0x10] $r2

82 Logic and Arithmetic Instruction List addq $r1, $r2, $r3 Add $r1 + $r2 $r3 subq $r1, $r2, $r3 Subtract $r1 - $r2 $r3 and $r1, $r2, $r3 AND $r1 & $r2 $r3 bic $r1, $r2, $r3 ANDNOT $r1 & ~$r2 $r3 bis $r1, $r2, $r3 OR $r1 $r2 $r3 ornot $r1, $r2, $r3 ORNOT $r1 ~$r2 $r3 eqv $r1, $r2, $r3 EQV (ORNOT) $r1 ~^ $r2 $r3 srl $r1, $r2, $r3 Right Shift Logical $r1 >> $r2 $r3 sll $r1, $r2, $r3 Left Shift Logical $r1 << $r2 $r3 sra $r1, $r2, $r3 Right Shift Arithmetic $r1 >>> $r2 $r3 mulq $r1, $r2, $r3 ultiply $r1 * $r2 $r3 lda $r3, const($r1) Load Address $r1 + const $r3

83 emory & Compare Instruction List ldq $r3, 5($r1) Load E[$r1+5] $r3 stq $r3, 5($r1) Store E[$r1+5] $r3 cmpeq $r1, $r2, $r3 Compare Equal $r1 == $r2? 1 $r3 : 0 $r3 cmplt $r1, $r2, $r3 Compare Less than Signed $r1 < $r2? 1 $r3 : 0 $r3 cmple $r1, $r2, $r3 cmpult $r1, $r2, $r3 cmpule $r1, $r2, $r3 Compare Less or Equal Signed Compare Less than nsigned Compare Less or Equal nsigned $r1 <= $r2? 1 $r3 : 0 $r3 $r1 < $r2? 1 $r3 : 0 $r3 $r1 <= $r2? 1 $r3 : 0 $r3

84 Control Instruction List beq $r3, target Branch if $r3 == 0 $r3 == 0? target PC : NPC PC bne $r3, target Branch if $r3!= 0 $r3!= 0? target PC : NPC PC ble $r3, target Branch if $r3 <= 0 $r3 <= 0? target PC : NPC PC blt $r3, target Branch if $r3 < 0 $r3 < 0? target PC : NPC PC bge $r3, target Branch if $r3 >= 0 $r3 >= 0? target PC : NPC PC bgt $r3, target Branch if $r3 > 0 $r3 > 0? target PC : NPC PC blbc $r3, target Branch if $r3[0] == 0 $r3[0] == 0? target PC : NPC PC blbs $r3, target Branch if $r3[0] == 1 $r3[0] == 1? target PC : NPC PC

85 Control and Link Instruction List br $r31, target Branch target PC; PC $r31 bsr $r31, target Branch Subroutine target PC; PC $r31 jmp $r26, ($r3) Jump PC $r26; $r3 & ~3 PC jsr $r26, ($r3) Jump Subroutine PC $r26; $r3 & ~3 PC ret $r26, ($r3) Return PC $r26; $r3 & ~3 PC jsr_cr $r26, ($r3) Jump Coroutine PC $r26; $r3 & ~3 PC

86 Halt call_pal 0x555 Halt achine Halts

87 Directory Structure akefile - Just like you ve seen before program.mem - Assembled code to run synth - Directory where synthesis output will be created. Also contains synthesis script sys_defs.vh - Constants used throughout code (acros) testbench - Directory with testbench, memory, and pipeline printing code test_progs - Selection of programs to test your pipeline with verilog lines of verilog to implement pipeline vs-asm - Program to assemble test programs into program.mem

88 Running the Code Assemble a test program:./vs-asm test_prog/testname.s > program.mem Running the code: make or./simv (if you already ran make)

89 evens.s data = 0x1000 lda $r2,0 //r2=0 lda $r3,data //r3=data loop1: blbs $r2,loop2 //if($r3[0]==1) PC=loop2 stq $r2,0($r3) //mem[r3+0]=r2 addq $r3,0x8,$r3 //r3+=8 loop2: addq $r2,0x1,$r2 //r2+=1 cmple $r2,0xf,$r1 //r1=(r2<=0xf) bne $r1,loop1 //if(r1!=0) PC=loop1 call_pal 0x555 //halt

90 Output program.out - Output of memory of pipeline pipeline.out - Text file of which PC/instruction is in each stage as well as bus activity writeback.out - PC and what (if anything) is being written to the RF from the WB stage

91 program.out nified emory contents hex on left, decimal on right: mem[ 0] = 207f f0000 : mem[ 8] = b f : mem[ 16] = : mem[ 24] = f43ffffa4041fda1 : mem[ 32] = mem[ 4104] = : mem[ 4112] = : mem[ 4120] = : mem[ 4128] = : mem[ 4136] = a : mem[ 4144] = c : mem[ 4152] = e : System halted on @@ 415 cycles / 82 instrs = ns total time to

92 pipeline.out Cycle: IF ID E E WB 0: 4:lda 0:- 0:- 0:- 0:- 1: 8:- 4:lda 0:- 0:- 0:- 2: 8:- 8:- 4:lda 0:- 0:- 3: 8:- 8:- 8:- 4:lda 0:- 4: 8:- 8:- 8:- 8:- 4:lda 5: 8:lda 8:- 8:- 8:- 8:- 6: 12:- 8:lda 8:- 8:- 8:- 7: 12:- 12:- 8:lda 8:- 8:- 8: 12:- 12:- 12:- 8:lda 8:- 9: 12:- 12:- 12:- 12:- 8:lda 10: 12:blbs 12:- 12:- 12:- 12:- 11: 16:- 12:blbs 12:- 12:- 12:- 12: 16:- 16:- 12:blbs 12:- 12:- 13: 16:- 16:- 16:- 12:blbs 12:- 14: 16:- 16:- 16:- 16:- 12:blbs 15: 16:stq 16:- 16:- 16:- 16:- 16: 20:- 16:stq 16:- 16:- 16:-... Remember, P3 starts with 1 insn at a time going through the pipeline

93 pipeline.out Continued D-E Bus & Reg Result BS_LOAD E[8] accepted 1 BS_LOAD E[16] accepted 1 BS_LOAD E[16] accepted 1 BS_STORE E[4096] = 0 accepted 1 BS_LOAD E[16] accepted 1 BS_LOAD E[16] accepted 1 BS_LOAD E[16] accepted 1 BS_LOAD E[16] accepted 1 BS_LOAD E[16] accepted 1 r3=4104 BS_LOAD E[16] accepted 1 BS_LOAD E[16] accepted 1 BS_LOAD E[24] accepted 1 BS_LOAD E[24] accepted 1 BS_LOAD E[24] accepted 1 BS_LOAD E[24] accepted 1

94 writeback.out PC= , REG[ 2]= PC= , REG[ 3]= PC= , --- PC= c, --- PC= , REG[ 3]= PC= , REG[ 2]= PC= , REG[ 1]= PC= c, --- PC= , --- PC= , REG[ 2]= PC= , REG[ 1]= PC= c, --- PC= , --- PC= c, --- PC= , REG[ 3]= PC= , REG[ 2]= PC= , REG[ 1]=

95 Checking your solution You can compare memory portion of code we give you against your output. CPI, cycles, ns, will be different emory and writeback output should be the same Like the code you ve been given, should always halt on halt instruction At some point your code probably won t because you messed something up Pay attention to that output

96 Checking your solution We ll also post some pipeline/program/writeback output on the website Your output, and our output should match exactly You can use the program diff to check that they do diff <our output> <your output>

97 VeriSimple Pipeline Specifics

98 Fetch Stage

99 Fetch Stage Code assign PC_plus_4 = PC_reg + 4; assign next_pc = ex_mem_take_branch? ex_mem_target_pc : PC_plus_4; assign if_npc_out = PC_plus_4; // This register holds the PC value clock) begin if(reset) PC_reg <= SD 0; // initial PC value is 0 else if(pc_enable) PC_reg <= SD next_pc; // transition to next PC end // always // This FF controls the stall signal that artificially forces // fetch to stall until the previous instruction has completed // This must be removed for Project 3 clock) begin if (reset) if_valid_inst_out <= SD 1; // must start with something else if_valid_inst_out <= SD mem_wb_valid_inst; end

100 Decode Stage

101 Decode Stage Code // Instantiate the register file used by this pipeline regfile regf_0 (...) // instantiate the instruction decoder decoder decoder_0 (...) // mux to generate dest_reg_idx based on // the dest_reg_select output from decoder always_comb begin case (dest_reg_select) DEST_IS_REGC: id_dest_reg_idx_out = rc_idx; DEST_IS_REGA: id_dest_reg_idx_out = ra_idx; DEST_NONE: id_dest_reg_idx_out = ZERO_REG; default: id_dest_reg_idx_out = ZERO_REG; endcase end

102 Execute Stage

103 Execute Stage Code always_comb begin case (id_ex_opa_select) AL_OPA_IS_REGA: opa_mux_out = id_ex_rega; AL_OPA_IS_E_DISP: opa_mux_out = mem_disp; AL_OPA_IS_NPC: opa_mux_out = id_ex_npc; AL_OPA_IS_NOT3: opa_mux_out = ~64 h3; endcase end always_comb begin opb_mux_out = 64 hbaadbeefdeadbeef; case (id_ex_opb_select) AL_OPB_IS_REGB: opb_mux_out = id_ex_regb; AL_OPB_IS_AL_I: opb_mux_out = alu_imm; AL_OPB_IS_BR_DISP: opb_mux_out = br_disp; endcase end alu alu_0 (...) brcord brcond (...) assign ex_take_branch_out = id_ex_uncond_branch id_ex_cond_branch & brcond_result;

104 emory Stage

105 emory Stage Code // Determine the command that must be sent to mem assign proc2dmem_command = ex_mem_wr_mem? BS_STORE : ex_mem_rd_mem? BS_LOAD : BS_NONE; // The memory address is calculated by the AL assign proc2dmem_data = ex_mem_rega; assign proc2dmem_addr = ex_mem_alu_result; // Assign the result-out for next stage assign mem_result_out = (ex_mem_rd_mem)? Dmem2proc_data : ex_mem_alu_result;

106 Writeback Stage

107 Writeback Stage Code // ux to select register writeback data: // AL/E result, unless taken branch, in which case we write // back the old NPC as the return address. Note that ALL branches // and jumps write back the link value, but those that don t // want it specify ZERO_REG as the destination. assign result_mux = (mem_wb_take_branch)? mem_wb_npc : mem_wb_result; // Generate signals for write-back to register file // reg_wr_en_out computation is sort of overkill since the reg file // has a special way of handling ZERO_REG but there is no harm // in putting this here. Hopefully it illustrates how the pipeline works. assign reg_wr_en_out = mem_wb_dest_reg_idx!= ZERO_REG; assign reg_wr_idx_out = mem_wb_dest_reg_idx; assign reg_wr_data_out = result_mux;

108 emory arbitration

109 emory arbitration code assign proc2mem_command = (proc2dmem_command== BS_NONE)? BS_LOAD : proc2dmem_command; assign proc2mem_addr = (proc2dmem_command== BS_NONE)? proc2imem_addr : proc2dmem_addr;

110 Pipeline register clock) begin if(reset) begin if_id_npc <= SD 0; if_id_ir <= SD NOOP_INST; if_id_valid_inst <= SD FALSE; end // if (reset) else if (if_id_enable) begin if_id_npc <= SD if_npc_out; if_id_ir <= SD if_ir_out; if_id_valid_inst <= SD if_valid_inst_out; end // if (if_id_enable) end // always

111 Project 3 Goals Branches should resolve in the same stage they are currently resolved in. All forwarding must be to the E stage, even if the data isn t needed until a later stage. Any stalling due to data hazards must occur in the decode stage. (That is, if stalling is required the dependent instruction should stall in the decode stage.) Obviously, instructions following the stalling instruction in the IF stage will have to stay in the IF stage. Put another way, if you need to insert an invalid instruction, it should be inserted in the E stage (as was done in the slides in the first few lectures this semester.) If you wish to insert a noop you must invalidate the instruction. Otherwise your CPI numbers will be wrong. If there is a structural hazard in the memory, you should let the load/store go and have the fetch stage wait on getting memory.

112 Project 3 Goals Branches should resolve in the same stage they are currently resolved in. All forwarding must be to the E stage, even if the data isn t needed until a later stage. Any stalling due to data hazards must occur in the decode stage. (That is, if stalling is required the dependent instruction should stall in the decode stage.) Obviously, instructions following the stalling instruction in the IF stage will have to stay in the IF stage. Put another way, if you need to insert an invalid instruction, it should be inserted in the E stage (as was done in the slides in the first few lectures this semester.) If you wish to insert a noop you must invalidate the instruction. Otherwise your CPI numbers will be wrong. If there is a structural hazard in the memory, you should let the load/store go and have the fetch stage wait on getting memory.

113 Project 3 Goals Branches should resolve in the same stage they are currently resolved in. All forwarding must be to the E stage, even if the data isn t needed until a later stage. Any stalling due to data hazards must occur in the decode stage. (That is, if stalling is required the dependent instruction should stall in the decode stage.) Obviously, instructions following the stalling instruction in the IF stage will have to stay in the IF stage. Put another way, if you need to insert an invalid instruction, it should be inserted in the E stage (as was done in the slides in the first few lectures this semester.) If you wish to insert a noop you must invalidate the instruction. Otherwise your CPI numbers will be wrong. If there is a structural hazard in the memory, you should let the load/store go and have the fetch stage wait on getting memory.

114 Sample Code add ; reg 3 = reg 1 + reg 2 nand ; reg 5 = reg 3 ~& reg 4 add ; reg 7 = reg 6 + reg 3 lw ; reg 6 = em[reg ] sw ; em[reg6+12] = reg 2

115 PC Inst mem Register file A L 1 Data memory + + IF/ ID ID/ E E/ em em/ WB op offset valb vala PC+1 1 target AL result op valb op AL result mdata eq? add R2 R3 R4 R5 R1 R6 R0 R7 rega regb data

116 PC Inst mem Register file A L 1 Data memory + + IF/ ID ID/ E E/ em em/ WB add target AL result op valb op AL result mdata eq? nand R2 R3 R4 R5 R1 R6 R0 R7 rega regb data

117 Hazard PC Inst mem Register file A L 1 Data memory + + IF/ ID ID/ E E/ em em/ WB add nand R2 R3 R4 R5 R1 R6 R0 R7 rega regb data 3 3

118 PC Inst mem Register file A L 1 Data memory + + IF/ ID ID/ E E/ em em/ WB nand add add R2 R3 R4 R5 R1 R6 R0 R7 rega regb 5 data 3 H1

119 New Hazard PC Inst mem Register file A L 1 Data memory + + IF/ ID ID/ E E/ em em/ WB nand add add R2 R3 R4 R5 R1 R6 R0 R7 rega regb 5 data 3 H

120 PC Inst mem Register file A L 1 Data memory + + IF/ ID ID/ E E/ em em/ WB add nand add 21 lw R2 R3 R4 R5 R1 R6 R0 R7 rega regb data H2 H1

121 PC Inst mem Register file A L 1 Data memory + + IF/ ID ID/ E E/ em em/ WB add nand add 21 lw R2 R3 R4 R5 R1 R6 R0 R7 rega regb data H2 H1 3 No Hazard 21 1

122 Project 3 Goals Branches should resolve in the same stage they are currently resolved in. All forwarding must be to the E stage, even if the data isn t needed until a later stage. Any stalling due to data hazards must occur in the decode stage. (That is, if stalling is required the dependent instruction should stall in the decode stage.) Obviously, instructions following the stalling instruction in the IF stage will have to stay in the IF stage. Put another way, if you need to insert an invalid instruction, it should be inserted in the E stage. If you wish to insert a noop you must invalidate the instruction. Otherwise your CPI numbers will be wrong. If there is a structural hazard in the memory, you should let the load/store go and have the fetch stage wait on getting memory.

123 Sample Code add ; reg 3 = reg 1 + reg 2 nand ; reg 5 = reg 3 ~& reg 4 add ; reg 7 = reg 6 + reg 3 lw ; reg 6 = em[reg ] sw ; em[reg6+12] = reg 2

124 PC Inst mem Register file A L 1 Data memory + + IF/ ID ID/ E E/ em em/ WB lw add nand -2 sw R2 R3 R4 R5 R1 R6 R0 R7 rega regb 7 5 data H2 H1 6

125 PC Inst mem Register file A L 1 Data memory + + IF/ ID ID/ E E/ em em/ WB lw add nand -2 sw R2 R3 R4 R5 R1 R6 R0 R7 rega regb data H2 H1 Hazard 6 en en L

126 PC Inst mem Register file A L 1 Data memory + + IF/ ID ID/ E E/ em em/ WB 5 31 lw add 22 sw R2 R3 R4 R5 R1 R6 R0 R7 rega regb 6 7 data H2 noop

127 PC Inst mem Register file A L 1 Data memory + + IF/ ID ID/ E E/ em em/ WB noop 5 31 lw add 22 sw R2 R3 R4 R5 R1 R6 R0 R7 rega regb 6 7 data H2 Hazard 6

128 PC Inst mem Register file A L 1 Data memory + + IF/ ID ID/ E E/ em em/ WB sw noop lw R2 R3 R4 R5 R1 R6 R0 R7 rega regb 6 data H3

129 PC Inst mem Register file A L 1 Data memory + + IF/ ID ID/ E E/ em em/ WB sw noop lw R2 R3 R4 R5 R1 R6 R0 R7 rega regb 6 data H

130 PC Inst mem Register file A L 1 Data memory + + IF/ ID ID/ E E/ em em/ WB 111 sw 7 noop R2 R3 R4 R5 R1 R6 R0 R7 rega regb data H3

131 Project 3 Goals Branches should resolve in the same stage they are currently resolved in. All forwarding must be to the E stage, even if the data isn t needed until a later stage. Any stalling due to data hazards must occur in the decode stage. (That is, if stalling is required the dependent instruction should stall in the decode stage.) Obviously, instructions following the stalling instruction in the IF stage will have to stay in the IF stage. Put another way, if you need to insert an invalid instruction, it should be inserted in the E stage. If you wish to insert a noop you must invalidate the instruction. Otherwise your CPI numbers will be wrong. If there is a structural hazard in the memory, you should let the load/store go and have the fetch stage wait on getting memory.

132 Project 3 Goals Branches should resolve in the same stage they are currently resolved in. All forwarding must be to the E stage, even if the data isn t needed until a later stage. Any stalling due to data hazards must occur in the decode stage. (That is, if stalling is required the dependent instruction should stall in the decode stage.) Obviously, instructions following the stalling instruction in the IF stage will have to stay in the IF stage. Put another way, if you need to insert an invalid instruction, it should be inserted in the E stage. If you wish to insert a noop you must invalidate the instruction. Otherwise your CPI numbers will be wrong. If there is a structural hazard in the memory, you should let the load/store go and have the fetch stage wait on getting memory.

133 PC Inst mem Register file A L 1 Data memory + + IF/ ID ID/ E E/ em em/ WB noop 5 31 lw add 22 sw R2 R3 R4 R5 R1 R6 R0 R7 rega regb 6 7 data H2 Hazard 6