CS 152 Computer Architecture and Engineering

Transcription

1 CS 152 Computer rchitecture and Engineering Lecture 10 Pipelining III John Lazzaro ( Ts: Ted Hong and David arquardt www-inst.eecs.berkeley.edu/~cs152/

2 Last time: Hazard Taxonomy Structural Hazards Data Hazards (RW, WR, WW) Control Hazards (taken branches and jumps) On each clock cycle, we must detect the presence of all of these hazards, and resolve them before they break the contract with the programmer.

3 Last Time: Hazard Resolution Toolkit Stall earlier instructions in pipeline. Forward results computed in later pipeline stages to earlier stages. dd new hardware or rearrange hardware design to eliminate hazard. Change IS to eliminate hazard. Kill earlier instructions in pipeline. ake hardware handle concurrent requests to eliminate hazard.

4 Today: Putting it ll Together Specifications for Lab 3 t-risk hazards for Lab 3 Preferred hazard resolution tools. Tips for control design

5 Lab 3: IS Specifications lso: RESET signal, BREK release signal, etc... Single delay slot No load delay slot

6 Hazard Diagnosis

7 Data Hazards: WR and WW... Write fter Read (WR) hazards. Instruction I2 expects to write over a data value after an earlier instruction I1 reads it. But instead, I2 writes too early, and I1 sees the new value. Write fter Write (WW) hazards. Instruction I2 writes over data an earlier instruction I1 also writes. But instead, I1 writes after I2, and the final data value is incorrect. WR and WW not possible in our 5-stage pipeline. However, T test code checks for these, and every semester a few WR/WWs are found. Why?

8 + What would cause a WW/WR here? IF (Fetch) ID (Decode) EX (LU) E WB, emtoreg ux,logic op D PC Q 0x4 ddr Instr em Data RegFile rs1 rs2 rd1 ws rd2 wd L U Y Data emory ddr Dout Din emtoreg R Ext B

9 Data Hazards: Read fter Write Read fter Write (RW) hazards. Instruction I2 expects to read a data value written by an earlier instruction, but I2 executes too early and reads the wrong copy of the data. Lab 3 solution: use forwarding heavily, fall back on stalling when forwarding won t work or slows down the critical path too much.

10 Full bypass network... ID (Decode) EX E, emtoreg WB ux,logic From WB op rs1 rs2 RegFile rd1 L U Y Data emory ddr Dout Din emtoreg R ws wd rd2 Ext B

11 Common bug: ultiple forwards... DD R4,R3,R2 Which do we forward from? OR R2,R3,R1 ND R2,R2,R1 ID (Decode) EX E, emtoreg WB ux,logic rs1 rs2 ws wd RegFile rd1 rd2 From WB op L U Y Data emory ddr Dout Din emtoreg R Ext B

12 LW and Hazards

13 Questions about LW and forwarding DDIU R1 R1 24 Will this work as shown? ID (Decode) OR R3,R3,R2 LW R1 128(R29) EX E WB, emtoreg ux,logic rs1 rs2 ws wd RegFile rd1 rd2 From WB op L U Y Data emory ddr Dout Din emtoreg R Ext B

14 Questions about LW and forwarding DDIU R1 R1 24 Will this work as shown? LW R1 128(R29) ID (Decode) EX OR R1,R3,R1 E, emtoreg WB ux,logic rs1 rs2 ws wd RegFile rd1 rd2 From WB op L U Y Data emory ddr Dout Din emtoreg R Ext B

15 Resolving a RW hazard by stalling Stage #1 Stage #2 Stage #3 Instr Fetch Decode & Reg Fetch Sample program DD R4,R3,R2 OR R5,R4,R2 + D PC Q 0x4 ddr Instr em Data OR R5,R4,R2 Keep executing OR instruction until R4 is ready. Until then, send NOPS to 2/3. rs1 rs2 ws wd RegFile rd1 rd2 DD R4,R3,R2 Let DD proceed to WB stage, so that R4 is written to regfile. New datapath hardware (1) ux into 2/3 to feed in NOP. Freeze PC and until stall is over. Ext B (2) Write enable on PC and 1/2

16 Branches and Hazards

17 + Recall: Control hazard and hardware Stage #1 Stage #2 Stage #3 Instr Fetch Decode & Reg Fetch To branch control logic == 0x4 RegFile D PC Q ddr Instr em Data rs1 rs2 ws wd rd1 rd2 Ext B

18 + Recall: fter more hardware, change IS IF (Fetch) ID (Decode) EX (LU) E WB 0x4 D PC Q ddr Instr em Data If we change IS, can we always let I2 complete ( branch delay slot ) and eliminate the control hazard. Sample Program Time: t1 t2 t3 t4 t5 t6 t7 t8 (IS w/o branch Inst ID stage delay slot) I1: IF ID EX E WB computes I2: IF if branch I1: BEQ R4,R3,25 I3: is taken I2: ND R6,R5,R4 I4: I3: SUB R1,R9,R8 If branch is taken, this I5: instruction UST NOT I6: complete!

19 Questions about branch and forwards ux,logic BEQ R1 R3 label Will this work as shown? To branch control logic ID (Decode) == OR R3,R3,R1 EX E, emtoreg WB op RegFile rs1 rs2 rd1 ws rd2 wd L U Y Data emory ddr Dout Din emtoreg R Ext B

20 Why might this be hard? BEQ R1 R3 l3 BEQ R1 R3 l2 ID (Decode) EX E, emtoreg WB ux,logic op RegFile rs1 rs2 rd1 L U Y Data emory ddr Dout Din emtoreg R ws wd rd2 Ext B

21 Lessons learned Pipelining is hard Study every instruction Write test code in advance Think about interactions...

22 Control Implementation

23 Recall: What is single cycle control? ddr Instr em Data Equal Combinational Logic (Only Gates, No Flip Flops) Just specify logic functions! RegDest RegWr ExtOp LUsrc emwr emtoreg PCSrc RegDest RegFile rs1 rs2 rd1 ws rd2 wd Ext LUctr op L U Equal Data emory ddr Dout Din RegWr ExtOp LUsrc emwr emtoreg

24 In pipelines, all registers are used ID (Decode) EX E WB Equal Combinational Logic (Only Gates, No Flip Flops) (add extra state outside!) RegDest RegWr ExtOp emtoreg PCSrc conceptual design -- for shortest critical path, registers may hold decoded info, not the complete -bit instruction

25 Two goals when specifying control logic Bug-free: One 0 that should be a 1 in the control logic function breaks contract with the programmer. Efficient: Logic function specification should map to hardware with good performance properties: fast, small, low power, etc. Should be easy for humans to read and understand: sensible signal names, symbolic constants...

26 dmin: Design Document Deadlines

27 dmin: Team Evaluations due Thursday lso: Homework 1 is now posted.

28 Lectures: Coming up next... Tools for understanding memory arrays.