Simulation of the Hello World Application for the Field-programmable Port Extender (FPX)

Transcription

1 Simulation of the Hello World Application for the Field-programmable Port Extender (FPX) John W. Lockwood, Washington University, Applied Research Lab Spring 2001 Gigabit Kits Workshop Supported by NSF-ANI and Xilinx Corp Field Programmable Port Extender (FPX) 1 The HelloWorld Testbench Visit Download HelloWorld Testbench Right-click on HelloTestbench.tar Save Target in: D:\fpx\ Access Files in Cygwin Bash Shell Start > Programs > Cygwin > Bash cd /cygdrive/d/fpx/ tar xvf HelloTestbench.tar cd HelloTestbench.tar ls Field Programmable Port Extender (FPX) 2

2 Problem Statement General Statement Implement a plug-in module that monitors a traffic flow. For cells with payloads that begin with Hello, have the module replace the following bytes with World. Details Scan Flows on VCI=5 Match the content of the cell for the HELLO ASCII: HELLO Hex: C 4C 4F Binary: 0100, , , , ,1111 Replace following contents with WORLD. ASCII WORLD. Hex: 57 4F 52 4C 44 2E Binary: 0101, , , , , ,1110 Field Programmable Port Extender (FPX) 3 Hello, World Module Function Compare Header [5 bytes in 2 words] Payload [48 bytes in 12 words] JWL:ARL 07/00 VPI VCI=5 VPI=X VCI=5 PAD PAD H E L L H E L L Match O P5 P6 P7 P8 P9 P10 P11.. Payload.... Payload.. P44 P45 P46 P47 P44 P45 P46 P47 32 bits Match O W O Match+Write R L D. Write Copy Copy Field Programmable Port Extender (FPX) 4

3 Case 1: Mismatched VCI Compare VPI VCI!=5 VPI=X VCI!=5 Mismatch H E L L O PAD P5 P6 P7 P8 P9 P10 P11.. Payload.. H E L L O P8 PAD P5 P6 P7 P9.. Payload.. P10 P11 Copy P44 P45 P46 P47 P44 P45 P46 P47 Copy JWL:ARL 07/00 Only process Cells on the selected VCI All other flows should pass unchanged Field Programmable Port Extender (FPX) 5 Case 2: Mismatched Source String Compare VPI VCI=5 VPI=X VCI=5 Match M E L L O PAD P5 P6 P7 P8 P9 P10 P11.. Payload.. M E L L O P8 PAD P5 P6 P7 P9.. Payload.. P10 P11 Mismatch+Copy Copy P44 P45 P46 P47 P44 P45 P46 P47 Copy JWL:ARL 07/00 Cell payload must contain HELLO in payload. MELLO HELLO Field Programmable Port Extender (FPX) 6

4 Case 3: Mismatched Source String [word 2] Compare VPI VCI=5 VPI=X VCI=5 Match H E L L P PAD P5 P6 P7 P8 P9 P10 P11.. Payload.. PAD H E L L Match P P5 P6 P7 Mismatch+Copy P8 P9.. Payload.. P10 P11 P44 P45 P46 P47 P44 P45 P46 P47 Copy JWL:ARL 07/00 Payload must match over entire string. Data arrives as streaming words Field Programmable Port Extender (FPX) 7 Logical Implementation VCI Match Append WORLD to payload New Cell Field Programmable Port Extender (FPX) 8

5 Manifest of Files in HelloTestbench.tar File: Contains: README.txt: General Information Makefile: Build and complile programs TESTCELL.DAT: Cells written into simulation (Hex) CELLSOUT.DAT: Data written out from simulation Hex.txt: HEX/ASCII Table fake_nid_in.vhd: Utilities to save cells to file fake_nid_out.vhd: Utility to read cells from file top.vhd: Top level design helloworld.vhd: Top-level helloworld design pins.ucf: Pin mapping for RAD FPGA Field Programmable Port Extender (FPX) 9 Module Implementation D_MOD_IN[31:0] SOC_MOD_IN TCA_MOD_OUT Data Interface D_MOD_OUT[31:0] SOC_MOD_OUT TCA_MOD_IN X SRAM_GR SRAM_D_IN[35:0] X SDRAM_GR SDRAM_DATA[63:0] CLK RESET_L ENABLE_L Module Logic SRAM Interface SDRAM Interface Module Interface XSRAM_REQ SRAM_D_OUT[35:0] SRAM_ADDR[17:0] SRAM_RW XSDRAM_REQ SDRAM_DATA[63:0] SRAM_ADDR[17:0] SRAM_RW READY_L Field Programmable Port Extender (FPX) 10

6 Hello, World Entity RAD NID Field Programmable Port Extender (FPX) 11 TestBench configuration TESTCELL.DAT top Clk Reset NID_Out NID_In soc Data tcaff soc Data tcaff HelloWorld CELLSOUT.DAT Field Programmable Port Extender (FPX) 12

7 Contents of TESTCELL.DAT wait 10 Pause before sending cell new_cell Indicate Beginning of cell a Cell Header = { VPI[12]:VCI[16]:PT[4] } 00FFFFFF Cell Header = { HEC[8]:Pad[24] } 48454C4C Payload [ 48 Bytes ] 4F FFFF wait 10 Pause before sending cell Field Programmable Port Extender (FPX) 13 Source: Architecture -- Hello World: Sample FPX Application -- Operates as Ingress (switch-side) cell processor of RAD -- Copyright: July 2000, John Lockwood, David Lim -- Washington University, Applied Research Lab architecture Hello_arch of HelloWorld is type state_type is (rst, dout, hell_check, o_check, world); signal state, nx_state : state_type; signal counter, nx_counter : std_logic_vector (3 downto 0); signal CEN, nx_cen : std_logic; signal BData_Out : std_logic_vector (31 downto 0); signal BData_in : std_logic_vector (31 downto 0); signal BSOC_In : std_logic; signal BTCA_In : std_logic; signal BSOC_Out : std_logic; signal BTCA_Out : std_logic; signal clkin : std_logic; Field Programmable Port Extender (FPX) 14

8 Source: Cell Counter counter_process: process (CEN, counter) begin if CEN = 0 then nx_counter <= "0001"; else nx_counter <= unsigned (counter) + 1; end if; end process; Field Programmable Port Extender (FPX) 15 Source: State transitions -- State Transitions state_machine_process: process (BSOC_In, state, counter, BData_In, rad_reset, CEN) begin if ( rad_reset = 1 ) then nx_state <= rst; nx_cen <= 0 ; elsif ( BSOC_In = 1 and BData_In(19 downto 4) = " " ) then -- checks to see if VCI = 5, if so: next check payload nx_state <= hell_check; nx_cen <= 1 ; elsif ( BSOC_In = 1 and BData_In(19 downto 4) /= " " ) then -- VCI!= 5 nx_state <= dout; nx_cen <= 1 ; Field Programmable Port Extender (FPX) 16

9 Source: Output Data -- Upper 16-bits of Data Output DataOut_31downto16_process: process (clkin) begin if clkin event and clkin = 1 then -- checks to see if the intput data has the letter "O if ( state = o_check and BData_In(31 downto 24) =" " ) then -- writes out "O " for the higher two bytes of the output BData_Out(31 downto 16) <= " "; -- ("O ") elsif ( state = world and counter = "0100" ) then BData_Out(31 downto 16) <= " "; -- ("RL") elsif ( state = dout or state=hell_check or BSOC_In = '1' ) then BData_Out(31 downto 16) <= BData_In(31 downto 16); Field Programmable Port Extender (FPX) 17 Source: Next State Assignments BData_Out_process: process (clkin) begin -- buffer signal assignments: if clkin'event and clkin = '1' then d_sw_rad <= BData_Out; -- (Data_Out = d_sw_rad) BData_in <= d_sw_nid; -- (Data_In = d_sw_nid) BSOC_In <= soc_sw_nid; -- (SOC_In = soc_sw_nid) BSOC_Out <= BSOC_In; BTCA_In <= tcaff_sw_nid; -- (TCA_In = tcaff_sw_nid) BTCA_Out <= BTCA_In; counter <= nx_counter; -- next state assignments state <= nx_state; -- next state assignments: Field Programmable Port Extender (FPX) 18

10 Simulation Make newsim First step Make comp Compile all VHD designs Make sim Simulate top-level design Add wave * Run 2000 Right-click on din, dout : Set Radix to ASCII Field Programmable Port Extender (FPX) 19 Viewing Signals with Modelsim Display top-level signals [Modelsim window] Add Wave * Display components [View menu] > Structure Select component Click on: helloworld [hello_arch] View signals on that component [View menu] > signals Select signals to view [Signals View menu] > Wave > Signals in design Run simulation [Modelsim window] > run 2000 Field Programmable Port Extender (FPX) 20

11 Hex / ASCII Table [See your Handout!] "Hex.txt" 34 lines, 1776 characters Hx Symbol (Function) Hx Char Hx Char Hx Char NUL (null) 20 SPACE SOH (start of head) 21! 41 A 61 a 02 STX (start of text) 22 " 42 B 62 b 03 ETX (end of text) 23 # 43 C 63 c 04 EOT (end of trans) 24 $ 44 D 64 d 05 ENQ (enquiry) 25 % 45 E 65 e 06 ACK (acknowledge) 26 & 46 F 66 f 07 BEL (bell) G 67 g 08 BS (backspace) 28 ( 48 H 68 h 09 TAB (horizontal tab) 29 ) 49 I 69 i 0A LF (line feed) 2A * 4A J 6A j 0B VT (vertical tab) 2B + 4B K 6B k 0C FF (form feed) 2C, 4C L 6C l 0D CR (carriage ret) 2D - 4D M 6D m 0E SO (shift out) 2E. 4E N 6E n 0F SI (shift in) 2F / 4F O 6F o 10 DLE (escape) P 70 p 11 DC1 (devcontrol 1) Q 71 q 12 DC2 (devcontrol 2) R 72 r 13 DC3 (devcontrol 3) S 73 s 14 DC4 (devcontrol 4) T 74 t 15 NAK (nak) U 75 u 16 SYN (synch idle) V 76 v 17 ETB (end of block) W 77 w 18 CAN (cancel) X 78 x 19 EM (end of medium) Y 79 y 1A SUB (substitute) 3A : 5A Z 7A z 1B ESC (escape) 3B ; 5B [ 7B { 1C FS (file separator) 3C < 5C \ 7C 1D GS (group sep) 3D = 5D ] 7D } 1E RS (record sep) 3E > 5E ^ 7E ~ 1F US (unit sep) 3F? 5F _ 7F DEL Field Programmable Port Extender (FPX) 21 Exercises Simulate cell on VCI=5 with content: HELLO Process first cell in TESTCELL.DAT Simulate cell on VCI=6 with content: HELLO Simulate cell on VCI=5 with content: MELLO Modify the simulation input to inject cell with YELLOW (sp) Modify state machine to search for YELLOW Field Programmable Port Extender (FPX) 22

12 Implementation [Homework] Front-end Synthesis Map VHDL constructs into LUTs Tools FPGA Express (Xilinx Alliance) Synplicity More.. Back-end Tools Xilinx Place Route Bitgen Field Programmable Port Extender (FPX) 23 FPGA: Design Flow VHDL EDIF BIT VHDL Design Synplicity Xilinx Download Xilinx bit file to FPX FPGA Timing Logical Simulation Verification Application groups develop RAD module Compile of Architecture Synthesize into LUT functions Route and place into CLB Array Verify timing of circuit to 100 MHz Field Programmable Port Extender (FPX) 24

13 I/O Definitions (Pins.UCF) ## File: rad.ucf ## Backend constraints file for ## RAD FPGA ## Switch (SW) Side Module ## DataIn (Linecard interface, from NID) NET d_sw_nid(0) LOC=B31; NET d_sw_nid(1) LOC=C31; NET d_sw_nid(2) LOC=C32; (see paper) ## DataOut (Linecard interface, from RAD) NET d_sw_rad(0) LOC=B20; NET d_sw_rad(1) LOC=B21; NET d_sw_rad(2) LOC=E22; (see paper) ## Start of Cell NET soc_sw_rad LOC=D27; NET soc_sw_nid LOC=A32; ## TCA NET tcaff_sw_nid LOC=B26; NET tcaff_sw_rad LOC=D39; ## clock NET rad_clk LOC=AW19; ## Reset NET rad_reset LOC=B30; Field Programmable Port Extender (FPX) 25 Hello, World Silicon Layout View Field Programmable Port Extender (FPX) 26

14 FPGA Routing and Placement Detail Silicon Process Highly regular Configurable Logic Block (CLB) Two slices/clb Two LUTs/slice Dense routing Between modules GRM Short lines Long Lines Reprogrammable SRAM Pass Transistors Field Programmable Port Extender (FPX) 27 Post-Synthesis Signal Timing Start_of_cell (SOC): Buffered across Edge flops data_in : VCI=5, Payload= HELLOEEO data_out : HELLO WORLD. Field Programmable Port Extender (FPX) 28

15 Results: Performance Operating Frequency: 119 MHz. 8.4ns critical path Well within the 10ns period RAD's clock. Targeted to RAD s V1000E-FG680-7 Maximum packet processing rate: 7.1 Million packets per second. (100 MHz)/(14 Clocks/Cell) Circuit handles back-to-back packets Field Programmable Port Extender (FPX) 29 Results: Chip Utilization Slice utilization: 1% (49/12,288 slices) Details Edge Flops: DataIn + DataOut + SOCs + TCAs = = 68 Internal Flops : BufferedData + SOCs + TCAs + state + counter = =42 Field Programmable Port Extender (FPX) 30

16 Conclusions "Hello World Illustrates: Example of simple hardware module implemented on the the RAD. Starting point for new application development. FPX provides Simple and efficient platform to implement certain types of cell and packet processing operations. Hardware handles 7.1 Million packets/second Software Functions: Should be done on SPC Interesting Ideas for Future Work Hardware/software co-design Example: Send matching packets to software for processing. Field Programmable Port Extender (FPX) 31 Hello, World References FPX Homepage Hello World Handout John Lockwood, David Lim, "Hello World: A simple application for the Field Programmable Port Extender (FPX), Washington University, Department of Computer Science, Technical Report WUCS-00-12, July 11, Hello World Testbench FPX Tool Environment Field Programmable Port Extender (FPX) 32