ILP: COMPILER-BASED TECHNIQUES
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1 ILP: COMPILER-BASED TECHNIQUES Mahdi Nazm Bojnordi Assistant Professor School of Computing University of Utah CS/ECE 6810: Computer Architecture
2 Overview Announcements Homework 2 will be released on Sept. 26 th This lecture Program execution Loop optimization Superscalar pipelines Software pipelining
3 Big Picture Goal: improving performance Software (ILP and IC) Hardware (IPC) Inst. Fetch Inst. Decode Execute Memory Access Write back
4 Big Picture Goal: improving performance Software (ILP and IC) Performance = (IPC x F) / IC Hardware (IPC) Inst. Fetch Inst. Decode Execute Memory Access Write back
5 Big Picture Goal: improving performance Software (ILP and IC) Hardware (IPC) Performance = (IPC x F) / IC Increasing IPC: 1. Improve ILP 2. Exploit more ILP Increasing F: 1. Deeper pipeline 2. Faster technology Inst. Fetch Inst. Decode Execute Memory Access Write back
6 Big Picture Goal: improving performance Software (ILP and IC) Performance = (IPC x F) / IC Hardware (IPC) Increasing IPC: 1. Improve ILP 2. Exploit more ILP Increasing F: 1. Deeper pipeline 2. Faster technology Code gen. Architecture Circuit/Device Inst. Fetch Inst. Decode Execute Memory Access Write back
7 Big Picture Goal: improving performance Software (ILP and IC) Hardware (IPC) Architectural Techniques: - Deep pipelining - Ideal speedup = n times - Exploiting ILP - Dynamic scheduling (HW) - Static scheduling (SW) Inst. Fetch Inst. Decode Execute Memory Access Write back
8 Processor Pipeline Necessary cycles between dependent instructions
9 Processor Pipeline Necessary cycles between dependent instructions Producer Consumer Stalls Load Any Inst. 1 fp.alu Store 2 fp.alu Any other 3 int.alu Branch 1
10 Program Loop book-keeping overheads Producer Consumer Stalls Load Any Inst. 1 fp.alu Store 2 fp.alu Any other 3 int.alu Branch 1 Goal: adding s to all of the array elements m: s:
11 Program Loop book-keeping overheads do { m[i] = m[i] + s; i = i - 1; } while(i!= j) Producer Consumer Stalls Load Any Inst. 1 fp.alu Store 2 fp.alu Any other 3 int.alu Branch 1 Goal: adding s to all of the array elements m: s:
12 Program Loop book-keeping overheads S.D F4, 0(R1) DADDUI R1, R1, #-8 BNE R1, R2, Loop do { m[i] = m[i] + s; i = i - 1; } while(i!= j) Producer Consumer Stalls Load Any Inst. 1 fp.alu Store 2 fp.alu Any other 3 int.alu Branch 1 Goal: adding s to all of the array elements m: s:
13 Execution Schedule Diverse impact of cycles on performance S.D F4, 0(R1) DADDUI R1, R1, #-8 BNE R1, R2, Loop Producer Consumer Stalls Load Any Inst. 1 fp.alu Store 2 fp.alu Any other 3 int.alu Branch 1 S.D F4, 0(R1) DADDUI R1, R1, #-8 BNE R1, R2, Loop Schedule 1: 5 cycles 3 loop body instructions 2 loop counter instructions
14 Loop Optimization
15 Loop Optimization Re-ordering and changing immediate values S.D F4, 0(R1) DADDUI R1, R1, #-8 BNE R1, R2, Loop Schedule 1: 5 cycles 3 loop body instructions 2 loop counter instructions
16 Loop Optimization Re-ordering and changing immediate values DADDUI R1, R1, #-8 BNE R1, R2, Loop S.D F4, 8(R1) Schedule 2: 1 cycle 3 loop body instructions 2 loop counter instructions S.D F4, 0(R1) DADDUI R1, R1, #-8 BNE R1, R2, Loop Schedule 1: 5 cycles 3 loop body instructions 2 loop counter instructions
17 Loop Unrolling Reducing loop overhead by unrolling DADDUI R1, R1, #-8 BNE R1, R2, Loop S.D F4, 8(R1) Goal: adding s to all of the array elements Schedule 2: 1 cycle 3 loop body instructions 2 loop counter instructions m: s:
18 Loop Unrolling Reducing loop overhead by unrolling DADDUI R1, R1, #-8 BNE R1, R2, Loop S.D F4, 8(R1) do { m[i-0] = m[i-0] + s; m[i-1] = m[i-1] + s; m[i-2] = m[i-2] + s; m[i-3] = m[i-3] + s; i = i-4; } while(i!= j) Goal: adding s to all of the array elements Schedule 2: 1 cycle 3 loop body instructions 2 loop counter instructions m: s:
19 Loop Unrolling Reducing loop overhead by unrolling S.D F4, 0(R1) L.D F6, -8(R1) ADD.D F8, F6, F2 S.D F8, -8(R1) L.D F10,-16(R1) ADD.D F12, F10, F2 S.D F12, -16(R1) L.D F14, -24(R1) Schedule ADD.D 2: F16, F14, F2 1 S.D cycle F16, -24(R1) 3 loop DADDUI body R1, instructions R1, #-32 2 loop BNE counter R1,R2, instructions Loop m: s: do { m[i-0] = m[i-0] + s; m[i-1] = m[i-1] + s; m[i-2] = m[i-2] + s; m[i-3] = m[i-3] + s; i = i-4; } while(i!= j) Goal: adding s to all of the array elements
20 Loop Unrolling Reducing loop overhead by unrolling S.D F4, 0(R1) L.D F6, -8(R1) ADD.D F8, F6, F2 S.D F8, -8(R1) L.D F10,-16(R1) ADD.D F12, F10, F2 S.D F12, -16(R1) L.D F14, -24(R1) ADD.D F16, F14, F2 S.D F16, -24(R1) DADDUI R1, R1, #-32 BNE R1,R2, Loop Schedule 3: 14 cycles 12 loop body instructions 2 loop counter instructions
21 Instruction Reordering Eliminating cycles by unrolling and scheduling S.D F4, 0(R1) L.D F6, -8(R1) ADD.D F8, F6, F2 S.D F8, -8(R1) L.D F10,-16(R1) ADD.D F12, F10, F2 S.D F12, -16(R1) L.D F14, -24(R1) ADD.D F16, F14, F2 S.D F16, -24(R1) DADDUI R1, R1, #-32 BNE R1,R2, Loop L.D F6, -8(R1) L.D F10,-16(R1) L.D F14, -24(R1) ADD.D F8, F6, F2 ADD.D F12, F10, F2 ADD.D F16, F14, F2 S.D F4, 0(R1) S.D F8, -8(R1) DADDUI R1, R1, #-32 S.D F12, 16(R1) BNE R1,R2, Loop S.D F16, 8(R1)
22 IPC Limit Eliminating cycles by unrolling and scheduling Schedule 4: 0 cycles 12 loop body instructions 2 loop counter instructions + IPC = 1 - more instructions - more registers L.D F6, -8(R1) L.D F10,-16(R1) L.D F14, -24(R1) ADD.D F8, F6, F2 ADD.D F12, F10, F2 ADD.D F16, F14, F2 S.D F4, 0(R1) S.D F8, -8(R1) DADDUI R1, R1, #-32 S.D F12, 16(R1) BNE R1,R2, Loop S.D F16, 8(R1)
23 IPC Limit Eliminating cycles by unrolling and scheduling IPC>1? Schedule 4: 0 cycles 12 loop body instructions 2 loop counter instructions + IPC = 1 - more instructions - more registers L.D F6, -8(R1) L.D F10,-16(R1) L.D F14, -24(R1) ADD.D F8, F6, F2 ADD.D F12, F10, F2 ADD.D F16, F14, F2 S.D F4, 0(R1) S.D F8, -8(R1) DADDUI R1, R1, #-32 S.D F12, 16(R1) BNE R1,R2, Loop S.D F16, 8(R1)
24 Summary of Scalar Pipelines Upper bound on throughput IPC <= 1 Unified pipeline for all functional units Underutilized resources Inefficient freeze policy A cycle delays all the following cycles Pipeline hazards Stall cycles result in limited throughput
25 Superscalar Pipelines
26 Superscalar Pipelines Separate integer and floating point pipelines An instruction packet is fetched every cycle n Very large instruction word (VLIW) Inst. packet has one fp. and one int. slots Compiler s job is to find instructions for the slots IPC <= 2 i.if i.id i.ex i.ma i.wb fp.if fp.id fp.ex fp.wb
27 Superscalar Pipelines Forming instruction packets L.D F6, -8(R1) L.D F10,-16(R1) L.D F14, -24(R1) ADD.D F8, F6, F2 ADD.D F12, F10, F2 ADD.D F16, F14, F2 S.D F4, 0(R1) S.D F8, -8(R1) DADDUI R1, R1, #-32 S.D F12, 16(R1) BNE R1,R2, Loop S.D F16, 8(R1) Floating-point operations
28 Superscalar Pipelines Ideally, the number of empty slots is zero L.D F6, -8(R1) L.D F10,-16(R1) L.D F14, -24(R1) DADDUI R1, R1, #-32 S.D F4, 32(R1) S.D F8, 24(R1) S.D F12, 16(R1) BNE R1,R2, Loop S.D F16, 8(R1) NOP NOP ADD.D ADD.D ADD.D ADD.D NOP NOP NOP NOP F4, F0, F2 F8, F6, F2 F12, F10, F2 F16, F14, F2
29 Superscalar Pipelines Ideally, the number of empty slots is zero L.D F6, -8(R1) L.D F10,-16(R1) L.D F14, -24(R1) DADDUI R1, R1, #-32 S.D F4, 32(R1) S.D F8, 24(R1) S.D F12, 16(R1) BNE R1,R2, Loop S.D F16, 8(R1) NOP NOP ADD.D ADD.D ADD.D ADD.D NOP NOP NOP NOP F4, F0, F2 F8, F6, F2 F12, F10, F2 F16, F14, F2 Schedule 5: 0 cycles 8 loop body packets 2 loop overhead cycles IPC = 1.4
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