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1 ! )! # & ) * + * + * & *,+,-

2 Update Instruction Address IA Instruction Fetch IF Instruction Decode ID Execute EX Memory Access ME Writeback Results WB Program Counter Instruction Register Register File MUX PC Update Instruction Cache Decoder Execution Units Data Cache MUX Forwarding Paths! * - * - +/ + + / * + & 2001 r1r2 + r3 r3mem[r1 + 8] r5r3 - r4 Cycle IA IF ID EX ME WB IA IF ID EX ME WB IA IF ID EX ME WB Figure 2 Three instructions flow down a pipeline; the first forwards data to the second as shown with an arrow) The second instruction first stalls for one cycle, then forwards data to the third * + 3 # # # 2!!#!3#3 # )2/456/7584 # #

3 * / 9, 9,!*4: ; VLIW Functional Unit Instr Fetch Decode Functional Unit Memory Access Register File Memory Access # # ; <-= * : * + * >? * : >? >?

4 Physical Register Files) Branch Predictor I-cache Fetch buffer Decode Pipeline Issue F D Register Rename D Buffer I Exec Unit Exec Unit D Exec Unit to I-cache Load Queue Store Queue L1 Data Cache MSHRs L2 Cache to main memory Reorder Buffer Window) & R!& * : * * : 3) 3)3) >? 3)

5 !!) * : * A 3) 3) * B ** 3) 3) C & * B * place exceptions in entry mark entry when complete reserve entry at tail when dispatched Exceptions Reg Mapping Prog Counter r7 p5 r3 p6 Store remove from head if complete; STOP if exception present Complete 1 0 Figure 5 Reorder buffer; instructions are dispatched into the tail and exit from the head only after they have completed 3) **

6 6 3 3)) * : ) 6 +, D * 4 * loop: Static Instructions r3 memr4+r2) r7 memr5+r2) r7 r7 * r3 r1 r1-1 memr6+r2) r7 r2 r2 + 8 PC loop; r1!=0 Branch Predict & Fetch Dynamic Instruction Stream r3 memr4+r2) r7 memr5+r2) r7 r7 * r3 r1 r1-1 memr6+r2) r7 r2 r2 + 8 PC loop; r1!=0 r3 memr4+r2) r7 memr5+r2) r7 r7 * r3 r1 r1-1 memr6+r2) r7 r2 r2 + 8 PC loop; r1!=0 Figure 6 A block of instructions on the left) are fetched with the benefit of branch prediction) to form the dynamic instruction stream shown at right A branch instruction appears as an assignment to the program counter PC) ; * 7 >? *

7 ) * 7 * 7 :- + : A * 7 8 & / & /8 / 8 * 8 r3 memr4+r2) r7 memr5+r2) Register MAP r1 p3 r2 p4 r3 p6 r4 p1 r5 p2 r6 p7 r7 p5 a) r3 memp1+p4) r3 memr4+r2) r7 memr5+r2) Register MAP r1 p3 r2 p4 r3 p8 r4 p1 r5 p2 r6 p7 r7 p5 b) p8 memp1+p4) p9 memp2+p4) Free Pool p8,p9,p10,p11,p12,p13, p14,p15,p16,p17,p18, P19,p20,p21,p22,p23,p24 Figure 7 The register renaming process a) first source registers access the logical-to-physical register map to find their current mappings b) then the first physical register in the free pool is assigned to the result register and the register map table is updated DA : * : 6,E /,E + B

8 * 8 * Renamed Stream dispatch issue complete commit p8 memp1+p4) p9 memp2+p4) p10 p9 * p p11 p memp7+p4)p p12 p PC loop; p11!= p13 memp1+p12) p14 memp2+p12) p15 p14 * p p16 p memp7+p12) p p17 p PC loop; p16!= p18 memp1+p17) p19 memp2+p17) p20 p19 * p p21 p memp7+p17) p p22 p Figure 8 Three iterations of the example instruction stream after renaming Dispatch, issue, complete, and commit cycles illustrate out-of-order instruction issue and in-order instruction commit # B 43 * 7 / & -/!# /B!# C /B!# ; -

9 3) * B * 8 * F * 3)+4* 8 +F 3)!#B# 3) 3) 3) 3) * Register MAP r1 p21 r2 p22 r3 p18 r4 p1 r5 p2 r6 p7 r7 p20 Restore Register Map Register MAP r1 p16 r2 p17 r3 p18 r4 p1 r5 p2 r6 p7 r7 p14 Exceptions Reg Mapping Prog Counter 0000 r2 p17 6C r1 r7 p16 p19 60 r7 p14 5C Restore Program Counter 5C Store Complete tail head Figure 9 Example of ROB restoring architected state after an exception The instruction at the head of the ROB has an exception The register mapping and PC are backed up, and the pending store instruction is flushed!/ 01##2,+ 6 #-

10 3 * D ),6 * 4 * 8 D 6 * +5 6,,),) &,- 2 ; 3 2 ;3 * * +5 3) & 3) )

11 MSHRs Data from Memory Miss to Memory Instruction Issue hit/miss Address Generation Loads MUX L1 Data Cache Data on hit) MUX Data to Processor TLB Store-to- Load Forward Data Load Address Buffer Enable Store-to-Load Forward Address Compare store addresses store data Store Commit from ROB store data Pending Complete Store Queue Commit Stores Coalescing) Store Buffers Figure 10 L1 data cache and buffering subsystem that allow load/store reordering with forwarding of load data * ; * +5

12 +& -& 2E1 / * ++ G *- H H*+ D * 8 address from Address Generation Logic store address load address load address Load Address Queue address SQ tag pending Compare1 tag match & pending Compare 2 address match & valid Enable Forward1 Store-to-Load Forward Data1 Enable Forward2 data tag from pipeline control logic store data from execution units store data address data Store-to-Load Forward Data2 Commit from ROB valid Store Queue Figure 11 Detailed drawing of load/store buffering and comparison logic

13 * +- * ++ #,H G address from Address Generation Logic load address Load Address Queue address address store address SQ tag SQ tag Commit from ROB pending forwarded Compare3 address match & not forwarded flush/restart data tag from pipeline control logic store data from execution units store data address data Commit from ROB valid Store Queue Figure 12 Portion of load/store unit that implements speculative issuing of load instructions before prior store addresses are known # </-=* <//=!!!+2

14 * * * 8 * 6 / D * 3 #+ 3) CI I *0<-5= C *!! Issue Width Linear Relationship Linear Relationship Linear Relationship ~ Quadratic Relationship I-Fetch Resources aciheved width) Commit Width Numbers of Functional Units ROB Size Linear Relationships Issue Buffer Size # Rename Registers Load/Store Buffer Sizes +

15 @ 3 Processor Intel Core IBM Power4 MIPS R10000 Table 1 The relationship between window size ROB) and issue width for some real processors Intel PentiumPro Alpha AMD Opteron HP PA-8000 Intel Pentium 4 Reorder Buffer Size Issue Buffer Size Issue Width log 2 ROB) log 2 Issue Width) Issue Buffer Size ROB Size A * +/ 3) 6 * : 6+4 & / </:= #+ / 3! * 7#+ &

16 * - ) G / 3! THE 6600 BARREL AND SLOT +F45,E! ## 4455 </B= ## 4455 A ##4455!! +B 44556!! 0!!!!,E!!& >?>?3* +:!!&!!!!& A!!!!*!!& )!!,E *

17 I/O Programs in Barrel Memory Latency = 1 Barrel Rotation PC reg0 reg1 regn-1 SLOT Time-shared instruction control PC reg0 reg1 regn-1 ALU DENELCOR HEP Figure 14 CDC 6600 Barrel and Slot multi-threading ;0!</=;0! * +B ;0! 3 2*! opcode Scheduler Function Unit Main Memory PSW Queue PSW Instruction Memory reg addresses Register Memory operands Increment Delay nonmemory insts memory insts PSW Buffer pending memory results Function Units Figure 15 Block diagram of the Denelcor HEP 3 * +B!! 0!!

18 &!#!!! 2 6!!#!!! ;0!+-5!! ;! /!! ##4455!! ;0!2 ) 3)6 * +4! : # 2 <4=! : * +4 </4= -

19 L1 Cache Store Buffer I-Fetch Uop Queue Rename Queue Sched Register Read Execute Register Write Commit Prog Counters Trace Cache Allocate Registers Data Cache Reorder Buffer Figure 16 Intel Pentium 4 hyperthreading Registers,3E * +7 * * +7 address TId tag offset V TId tag data Compare == hit/miss Figure 17 A thread identifier TId) separates the entries belonging to different threads in a shared buffer or memory 3)6 D

20 >? ; )!/ 2 6 * * * & >?>?*D * +8 * D

21 3 * +8D D D Objectives Policies Mechanisms Capacity Resource Bandwidth Resource Capacity Resource Bandwidth Resource Figure 18 Objectives, policies, and mechanisms 4!5 D 6 D 6 D D 6 D D * DD PERFORMANCE D D * D! D *

22 @ FAIRNESS >? *! : <4= D & >? 4455!!! : 2 & <-7= & A K )& * & <+5= >? * D * D D D! : >?* )&<-+= ISOLATION )

23 6 # D D IMPLEMENTING OBJECTIVES * +8D D D 2 C>?</7= *! :! :! : ) /B/ )2!B D /!

24 BANDWIDTH SHARING ) + + J! : CAPACITY SHARING * +7!! :! :* +F! :,

25 Instruction Fetch Instruction Dispatch Instruction Issue Read Registers Execute Memory Access Write-Back Commit Program Counters Mechanisms part shared part part part part shared shared shared shared shared Round- Robin PRE-EMPTION Uop queue tracecache Round- Robin Rename/ Allocation Tables Issue Buffers FR-FCFS Policies Registers Execution part Ld/St Buffers shared Data Cache Figure 19 Pentium 4 hyper-threading mechanisms and policies shared shared Registers! FEEDBACK MECHANISMS & ; A POLICY COORDINATION D * -5 * part Round- Robin part ROB

26 bandwidth resource capacity resource bandwidth resource capacity resource bandwidth resource capacity resource bandwidth resource Local Policy Local Policy Local Policy Local Policy Local Policy Local Policy Local Policy Global Policy Figure 20 Local policies manage local resources in accordance with a global policy * -+ bandwidth resource capacity resource bandwidth resource capacity resource bandwidth resource capacity resource bandwidth resource Policy Feedback Figure 21 A policy may incorporate a feedback mechanism that monitors the status at a later pipeline stage SCHEDULING GRANULARITY + + # * -- D Monitor Status *

27 ! * --; ;0!##4455!!! : * issue width cycles cycles cycles a) coarse-grain b) fine-grain c) simultaneous Figure 22 Multi-threaded scheduling policies G G 2 2 * -- 2 *! : G! : * +F ; THREAD SELECTION, ) 4455!! 33

28 -G,3E ; /G 0 /,* *#* ; *3*#*! : 1G WORK CONSERVATION J *! : J #! :! : CAPACITY POLICIES #B ) -

29 )!! : # * F#+ #B!2!#! ) J # * -/ >? * -/ * -/ # + 4

30 cache misses pipeline stalls thread 1 thread 2 fine-grain MT coarsegrain MT time clock cycles) Figure 23 Scheduling of two threads with fine-grain round-robin scheduling and coarse-grain switch-on-event scheduling E * * ; * -/ )23 4:9 /B+ D * -: * -:; * -: ;0!

31 thread 1 thread 2 fine-grain MT time clock cycles) Figure 24 Fine-grain multithreading of pipelines without forwarding hardware There are more gaps due to stalls in the individual threads However, fine-grain multi-threading is able to fill in most of the gaps #!2! A SCHEDULING GRANULARITY * -B # branch misprediction cache miss Processor Instructions per Cycle Figure 25 Superscalar processors instruction execution is interspersed with miss events branch mispredictions and cache/tlb misses) A *,+,+ *,-,+,-,)

32 J<+5=,- /55,+ # * )23 4:9 /B+2 </8=,/ <-8= & *,+! : 2 SINGLE THREAD POLICIES D * +/0 *

33 @ L&* * 4: * Total Issue Buffer Size Active Threads Figure 26 Relationship between the number of active threads and the aggregate issue buffer size D D * D FETCH UNIT MECHANISMS AND POLICIES # &

34 D * 2 ; * </F= </4= E 2 2 D 6 ; 2</4= ) <B= ; D 2 )2!B INSTRUCTION ISSUE

35 A 2<+:= /034* -7 #EA #EA#EA 6 5 Instructions per Cycle Round Robin ICOUNT Threads Figure 27 Performance comparison of Round-Robin and ICOUNT fetch policies in an 8-way SMT prrocessor from [reference]) RETIREMENT POLICIES A3) ** 3) 3) 3) )2!B FAIRNESS POLICIES D /:+ * ) 3

36 D D <-/= <+5= * )& <-+= * #EA EXPLICIT PRIORITY POLICIES ; *!B /B/ * /!05!2! ) 5 </5= / 36 *

37 /*7 )23 4:9!!# 3 4:9 Update Instruction Address IA Instruction Fetch IF Instruction Decode ID Execute EX Memory Access ME Writeback Results WB Program Counter Instruction Buffer 16) Register File MUX PC Update Instruction Cache Decoder Execution Units Data Cache Branch Target Buffer 8) MUX Forwarding Paths Thread Switch Buffer 8) Figure 28 The IBM RS64 IV pipeline has conventional in-order pipeline stages It is a 4-way superscalar processor and has instruction buffers to reduce branch misprediction and thread switch delays!!# : B * -8)! : 3 4:9! * #3 # D,+,-,) ),-,+,+,-,+,+,-

38 @,),) # * -8 * -F,+ + ) A +& cycles: Load 1 IA IF inst buffer ID EX ME WB Inst 1 IA IF inst buffer ID EX ME Inst 2 IA IF thread switch buffer ID EX ME WB miss => flush; thread-switch 3 cycle switch penalty Figure 29 Thread switch timing on a data cache miss The processor is 4-way superscalar, but to simplify the figure this is not shown * /5 2,+ +7M -

39 L1 Cache Misses IERAT Misses TLB Misses L2 Cache Misses Timeout Priority Miscellaneous 9 13 Figure 30 Causes for thread switches The IERAT serves as an instruction TLB BM 8992 EAA <+-=A ),++4N8N /2,- ; A #42! A Instruction Fetch IF Thread Select TS Instruction Decode ID Execute EX Memory Access ME Writeback Results WB Select Logic PC Instruction Buffers Select Logic Register File 4 threads MUX Store Buffers partitioned) PCs 4 threads Instruction Cache 2 Decoder Execution Units Data Cache MUX Instruction types Misses Traps Resource conflicts Thread Select Policy Forwarding Paths Figure 31 Block diagram of SUN Niagara multi-threaded processor pipeline A * /+,E, 6,

40 !#,3E G # & * / ,3E + -5 & 5# 5 + A/ ; 5 5 / 5

41 cycles: load 0 TS ID EX ME WB add 1 TS ID EX ME WB load 1 TS ID EX ME WB add 0 ID EX ME WB TS hit/ miss? forward Figure 32 Example of Niagara thread scheduling The add instruction from thread 0 is issued speculatively assuming thread 0s load hits in the data cache) / : )2!B!B!: 0!B!B 2!B +87B2),-,/ #4 * // D G -:!B ** ) * *#*

42 Instruction Fetch Instruction Dispatch Instruction Issue Read Registers Execute Memory Access Write-Back Commit Mechanisms pooled part pooled part part part part pooled pooled pooled pooled pooled Branch Predictors Program Counters Round- Robin I-cache Priority Inst Buffers Dispatch Policy Rename Tables Issue Buffers FCFS Registers Execution Load Miss Queue occupancy part Ld/St Buffers pooled Data Cache pooled pooled Registers GCT occupancy Round- Robin pooled GCT Policies Figure 33 Resource management diagram for IBM /-: * // 0, * /: 0 5+ Figure 34 Thread performance for different setting of thread priorities in the IBM Power5

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